coreboot-gerrit August 2021

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Change in coreboot[master]: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig
by Subrata Banik (Code Review) 16 Aug '21

16 Aug '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48344 ) Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ...................................................................... soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig List of changes: 1. Default select USE_CAR_NEM_ENHANCED_V1 to use the existing algorithm 2. Select COS_MAPPED_TO_MSB 3. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow: - Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = 0xFFFFF - (2^(non-eviction mask)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(non-eviction mask)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of ways)-1) b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000 This new eNEM flow can be used for ADL SoC. Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 5ae3ddf..1b089c0 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -85,6 +85,7 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_YMM 0xc85 #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9023b58..7af664d 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -66,6 +66,14 @@ This config supports INTEL_CAR_NEM_ENHANCED mode on TGL platform. +config USE_CAR_NEM_ENHANCED_V3 + bool + select USE_CAR_NEM_ENHANCED_V1 + select COS_MAPPED_TO_MSB + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + ADL platform. + config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 167342f..371ac73 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -413,7 +413,11 @@ set_eviction_mask: mov %ebx, %ecx /* back up the number of ways */ - mov %eax, %ebx /* back up the non-eviction mask*/ + mov %eax, %ebx /* back up the non-eviction mask */ +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + movd %ecx, %mm3 /* Store the number of ways in mm3 for later use */ + movd %ebx, %mm4 /* Store the non-eviction mask in mm4 for later use */ +#endif /* * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 * This MSR contain one bit per each way of LLC @@ -450,6 +454,37 @@ #endif xorl %edx, %edx wrmsr + +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + /* Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = 0xFFFFF - (2^(non-eviction mask) - 1) */ + movd %mm4, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + mov %eax, %ebx + mov $0xFFFFF, %eax + subl %ebx, %eax + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_1, %ecx + wrmsr + + /* Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(non-eviction mask) - 1) */ + movd %mm4, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_2, %ecx + wrmsr + + /* Set MSR 0xC85 L3_Protected_ways = (2^(no. of ways) - 1) */ + movd %mm3, %ecx + shl %cl, %eax + subl $0x01, %eax + xorl %edx, %edx + mov $IA32_YMM, %ecx + wrmsr +#endif /* * Set IA32_PQR_ASSOC * diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 191232a..568a502 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -96,6 +96,13 @@ rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + /* Set MSR 0xC85 L3_Protected_ways = 0x00000 */ + mov $IA32_YMM, %ecx + mov $0x00000, %eax + xorl %edx, %edx + wrmsr +#endif #endif /* Return to caller. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Gerrit-Change-Number: 48344 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: Refactor QSPI driver
by Rajesh Patil (Code Review) 16 Aug '21

16 Aug '21

Attention is currently required from: Shelley Chen, Ravi kumar, Sudheer Amrabadi, Julius Werner, mturney mturney. Rajesh Patil has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55322 ) Change subject: sc7280: Refactor QSPI driver ...................................................................... Patch Set 21: (1 comment) File src/soc/qualcomm/sc7280/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/55322/comment/681ff3ee_76ec9122 PS15, Line 18: #define QSPI_CS GPIO(15) : #define QSPI_DATA_0 GPIO(12) : #define QSPI_DATA_1 GPIO(13) : #define QSPI_CLK GPIO(14) : > Let's follow the tab convention that you've been using for the other #defines (above and below) here […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1dc3fe8bd71957ff8604ef4c9d97963100ccfb Gerrit-Change-Number: 55322 Gerrit-PatchSet: 21 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Mon, 16 Aug 2021 05:32:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Create eNEM Kconfig for Alder Lake
by Subrata Banik (Code Review) 16 Aug '21

16 Aug '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56090 ) Change subject: soc/intel/alderlake: Create eNEM Kconfig for Alder Lake ...................................................................... soc/intel/alderlake: Create eNEM Kconfig for Alder Lake Alder Lake SoC specific Kconfig that internally selects all eNEM related Kconfig. CONFIG_ALDERLAKE_CAR_ENHANCED_NEM will get autoselected if platform doesn't have INTEL_CAR_NEM Kconfig selected explicitly. BUG=b:168820083 TEST=Verified CONFIG_INTEL_CAR_NEM is still enable. Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56090 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f77b4c3..154f104 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -84,6 +84,14 @@ select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM +config ALDERLAKE_CAR_ENHANCED_NEM + bool + default y if !INTEL_CAR_NEM + select INTEL_CAR_NEM_ENHANCED + select CAR_HAS_SF_MASKS + select COS_MAPPED_TO_MSB + select CAR_HAS_L3_PROTECTED_WAYS + config MAX_CPUS int default 24 -- To view, visit https://review.coreboot.org/c/coreboot/+/56090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881 Gerrit-Change-Number: 56090 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 ...
by Karthik Ramasubramanian (Code Review) 16 Aug '21

16 Aug '21

Attention is currently required from: Henry Sun, Chen Wisley, Wisley Chen. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56909 ) Change subject: mb/google/dedede/variant/lantis: Include SPD for MT53E512M32D1NP-046 WT:B ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22c50a55dd3b8bbda64ba1b607c8b22cc6592f98 Gerrit-Change-Number: 56909 Gerrit-PatchSet: 3 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 16 Aug 2021 03:43:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/sasukette:Add fw_config probe for codec ALC5682I...
by Karthik Ramasubramanian (Code Review) 16 Aug '21

16 Aug '21

Attention is currently required from: Zhi7 Li. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56930 ) Change subject: mb/google/dedede/var/sasukette:Add fw_config probe for codec ALC5682I-VD & VS compatibility ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/dedede/variants/sasukette/ramstage.c: https://review.coreboot.org/c/coreboot/+/56930/comment/083c7a32_7f0e3161 PS7, Line 14: const struct device_path codec_path[] = { : { .type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_I2C4 }, : { .type = DEVICE_PATH_I2C, .i2c.device = 0x1a } : }; : const struct device *codec = find_dev_nested_path(pci_root_bus(), : codec_path, ARRAY_SIZE(codec_path)); : struct drivers_i2c_generic_config *config; : : if (!codec || (codec->chip_ops != &drivers_i2c_generic_ops) || !codec->chip_info) : return; : : config = codec->chip_info; : if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682))) : config->hid = "10EC5682"; : else if (fw_config_probe(FW_CONFIG(AUDIO_CODEC_SOURCE, AUDIO_CODEC_ALC5682I_VS))) : config->hid = "RTL5682"; W.r.t CB:56804, move this to a separate function - eg. void audio_codec_update(void), so that the ext_vr can be added as another function. -- To view, visit https://review.coreboot.org/c/coreboot/+/56930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8840454e4934162ea59c742634a56f70b153238 Gerrit-Change-Number: 56930 Gerrit-PatchSet: 8 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 16 Aug 2021 03:27:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/sasukette:Add fw_config probe for codec ALC5682I...
by build bot (Jenkins) (Code Review) 16 Aug '21

16 Aug '21

Attention is currently required from: Zhi7 Li. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56930 ) Change subject: mb/google/dedede/var/sasukette:Add fw_config probe for codec ALC5682I-VD & VS compatibility ...................................................................... Patch Set 8: (1 comment) File src/mainboard/google/dedede/variants/sasukette/ramstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-126234): https://review.coreboot.org/c/coreboot/+/56930/comment/2483546f_a64868e9 PS8, Line 16: {.type = DEVICE_PATH_I2C, .i2c.device = 0x1a}}; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/56930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8840454e4934162ea59c742634a56f70b153238 Gerrit-Change-Number: 56930 Gerrit-PatchSet: 8 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 16 Aug 2021 03:27:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/sasukette:Add fw_config probe for codec ALC5682I...
by Zhi7 Li (Code Review) 16 Aug '21

16 Aug '21

Attention is currently required from: Zhi7 Li. Hello build bot (Jenkins), Tim Wawrzynczak, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56930 to look at the new patch set (#8). Change subject: mb/google/dedede/var/sasukette:Add fw_config probe for codec ALC5682I-VD & VS compatibility ...................................................................... mb/google/dedede/var/sasukette:Add fw_config probe for codec ALC5682I-VD & VS compatibility Change the `_HID` value depending on the the fw_config values BUG=b:193623380 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7(a)huaqin.corp-partner.google.com> Change-Id: Ic8840454e4934162ea59c742634a56f70b153238 --- M src/mainboard/google/dedede/variants/sasukette/Makefile.inc M src/mainboard/google/dedede/variants/sasukette/overridetree.cb A src/mainboard/google/dedede/variants/sasukette/ramstage.c 3 files changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/56930/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/56930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8840454e4934162ea59c742634a56f70b153238 Gerrit-Change-Number: 56930 Gerrit-PatchSet: 8 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Codec ALC5682I-VD & VS compatibility
by Karthik Ramasubramanian (Code Review) 16 Aug '21

16 Aug '21

Attention is currently required from: Zhi7 Li. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56930 ) Change subject: mb/google/dedede/var/sasukette: Codec ALC5682I-VD & VS compatibility ...................................................................... Patch Set 7: (3 comments) File src/mainboard/google/dedede/variants/sasukette/overridetree.cb: https://review.coreboot.org/c/coreboot/+/56930/comment/dde5edf3_301ae84f PS7, Line 2: field AUDIO_CODEC_SOURCE 41 43 Can you please confirm that there are no conflicts with the second source of other components in Sasukette? Please check EC as well. https://review.coreboot.org/c/coreboot/+/56930/comment/6af8d154_af4856d2 PS7, Line 4: 3 Why is it 3 instead of 2 - i.e. why is there a gap? File src/mainboard/google/dedede/variants/sasukette/ramstage.c: https://review.coreboot.org/c/coreboot/+/56930/comment/8fb366e7_7fcd9e71 PS7, Line 29: config->hid = "RTL5682"; Nit: Seems there are 2 spaces between = and "RTL5682" -- To view, visit https://review.coreboot.org/c/coreboot/+/56930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8840454e4934162ea59c742634a56f70b153238 Gerrit-Change-Number: 56930 Gerrit-PatchSet: 7 Gerrit-Owner: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 16 Aug 2021 03:21:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cappy2: Fix the DUT with cirrus codec PLT fail
by Karthik Ramasubramanian (Code Review) 16 Aug '21

16 Aug '21

Attention is currently required from: Sunwei Li, Henry Sun, Paul Menzel, Weimin Wu, Zhi7 Li. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56973 ) Change subject: mb/google/dedede/var/cappy2: Fix the DUT with cirrus codec PLT fail ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65bca519f75af84848284f039b6ad67cb1887823 Gerrit-Change-Number: 56973 Gerrit-PatchSet: 3 Gerrit-Owner: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-CC: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Attention: Sunwei Li <lisunwei(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 16 Aug 2021 03:01:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/octopus/var/phaser: Change IRQ trigger method to level
by Joey Peng (Code Review) 16 Aug '21

16 Aug '21

Attention is currently required from: Paul Menzel, Marco Chen. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56380 ) Change subject: mb/google/octopus/var/phaser: Change IRQ trigger method to level ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56380/comment/005842df_00c22521 PS4, Line 14: > This is the information (that is was copied and never used) I’d like to have in the commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44ee779242779c78ceafdddd34dca2571e714dd3 Gerrit-Change-Number: 56380 Gerrit-PatchSet: 6 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marco Chen <marcochen(a)google.com> Gerrit-Attention: Marco Chen <marcochen(a)chromium.org> Gerrit-Comment-Date: Mon, 16 Aug 2021 02:47:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Marco Chen <marcochen(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit August 2021