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Hello build bot (Jenkins), Henry Sun, Marco Chen, Marco Chen,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56380
to look at the new patch set (#6).
Change subject: mb/google/octopus/var/phaser: Change IRQ trigger method to level
......................................................................
mb/google/octopus/var/phaser: Change IRQ trigger method to level
The change from Synaptics S7817 to Elan 3915N and pin distribution
of touch IC is the same.
The original Elan section was copied from reference design and
was never used before.
According to vendor spec definition IRQ trigger method needs to
change to level.
BUG=b:190574692
TEST=Build coreboot and check that device works
Change-Id: I44ee779242779c78ceafdddd34dca2571e714dd3
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/octopus/variants/phaser/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/56380/6
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56568 )
Change subject: soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enable
......................................................................
soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enable
As per TGL EDS doc:575681, two ways will be controlled with one bit
of SF QoS register(SF Mask#1/#2) hence, selects SF_MASK_2WAYS_PER_BIT
for TGL SoC.
Change-Id: Ibeef653e0c510b62880b10b3f9767664d89c9623
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56568
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 9015703..e337e34 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -28,6 +28,7 @@
select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM
select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED
select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
+ select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56915 )
Change subject: mb/google/brya: set PL4 value dynamically for thermal
......................................................................
Patch Set 4: Code-Review+2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56930 )
Change subject: mb/google/dedede/var/sasukette: Codec ALC5682I-VD & VS compatibility
......................................................................
Patch Set 7:
(2 comments)
Patchset:
PS1:
> Thanks a lot for your advise, I have verified that ALC5682I-VD or VS audio codec can both work norma […]
👍 great!
File src/mainboard/google/dedede/variants/sasukette/ramstage.c:
https://review.coreboot.org/c/coreboot/+/56930/comment/4ca2fd6a_218ff5bb
PS6, Line 19: codec_path, ARRAY_SIZE(codec_path));
> Thanks very much for your detail reminding and comment which have really teach me a lot of how to ap […]
Line lengths in coreboot are 96 wide, so feel free to use the whole width, or break it up into multiple lines if required.
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