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Change subject: mb/google/dedede/var/sasukette: Add fw_config probe for ALC5682I-VD & VS
......................................................................
Patch Set 14: Code-Review+2
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Change subject: mb/google/brya/variants/primus: Fix GL9755S SD card reader power sequence
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56981/comment/72646270_f99b02ee
PS1, Line 7: mb/google/brya/variants/primus: Fix GL9755S SD card reader power
: sequence
comment header must be 72 chars wide maximum, suggestion:
```
mb/google/brya/primus: Fix GL9755S power sequence"
```
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Change subject: acpigen: Add ability to auto-generate _DSM Function 0
......................................................................
Patch Set 5:
(1 comment)
File src/acpi/acpigen.c:
https://review.coreboot.org/c/coreboot/+/56459/comment/6b9f6da1_faf31f00
PS5, Line 1657:
: for (size_t i = 1; i < id->count; i++) {
: if (id->callbacks[i]) {
: const size_t buffer_idx = i / (sizeof(uint8_t) * BITS_PER_BYTE);
: const size_t bit_idx = i % (sizeof(uint8_t) * BITS_PER_BYTE);
:
: set = true;
: buffer[buffer_idx] |= BIT(bit_idx);
: }
: }
Hi Tim,
I tested this patch and found two problems with the current.
1. Following is the output generated with the current implementation and Return is getting called unconditionally without checking for function index to be 0.
If ((Local0 == ToUUID ("f21202bf-8f78-4dc6-a5b3-1f738e285ade")))
{
ToInteger (Arg2, Local1)
Return (Buffer (0x08)
{
0xFF, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00 // ........
})
If ((Local1 == One))
{
...
}
Following is expected
If ((Local1 == Zero))
{
Return (Buffer (0x08)
{
0xFF, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00 // ........
})
}
2. As per the ACPI spec, each bit in the 32bit(4bytes) buffer signifies the support for the function.
For example if we have define 9 callbacks with the 0th set to NULL, following is the expected output
If ((Local1 == Zero))
{
Return (Buffer (0x02)
{
0xFF, 0x01
})
}
I update the logic to the following and it is working as expected. Please let me know your thoughts.
static void acpigen_dsm_uuid_enum_functions(const struct dsm_uuid *id)
{
const size_t bytes = (id->count / BITS_PER_BYTE) + ((id->count % BITS_PER_BYTE) > 0);
uint8_t *buffer = alloca(bytes);
bool set = false;
int cb_index = 0;
for (size_t i = 0; i < bytes; i++) {
for (size_t j = 0; j < BITS_PER_BYTE; j++) {
if (cb_index >= id->count)
break;
if (id->callbacks[cb_index++]) {
set = true;
buffer[i] |= BIT(j);
}
}
}
if (set)
buffer[0] |= BIT(0);
acpigen_write_if_lequal_op_int(LOCAL1_OP, 0);
acpigen_write_return_byte_buffer(buffer, bytes);
acpigen_pop_len(); /* If */
}
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Change subject: mb/google/dedede/var/sasukette: Add fw_config probe for non-ext VR
......................................................................
Patch Set 10:
(2 comments)
Patchset:
PS10:
Please rebase this change on top of CB:56930
File src/mainboard/google/dedede/variants/sasukette/ramstage.c:
https://review.coreboot.org/c/coreboot/+/56804/comment/e0a98dee_19a3388a
PS10, Line 7: EXT_VR
dont capitalize in between. Keep them all small letters.
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Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56967 )
Change subject: soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
......................................................................
Patch Set 5: Code-Review+1
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Hello build bot (Jenkins), Frans Hendriks, Patrick Rudolph, Jonathan Zhang, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph, Piotr Król, Tim Crawford, Nico Huber, Anjaneya "Reddy" Chagam, Michał Żygowski, Johnny Lin, Tim Wawrzynczak, Christian Walter, Morgan Jang, Wim Vervoorn,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56967
to look at the new patch set (#5).
Change subject: soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
......................................................................
soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/asrock/h110m/devicetree.cb
M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
M src/mainboard/facebook/monolith/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/hp/280_g2/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/cedarisland_crb/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/kontron/bsl6/devicetree.cb
M src/mainboard/libretrend/lt1000/devicetree.cb
M src/mainboard/ocp/deltalake/devicetree.cb
M src/mainboard/ocp/tiogapass/devicetree.cb
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb
M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
M src/mainboard/purism/librem_skl/devicetree.cb
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
M src/mainboard/siemens/chili/variants/base/devicetree.cb
M src/mainboard/siemens/chili/variants/chili/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
M src/mainboard/system76/gaze15/devicetree.cb
M src/mainboard/system76/lemp9/devicetree.cb
M src/mainboard/system76/oryp5/devicetree.cb
M src/mainboard/system76/oryp6/devicetree.cb
M src/mainboard/system76/whl-u/devicetree.cb
M src/soc/intel/common/block/include/intelblocks/cfg.h
59 files changed, 2 insertions(+), 160 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/56967/5
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Change subject: mb/google/dedede/var/sasukette: Add fw_config probe for ALC5682I-VD & VS
......................................................................
Patch Set 14: Code-Review+2
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Hello build bot (Jenkins), Frans Hendriks, Patrick Rudolph, Jonathan Zhang, Jeremy Soller, Angel Pons, Michael Niewöhner, Patrick Rudolph, Piotr Król, Tim Crawford, Nico Huber, Anjaneya "Reddy" Chagam, Michał Żygowski, Johnny Lin, Tim Wawrzynczak, Christian Walter, Morgan Jang, Wim Vervoorn,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56967
to look at the new patch set (#4).
Change subject: soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
......................................................................
soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured in the
devicetree with something else, `CHIPSET_LOCKDOWN_COREBOOT` is used.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/asrock/h110m/devicetree.cb
M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
M src/mainboard/facebook/monolith/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
M src/mainboard/hp/280_g2/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree.cb
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/cedarisland_crb/devicetree.cb
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb
M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/mainboard/kontron/bsl6/devicetree.cb
M src/mainboard/libretrend/lt1000/devicetree.cb
M src/mainboard/ocp/deltalake/devicetree.cb
M src/mainboard/ocp/tiogapass/devicetree.cb
M src/mainboard/prodrive/hermes/devicetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb
M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
M src/mainboard/purism/librem_skl/devicetree.cb
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
M src/mainboard/siemens/chili/variants/base/devicetree.cb
M src/mainboard/siemens/chili/variants/chili/devicetree.cb
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
M src/mainboard/system76/gaze15/devicetree.cb
M src/mainboard/system76/lemp9/devicetree.cb
M src/mainboard/system76/oryp5/devicetree.cb
M src/mainboard/system76/oryp6/devicetree.cb
M src/mainboard/system76/whl-u/devicetree.cb
M src/soc/intel/common/block/include/intelblocks/cfg.h
59 files changed, 2 insertions(+), 160 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/56967/4
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56982 )
Change subject: mb/google/octopus: add CBI SKU RAM ID 5
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/octopus/variants/baseboard/memory.c:
https://review.coreboot.org/c/coreboot/+/56982/comment/cf3947f3_0b7c2378
PS2, Line 169: [5]
I believe index 5 was not assigned in the past to any memory configuration. Can you please confirm?
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