coreboot-gerrit August 2021

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Change in coreboot[master]: util/crossgcc: Update to expat 2.4.1
by Lance Zhao (Code Review) 17 Aug '21

17 Aug '21

Lance Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56979 ) Change subject: util/crossgcc: Update to expat 2.4.1 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Duplicate of CB:56868 Thanks. However have you seen extra change I have made EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/files/${EXPAT_VERSION}/…", will sync and build to confirm that. -- To view, visit https://review.coreboot.org/c/coreboot/+/56979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba50f645321ced85dd2423585bd19446b484866d Gerrit-Change-Number: 56979 Gerrit-PatchSet: 1 Gerrit-Owner: Lance Zhao Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 16 Aug 2021 15:08:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: MAINTAINERS: add AMD Stoneyridge SoC
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56855 to look at the new patch set (#2). Change subject: MAINTAINERS: add AMD Stoneyridge SoC ...................................................................... MAINTAINERS: add AMD Stoneyridge SoC Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Idc4d98fd35d1b2f2d8165909c0fce141c6ca100d --- M MAINTAINERS 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/56855/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc4d98fd35d1b2f2d8165909c0fce141c6ca100d Gerrit-Change-Number: 56855 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/crossgcc: Update to expat 2.4.1
by Lance Zhao (Code Review) 17 Aug '21

17 Aug '21

Lance Zhao has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/56979 ) Change subject: util/crossgcc: Update to expat 2.4.1 ...................................................................... Abandoned Duplicate of CB:56868 -- To view, visit https://review.coreboot.org/c/coreboot/+/56979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba50f645321ced85dd2423585bd19446b484866d Gerrit-Change-Number: 56979 Gerrit-PatchSet: 1 Gerrit-Owner: Lance Zhao Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chip...
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56955 ) Change subject: mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cb ...................................................................... mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cb For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/soc/intel/tigerlake/chipset.cb 5 files changed, 2 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 27f3211..2445987 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index abb8bdc..ae81518 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -79,8 +79,6 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 66eb027..2b159d5 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c4bbdda..e55a73c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/soc/intel/tigerlake/chipset.cb b/src/soc/intel/tigerlake/chipset.cb index e81f0524..4ebfcfd 100644 --- a/src/soc/intel/tigerlake/chipset.cb +++ b/src/soc/intel/tigerlake/chipset.cb @@ -1,4 +1,6 @@ chip soc/intel/tigerlake + + device cpu_cluster 0 on end device domain 0 on device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end -- To view, visit https://review.coreboot.org/c/coreboot/+/56955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d Gerrit-Change-Number: 56955 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC ID
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56954 ) Change subject: mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC ID ...................................................................... mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC ID coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 4 files changed, 4 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 4a0c49f..27f3211 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index e2a84f8..abb8bdc 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -79,9 +79,7 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4e3d2e79..66eb027 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7f7e16b..c4bbdda 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this -- To view, visit https://review.coreboot.org/c/coreboot/+/56954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360 Gerrit-Change-Number: 56954 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp_m: Enable CR50 TPM support over SPI
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54023 ) Change subject: mb/intel/adlrvp_m: Enable CR50 TPM support over SPI ...................................................................... mb/intel/adlrvp_m: Enable CR50 TPM support over SPI Add Kconfig options and enable TPM device in devicetree BUG=None TEST=Booted the image and checked the successful TPM communication in verstage,romstage & ramstage from coreboot logs. Signed-off-by: Thejaswani Puta thejaswani.putta(a)intel.com <thejaswani.putta(a)intel.com> Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54023 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/early_gpio_m.c M src/mainboard/intel/adlrvp/gpio_m.c 4 files changed, 51 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Thejaswani Putta: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index f622921..eed3b30 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -22,6 +22,9 @@ select DRIVERS_I2C_MAX98373 select FW_CONFIG if BOARD_INTEL_ADLRVP_M_EXT_EC select FW_CONFIG_SOURCE_CHROMEEC_CBI if BOARD_INTEL_ADLRVP_M_EXT_EC + select MAINBOARD_HAS_TPM2 if BOARD_INTEL_ADLRVP_M_EXT_EC + select MAINBOARD_HAS_SPI_TPM_CR50 if BOARD_INTEL_ADLRVP_M_EXT_EC + select SPI_TPM if BOARD_INTEL_ADLRVP_M_EXT_EC config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON @@ -91,11 +94,18 @@ config VBOOT select VBOOT_LID_SWITCH - select VBOOT_MOCK_SECDATA + select VBOOT_MOCK_SECDATA if BOARD_INTEL_ADLRVP_P_EXT_EC select EC_GOOGLE_CHROMEEC_SWITCHES if ADL_CHROME_EC select VBOOT_EARLY_EC_SYNC if BOARD_INTEL_ADLRVP_M_EXT_EC config UART_FOR_CONSOLE int default 0 + +config DRIVER_TPM_SPI_BUS + default 0x2 if BOARD_INTEL_ADLRVP_M_EXT_EC + +config TPM_TIS_ACPI_INTERRUPT + int + default 67 if BOARD_INTEL_ADLRVP_M_EXT_EC # GPE0_DW2_3 (GPP_E3) endif diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index b28f387..65a6cac 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -6,6 +6,19 @@ end chip soc/intel/alderlake + device cpu_cluster 0 on + device lapic 0 on end + end + + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses. + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE @@ -107,14 +120,14 @@ register "SerialIoGSpiMode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, - [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, }" register "SerialIoGSpiCsMode" = "{ [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI1] = 1, [PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI3] = 0, }" @@ -141,6 +154,10 @@ # Intel Common SoC Config register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[1] = { + .speed_mhz = 1, + .early_init = 1, + }, .i2c[0] = { .speed = I2C_SPEED_FAST, }, @@ -353,6 +370,14 @@ device ref uart0 on end device ref gspi0 on end device ref p2sb on end + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)" + device spi 0 on end + end + end # GSPI1 device ref hda on chip drivers/intel/soundwire device generic 0 on diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c index 3b60e24..79349b1 100644 --- a/src/mainboard/intel/adlrvp/early_gpio_m.c +++ b/src/mainboard/intel/adlrvp/early_gpio_m.c @@ -99,6 +99,18 @@ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1), PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1), PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1), + + /* H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + /* TPM */ + /* F16 : GSPI1_CS0N */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + /* F11 : GSPI1_CLK */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F13 : GSPI1_MISO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F12 : GSPI1_MOSI */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), }; static const struct pad_config early_uart_gpio_table[] = { diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c index d5eeffa..11686be 100644 --- a/src/mainboard/intel/adlrvp/gpio_m.c +++ b/src/mainboard/intel/adlrvp/gpio_m.c @@ -159,7 +159,7 @@ PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* S7 : SNDW4_DATA */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2) + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), }; void variant_configure_gpio_pads(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/54023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8 Gerrit-Change-Number: 54023 Gerrit-PatchSet: 13 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Create driblee variant
by Karthik Ramasubramanian (Code Review) 17 Aug '21

17 Aug '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56798 ) Change subject: mb/google/dedede: Create driblee variant ...................................................................... mb/google/dedede: Create driblee variant Create the driblee variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:191732473 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DRIBLEE Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56798 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/driblee/include/variant/ec.h A src/mainboard/google/dedede/variants/driblee/include/variant/gpio.h A src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc A src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/driblee/overridetree.cb 8 files changed, 83 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index c2c0f5c..5c0b0df 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -114,6 +114,7 @@ default "Cappy2" if BOARD_GOOGLE_CAPPY2 default "Bugzzy" if BOARD_GOOGLE_BUGZZY default "Corori" if BOARD_GOOGLE_CORORI + default "Driblee" if BOARD_GOOGLE_DRIBLEE config MAX_CPUS int @@ -153,6 +154,7 @@ default "cappy2" if BOARD_GOOGLE_CAPPY2 default "bugzzy" if BOARD_GOOGLE_BUGZZY default "corori" if BOARD_GOOGLE_CORORI + default "driblee" if BOARD_GOOGLE_DRIBLEE endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 98a656b..4dc0d0d 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -171,3 +171,8 @@ bool "-> Corori" select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_DRIBLEE + bool "-> Driblee" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/driblee/include/variant/ec.h b/src/mainboard/google/dedede/variants/driblee/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/driblee/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/driblee/include/variant/gpio.h b/src/mainboard/google/dedede/variants/driblee/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/driblee/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc b/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/dedede/variants/driblee/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/driblee/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt new file mode 100644 index 0000000..e4258b5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/driblee/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/driblee/overridetree.cb b/src/mainboard/google/dedede/variants/driblee/overridetree.cb new file mode 100644 index 0000000..cbad0d2 --- /dev/null +++ b/src/mainboard/google/dedede/variants/driblee/overridetree.cb @@ -0,0 +1,43 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0 + register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0" + + device domain 0 on + device pci 15.0 on end + device pci 1e.2 off end # GSPI 0 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end # Discrete TPM + end # chip drivers/pc80/tpm + end # PCH eSPI + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/56798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ad9a4e0cf7999337b55d62d5cc94e4f6c2e98f3 Gerrit-Change-Number: 56798 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Create corori variant
by Karthik Ramasubramanian (Code Review) 17 Aug '21

17 Aug '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56796 ) Change subject: mb/google/dedede: Create corori variant ...................................................................... mb/google/dedede: Create corori variant Create the corori variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:194356176 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_CORORI Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56796 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/Kconfig.name A src/mainboard/google/dedede/variants/corori/include/variant/ec.h A src/mainboard/google/dedede/variants/corori/include/variant/gpio.h A src/mainboard/google/dedede/variants/corori/memory/Makefile.inc A src/mainboard/google/dedede/variants/corori/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/corori/memory/mem_parts_used.txt A src/mainboard/google/dedede/variants/corori/overridetree.cb 8 files changed, 83 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index aa72c32..c2c0f5c 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -113,6 +113,7 @@ default "Cappy" if BOARD_GOOGLE_CAPPY default "Cappy2" if BOARD_GOOGLE_CAPPY2 default "Bugzzy" if BOARD_GOOGLE_BUGZZY + default "Corori" if BOARD_GOOGLE_CORORI config MAX_CPUS int @@ -151,6 +152,7 @@ default "cappy" if BOARD_GOOGLE_CAPPY default "cappy2" if BOARD_GOOGLE_CAPPY2 default "bugzzy" if BOARD_GOOGLE_BUGZZY + default "corori" if BOARD_GOOGLE_CORORI endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 98a2298..98a656b 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -166,3 +166,8 @@ select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_DA7219 + +config BOARD_GOOGLE_CORORI + bool "-> Corori" + select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/corori/include/variant/ec.h b/src/mainboard/google/dedede/variants/corori/include/variant/ec.h new file mode 100644 index 0000000..08870e0 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/dedede/variants/corori/include/variant/gpio.h b/src/mainboard/google/dedede/variants/corori/include/variant/gpio.h new file mode 100644 index 0000000..9078664 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/corori/memory/Makefile.inc b/src/mainboard/google/dedede/variants/corori/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/corori/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/corori/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/corori/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/corori/memory/mem_parts_used.txt new file mode 100644 index 0000000..e4258b5 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. +# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/corori/overridetree.cb b/src/mainboard/google/dedede/variants/corori/overridetree.cb new file mode 100644 index 0000000..cbad0d2 --- /dev/null +++ b/src/mainboard/google/dedede/variants/corori/overridetree.cb @@ -0,0 +1,43 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "SerialIoGSpiMode[PchSerialIoIndexGSPI0]" = "PchSerialIoDisabled" # Disable GSPI0 + register "SerialIoGSpiCsMode[PchSerialIoIndexGSPI0]" = "0" + + device domain 0 on + device pci 15.0 on end + device pci 1e.2 off end # GSPI 0 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end # Discrete TPM + end # chip drivers/pc80/tpm + end # PCH eSPI + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/56796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8380d5aab61c99d545625789ff1251ec1caa84a2 Gerrit-Change-Number: 56796 Gerrit-PatchSet: 8 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/poppy/variants/atlas: stop setting touchscreen probed=1
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56928 ) Change subject: mb/google/poppy/variants/atlas: stop setting touchscreen probed=1 ...................................................................... mb/google/poppy/variants/atlas: stop setting touchscreen probed=1 All Atlas devices have the touchscreen controller, so probing for its presence is unnecessary. Removing the probe requirement allows the touchscreen ACPI device in Linux to re-enumerate when rebinding its I2C adapter device. Without this change, after rebinding the touchscreen's I2C adapter device using sysfs the touchscreen ACPI and HID devices are absent, and the touchscreen is unresponsive. With this change, the touchscreen ACPI and HID devices are re-created after rebinding its I2C adapter device, and the touchscreen becomes responsive again. BUG=b:177350937 TEST=Tested on 2 Atlas DUTs running Chrome OS R94 top-of-tree builds with Linux 4.4 and 5.4. Built new AP FW from Atlas Chrome OS firmware branch with this change applied. Tested shipping RO + new RW, and new RO + new RW. Test sequence: 1) Boot DUT, verify basic touchscreen functionality. 2) $ cd /sys/bus/platform/drivers/i2c_designware 3) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:07 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002 drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:07 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0002/hidraw/hidraw1 4) $ echo i2c_designware.0 > unbind 5) Verify touchscreen is unresponsive (as expected after unbind). 6) $ ls -ld i2c_designware.0 ls: cannot access 'i2c_designware.0': No such file or directory 7) $ echo i2c_designware.0 > bind *** Without this change: *** 8) Touchscreen remains unresponsive. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00}} ls: cannot access 'i2c_designware.0/i2c-6/i2c-ACPI0C50:00': No such file or directory lrwxrwxrwx. 1 root root 0 Aug 12 01:18 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 4 root root 0 Aug 12 01:18 i2c_designware.0/i2c-6 *** With this change: *** 8) Touchscreen is functional again. 9) $ ls -ld i2c_designware.0{,/i2c-6{,/i2c-ACPI0C50:00{,/0018:0483:1058.*{,/hidraw{,/hidraw*}}}}} lrwxrwxrwx. 1 root root 0 Aug 12 01:09 i2c_designware.0 -> ../../../../devices/pci0000:00/0000:00:15.0/i2c_designware.0 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6 drwxr-xr-x. 4 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00 drwxr-xr-x. 5 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003 drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw drwxr-xr-x. 3 root root 0 Aug 12 01:09 i2c_designware.0/i2c-6/i2c-ACPI0C50:00/0018:0483:1058.0003/hidraw/hidraw1 Signed-off-by: Matthew Blecker <matthewb(a)chromium.org> Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db Reviewed-on: https://review.coreboot.org/c/coreboot/+/56928 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/atlas/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index e779ae4..4319948 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -273,7 +273,6 @@ register "generic.desc" = ""STM Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.speed" = "I2C_SPEED_FAST" - register "generic.probed" = "1" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" -- To view, visit https://review.coreboot.org/c/coreboot/+/56928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b90690b0591e8748d7a007f8cc9688d393e59db Gerrit-Change-Number: 56928 Gerrit-PatchSet: 8 Gerrit-Owner: Matthew Blecker <matthewb(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/redrix: Generate SPD ID for supported parts
by Felix Held (Code Review) 17 Aug '21

17 Aug '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56969 ) Change subject: mb/google/brya/var/redrix: Generate SPD ID for supported parts ...................................................................... mb/google/brya/var/redrix: Generate SPD ID for supported parts Add supported memory parts in mem_parts_used.txt, and generate SPD id for these parts. MT53E512M32D1NP-046 WT:B MT53E1G32D2NP-046 WT:B BUG=b:192052098 TEST=FW_NAME=redrix emerge-brya coreboot Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: I61377e6cdd3af9d6d80b9e1e68191b39f43358ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/56969 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/redrix/memory/Makefile.inc M src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc index 8fb0ea1..410ef10 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/redrix/memory/Makefile.inc @@ -3,7 +3,7 @@ SPD_SOURCES = SPD_SOURCES += lp4x-spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += lp4x-spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E -SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR +SPD_SOURCES += lp4x-spd-1.hex # ID = 1(0b0001) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, MT53E512M32D2NP-046 WT:E, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, MT53E1G32D2NP-046 WT:B SPD_SOURCES += lp4x-spd-2.hex # ID = 3(0b0011) Parts = H9HCNNNFAMMLXR-NEE SPD_SOURCES += lp4x-spd-7.hex # ID = 4(0b0100) Parts = MT53E2G32D4NQ-046 WT:A diff --git a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt index 50b2c2a..89da08a 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/dram_id.generated.txt @@ -7,3 +7,5 @@ K4UBE3D4AA-MGCR 2 (0010) H9HCNNNFAMMLXR-NEE 3 (0011) MT53E2G32D4NQ-046 WT:A 4 (0100) +MT53E512M32D1NP-046 WT:B 1 (0001) +MT53E1G32D2NP-046 WT:B 2 (0010) diff --git a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt index eb1c176..71bd5fd 100644 --- a/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/redrix/memory/mem_parts_used.txt @@ -6,3 +6,5 @@ K4UBE3D4AA-MGCR H9HCNNNFAMMLXR-NEE MT53E2G32D4NQ-046 WT:A +MT53E512M32D1NP-046 WT:B +MT53E1G32D2NP-046 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/56969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61377e6cdd3af9d6d80b9e1e68191b39f43358ab Gerrit-Change-Number: 56969 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit August 2021