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Change subject: mb/google/dedede/var/driblee: Generate RAM ID and SPD file
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/zork: only enable RTD2141 when present
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56990/comment/7254a560_24e6344c
PS2, Line 10: fw_config
: probe
> I'm not clear on what you're asking here. […]
Yes, the second one. Just reading the commit message, it’s not clear, how the fw-probe is structured(?).
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Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56662/comment/d31f4f60_5dc86582
PS1, Line 14:
> Angel, yes, but only when setting some magic undocumented register. Intel claims it has *nothing* to do with C10/S0ix but it *must*. Setting PWRM_CIR30C=0x00 instantly breaks anything deeper PC3 (which is the default), setting it to 0x44 makes it work again.
>
> I could also verify this on X11SSM-F (SKL/KBL), where vendor fw sets PWRM_CIR30C=0x44. I can break C10/S0ix by setting PWRM_CIR30C=0x00.
Alright, thanks for the info. I guess we can mark this as resolved?
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Change subject: mb/google/dedede/var/driblee: Generate RAM ID and SPD file
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Hi Google,
Would you help to review the CLs in the relation chain about updating driblee firmware settings?
Thank you very much.
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Change subject: util/liveiso: Add NixOS configs for bootable live systems
......................................................................
Patch Set 31:
(1 comment)
File util/liveiso/build-graphical.sh:
https://review.coreboot.org/c/coreboot/+/50194/comment/158badc1_630003ca
PS30, Line 3: config.system.build.isoImage
> nix-build just executes Nix expressions. […]
https://github.com/NixOS/nixpkgs/tree/master/nixos/lib
seems to be possible with `make-disk-image.nix` or `squashfs.nix`
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Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56662/comment/f041cb13_409bd894
PS1, Line 14:
> Thanks for testing!
Angel, yes, but only when setting some magic undocumented register. Intel claims it has *nothing* to do with C10/S0ix but it *must*. Setting PWRM_CIR30C=0x00 instantly breaks anything deeper PC3 (which is the default), setting it to 0x44 makes it work again.
I could also verify this on X11SSM-F (SKL/KBL), where vendor fw sets PWRM_CIR30C=0x44. I can break C10/S0ix by setting PWRM_CIR30C=0x00.
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Change subject: util/liveiso: Add NixOS configs for bootable live systems
......................................................................
Patch Set 31:
(1 comment)
File util/liveiso/build-graphical.sh:
https://review.coreboot.org/c/coreboot/+/50194/comment/248e31b2_2ff8492e
PS30, Line 3: config.system.build.isoImage
> Disclaimer: I have no idea about nix-build. ;) […]
nix-build just executes Nix expressions.
Yes, this creates an ISO image. AFAIK there is no module for building a disk image.
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