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Change subject: soc/intel/denverton_ns: Fix MRC cache write
......................................................................
soc/intel/denverton_ns: Fix MRC cache write
Fast SPI initialization is required for MRC cache write. Due to the
missing initialization, the SPI transaction causes the assertion of the
FCERR error bit (BIOS_HSFSTS_CTL register), so the Flash writes are
failing.
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/W2E7…
Signed-off-by: King Sumo <kingsumos(a)gmail.com>
Change-Id: I50cc4f8ced0b0524b39eece5a2bb4f0d99fb4eff
---
M src/soc/intel/denverton_ns/bootblock/bootblock.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57033/2
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Change subject: include/bcd: move bcd code to commonlib/bsd/include
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56904/comment/4fcf10de_3b78e630
PS3, Line 14: For reference bin2bcd() &
> Nit: Why wrap the line here?
fixed. thanks.
Patchset:
PS4:
fixed. thanks.
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I'd like you to reexamine a change. Please visit
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Change subject: include/bcd: move bcd code to commonlib/bsd/include
......................................................................
include/bcd: move bcd code to commonlib/bsd/include
Move bcd2bin() / bin2bcd() functions to commonlib/bsd/include/
Also, the license is changed from GPL to BSD.
This is because it is needed from "utils" (see CL in the chain).
For reference bin2bcd() & bcd2bin() are very simple functions.
There are already BSD implementations, like these ones (just to
name a few):
https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/ma…http://web.mit.edu/freebsd/head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c
BUG=b:172210863
TEST=make (everything compiled Ok).
Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72
Signed-off-by: Ricardo Quesada <ricardoq(a)google.com>
---
R src/commonlib/bsd/include/commonlib/bsd/bcd.h
M src/drivers/ams/as3722rtc.c
M src/drivers/elog/elog.c
M src/drivers/i2c/pcf8523/pcf8523.c
M src/drivers/i2c/rx6110sa/rx6110sa.c
M src/drivers/pc80/rtc/mc146818rtc.c
M src/drivers/ti/tps65913/tps65913rtc.c
M src/include/cper.h
M src/soc/mediatek/common/include/soc/rtc_common.h
M src/soc/rockchip/common/rk808.c
10 files changed, 16 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/56904/4
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
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Change subject: vc/google/chromeos: Add support for new SAR tables revisions
......................................................................
vc/google/chromeos: Add support for new SAR tables revisions
Existing SAR infrastructure supports only revision 0 of the SAR tables.
This patch modifies it to extend support intel wifi 6 and wifi 6e
configs as per the connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
The SAR table and WGDS configuration blocks size with in the earlier
SAR binary was static with option to enable WGDS block dynamically
using a coreboot config. The new binary format can support to have any
block as dynamic and the size of the configuration block depends on the
revision of the entry. This patch also adds support for PPAG ACPI
entries related to antenna gains.
BUG=b:193665559
TEST=Checked the SSDT entries for WRDS, EWRD, WGDS and PPAG with
different binaries generated by setting different versions in the
config.star
Change-Id: I08c3f321938eba04e8bcff4d87cb215422715bb2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com>
---
M src/drivers/wifi/generic/Kconfig
M src/drivers/wifi/generic/Makefile.inc
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/Makefile.inc
M src/vendorcode/google/chromeos/sar.c
6 files changed, 392 insertions(+), 85 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/56750/16
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Change subject: tests: Add lib/cbfs-lookup-test test case
......................................................................
Patch Set 5:
(13 comments)
File tests/lib/cbfs-lookup-test.c:
https://review.coreboot.org/c/coreboot/+/56813/comment/9e5af27d_66192792
PS4, Line 12: #define HEADER_INITIALIZER(ftype, attr_len, file_len) { \
> If you're reusing components of this CBFS mocking stuff in multiple tests, please factor them out in […]
Ok. Now it is in previous patch (libcbfs-verification-test).
https://review.coreboot.org/c/coreboot/+/56813/comment/5fdde253_e20c1e42
PS4, Line 115: BE32(CBFS_FILE_ATTR_TAG_UNUSED),
> What's this? This isn't valid. […]
So what about CBFS_FILE_ATTR_TAG_UNUSED and CBFS_FILE_ATTR_TAG_UNUSED2? They are here only for cbfstool?
https://review.coreboot.org/c/coreboot/+/56813/comment/e26fe911_d71d14e0
PS4, Line 139: },
Wow, that's a lot of cases. Thank you.
> doesn't all need to be in the same CL
You know, how it is usually - "I'll do it later" - and it is postponed indefinitely.
> - CBFS file header at a non-CBFS_ALIGNMENT boundary
Now all tests are executed for aligned and unaligned buffer (in terms of address alignment, not CBFS_ALIGNMENT)
> - CBFS files where either len, attributes_offset or offset are (uint32_t)-1 or something like that
I think, that these cases are covered by those:
> - CBFS file where the data length goes beyond the end of the rdev
> - CBFS file where attributes_offset is larger than offset
> - CBFS file where attributes_offset is smaller than sizeof(struct cbfs_file)
But I aded one case anyway - for .len = cpu_to_be32((uint32_t)-1);
If you see that I missed/didn't understand any of listed cases, then please, tell me.
https://review.coreboot.org/c/coreboot/+/56813/comment/0d535063_0f05c8c3
PS4, Line 148: __aligned(CBFS_ALIGNMENT);
> nit: technically, I don't see why this should need to be aligned? The only access function is cbfs_d […]
Done. However, I see that CBFS "aligns" files by CBFS_ALIGNMENT, but does not use ALIGN_UP/DOWN. Is it intended? Won't it cause problems in the future?
https://review.coreboot.org/c/coreboot/+/56813/comment/ab906777_73047b77
PS4, Line 153: __weak extern u8 _ecbfs_cache[];
> Why not just #include <symbols. […]
Done
https://review.coreboot.org/c/coreboot/+/56813/comment/134d828c_da07f741
PS4, Line 154: TEST_REGION(cbfs_cache, TEST_CBFS_CACHE_SIZE);
> If you're planning to link mem_pool and have a real cbfs_cache in here, I'd suggest doing the pass-t […]
Done
https://review.coreboot.org/c/coreboot/+/56813/comment/13b1765c_289b9860
PS4, Line 159: int create_cbfs(const struct cbfs_test_file **files, size_t nfiles)
> One of the lesser-tested properties of CBFS is that there may be an arbitrary amount of space behind […]
Done in test_cbfs_map() and test_cbfs_cbmem_alloc()
https://review.coreboot.org/c/coreboot/+/56813/comment/d751c247_1e93630e
PS4, Line 167: if (&data_ptr[file_size] > &cbfs_buffer[ARRAY_SIZE(cbfs_buffer) - 1])
> nit: this is checking your test data, not the code under test, so should probably just assert()?
Until it is used inside test code, not in any other place (like setup/teardown functions) it will be ok.
https://review.coreboot.org/c/coreboot/+/56813/comment/332b33dd_46deaf9b
PS4, Line 173: if ((uintptr_t)data_ptr % CBFS_ALIGNMENT != 0)
> This would of course need to check for the alignment of (data_ptr - cbfs_buffer), rather than data_p […]
Done
https://review.coreboot.org/c/coreboot/+/56813/comment/a221927a_01ba3e6e
PS4, Line 189: function_called();
> nit: I think technically you don't really need function_called() when you already have a check_expec […]
True. Checking arguments is enough here. For now.
https://review.coreboot.org/c/coreboot/+/56813/comment/3c9cb918_e9e6bdf0
PS4, Line 240: cbd.mcache_size = TEST_MCACHE_SIZE;
> This isn't actually testing the mcache? If you want to test with mcache, you have to cbfs_mcache_bui […]
Each test calls cbfs_init_boot_device() after constructing CBFS. cbfs_init_boot_device() calls cbfs_mcache_build() if required. then, mocks are configured depending on presence or absence of MCache.
https://review.coreboot.org/c/coreboot/+/56813/comment/b4a657b1_cfdb7565
PS4, Line 253: extern uintptr_t _cbmem_top_ptr;
> I'd honestly consider just mocking out the whole CBMEM part here, its internals are completely isola […]
Removing CBMEM implementation from this test is a good idea. Checking id and size should suffice.
https://review.coreboot.org/c/coreboot/+/56813/comment/8566a92c_179215e1
PS4, Line 308: size_out
> Please also test cbfs_map("filename", NULL) somewhere.
Done in:
- test_cbfs_map() -> TEST_DATA_INT_2
- test_cbfs_cbmem_alloc() -> TEST_DATA_2
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Change subject: tests: Add lib/cbfs-verification-test test case
......................................................................
Patch Set 8:
(6 comments)
File tests/include/tests/lib/cbfs_util.h:
https://review.coreboot.org/c/coreboot/+/56601/comment/9a83fbbe_46a0db9e
PS8, Line 24: 90
> Rather than having to check these by hand, I believe […]
It does work, and indeed, this is safer than hardcoded length.
https://review.coreboot.org/c/coreboot/+/56601/comment/f14992db_e2715804
PS8, Line 74: TEST_REGION(cbfs_cache, TEST_CBFS_CACHE_SIZE);
It is almost the same as for test data files. Test data file should be included only once per test (executable). However, test data is constant, and cbfs_cache is going to be written to, so I see, why you want to move cbfs_cache to its own compilation unit.
> all the corresponding struct cbfs_test_file globals for this
Sorry, but I do not understand, what you mean. Do you want me to move `TEST_REGION(cbfs_cache, TEST_CBFS_CACHE_SIZE);` to the another file and also define test files in this mock?
Defining test files in case of CBFS test does not make sense in my opinion. But if you meant to define arrays with test data for comparison with data returned by cbfs_map() etc, then it does make sense.
File tests/lib/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/56601/comment/5a914694_b74c5583
PS2, Line 199: CONFIG_NO_CBFS_MCACHE=0 \
> Well I think file verification and metadata verification are certainly different enough things that […]
Done
File tests/lib/cbfs-verification-test.c:
https://review.coreboot.org/c/coreboot/+/56601/comment/fa939a29_acad2d1d
PS2, Line 181: assert_memory_equal(mapping, &test_data, TEST_DATA_SIZE);
> That's not how this works -- CBFS cache is used by the specific rdev's mmap() implementation, not by […]
Done
https://review.coreboot.org/c/coreboot/+/56601/comment/e6b0f8a0_42d24831
PS2, Line 243: /* No cache, so no validation required */
> Not really sure what these comments mean. […]
Done
File tests/lib/cbfs-verification-test.c:
https://review.coreboot.org/c/coreboot/+/56601/comment/24d875e9_0c8b2145
PS8, Line 244: return cmocka_run_group_tests(cbfs_verification_tests, NULL, NULL);
> One problem with this copying approach I noticed is that when you run the test, it's hard to figure […]
How about adding TEST_NAME define and using it instead? And we could redefine cmocka_run_group_tests to use TEST_NAME (or default #group_tests if TEST_NAME is empty), and that would solve this problem, because each test in Makefile has to have a different name.
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Hello build bot (Jenkins), Julius Werner, Jan Dabros,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: tests: Add lib/cbfs-lookup-test test case
......................................................................
tests: Add lib/cbfs-lookup-test test case
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I2ebebba1468c19661741de8a8456605b1c5f56b6
---
M tests/lib/Makefile.inc
A tests/lib/cbfs-lookup-test.c
2 files changed, 942 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/56813/6
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Hello build bot (Jenkins), Paul Fagerburg, Julius Werner, Jan Dabros,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56601
to look at the new patch set (#9).
Change subject: tests: Add lib/cbfs-verification-test test case
......................................................................
tests: Add lib/cbfs-verification-test test case
This commit adds test case for lib/cbfs verification mechanisms.
Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com>
Change-Id: I1d8cbb1c2d0a9db3236de065428b70a9c2a66330
---
A tests/include/tests/lib/cbfs_util.h
M tests/lib/Makefile.inc
A tests/lib/cbfs-verification-test.c
A tests/mock/cbfs_file_mock.c
A tests/stubs/die.c
5 files changed, 388 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/56601/9
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Attention is currently required from: Nico Huber, Martin Roth, Matt DeVillier, Andy Pont, Paul Menzel, Stefan Reinauer, Angel Pons.
Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56223 )
Change subject: payloads/external/tianocore: Add build argument for 4G Decode
......................................................................
Patch Set 22:
(1 comment)
File payloads/external/tianocore/Makefile:
https://review.coreboot.org/c/coreboot/+/56223/comment/f6ae5fb8_75a45860
PS21, Line 38: 4G=-D ABOVE_4G_DECODE=TRUE
: else
: 4G=-D ABOVE_4G_DECODE=FALSE
> variable change to match Kconfig?
I guess we should. PR open to your branch to make it match.
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Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57005 )
Change subject: soc/amd/cezanne: Disable Co-op multitasking
......................................................................
soc/amd/cezanne: Disable Co-op multitasking
There are gremlins in the system. thread_coop_enable has an assert. This
is currently problematic for two reasons.
assert(current->can_yield <= 0);
When doing smm_do_relocate we are entering a deadlock. The root cause
hasn't been quite found yet, but it's related to co-op multi-threading.
For some reason the assert in thread_coop_enable is firing when
releasing the console_lock spin lock. I'm assuming cpu_info hasn't been
initialized yet. The assert tries to perform a printk, but since the
console_lock is still held we end up in a dead lock. This dead lock will
generally not happen after a warm reset. Again I'm assuming because the
cpu_info struct has some valid values at this point.
For now disable multi-tasking until we fix the cpu_info initialization.
BUG=b:194391185
TEST=Boot guybrush to OS
Co-developed-by: nikolai.vyssotski(a)amd.corp-partner.google.com
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ia3143f538a31b5aaaea104aa1d8bcf44e6dcb528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57005
Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com>
Reviewed-by: Rob Barnes <robbarnes(a)google.com>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 0 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Karthik Ramasubramanian: Looks good to me, approved
Rob Barnes: Looks good to me, approved
Jason Glenesk: Looks good to me, but someone else must approve
Nikolai Vyssotski: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index 306f181..81597d0 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -18,7 +18,6 @@
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select DRIVERS_USB_ACPI
select DRIVERS_I2C_DESIGNWARE
- select COOP_MULTITASKING
select DRIVERS_USB_PCI_XHCI
select FSP_COMPRESS_FSP_M_LZMA
select FSP_COMPRESS_FSP_S_LZMA
@@ -31,7 +30,6 @@
select IDT_IN_EVERY_STAGE
select IOAPIC
select PARALLEL_MP_AP_WORK
- select PAYLOAD_PRELOAD
select PLATFORM_USES_FSP2_0
select PROVIDES_ROM_SHARING
select RESET_VECTOR_IN_RAM
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