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Change subject: mb/google/guybrush: Enable PCIe L1 Substates
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Patch Set 5:
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Change subject: payloads/external/tianocore: Add build argument for 4G Decode
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Patch Set 22: Code-Review+2
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Change subject: soc/amd/common: Skip psp_verstage on S0i3 resume
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Patch Set 4: Code-Review+2
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Change subject: soc/amd/common: Show current SPI speeds and modes
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Patch Set 1:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/spi.h:
https://review.coreboot.org/c/coreboot/+/56960/comment/527af95b_ae1bda0a
PS1, Line 38: #define DECODE_SPI_READ_MODE(x) DECODE_SPI_MODE_UPPER_BITS(x) | \
would be good to add those
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Change subject: payloads/external/tianocore: Add build argument for 4G Decode
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Patch Set 22:
(1 comment)
File payloads/external/tianocore/Makefile:
https://review.coreboot.org/c/coreboot/+/56223/comment/bcb0158c_8df791fe
PS21, Line 38: 4G=-D ABOVE_4G_DECODE=TRUE
: else
: 4G=-D ABOVE_4G_DECODE=FALSE
> I guess we should. PR open to your branch to make it match.
Done
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Change subject: device_util.c: Replace `memcpy()` with `strcpy()`
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Patch Set 1: Code-Review+2
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Change subject: drivers/spkmodem: Move the driver to proper compilation unit
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Patch Set 12: Code-Review+2
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Change subject: lib/console: Use a linkerscript array for console drivers
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Patch Set 16: Code-Review+2
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Change subject: lib/console: Use a linkerscript array for console drivers
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Patch Set 16:
(1 comment)
File src/include/console/streams.h:
https://review.coreboot.org/c/coreboot/+/56472/comment/c034bacf_c7c283a3
PS16, Line 17: void (*tx_flush)(void);
> That's what I had in mind, yes. […]
This isn't currently a supported use case is it? imo, we don't need to support 2 uart consoles right now, so I think the current approach is fine.
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