Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner.
Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56588 )
Change subject: soc: common: clock: Add support for common clock driver
......................................................................
Patch Set 2:
(14 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56588/comment/3058b864_9dcf5193
PS2, Line 7: Add support for common clock driver
> > Add common clock driver
Ack
https://review.coreboot.org/c/coreboot/+/56588/comment/ab2aebba_811cf13f
PS2, Line 10: root clock generator(RCG)
> Please add a space before the (.
Ack
https://review.coreboot.org/c/coreboot/+/56588/comment/15ded691_6ea66518
PS2, Line 14: Zonda/Agera
> Please clarify what these names mean.
The are the PLL types used for CPU.
https://review.coreboot.org/c/coreboot/+/56588/comment/bf5df6e6_9961601d
PS2, Line 19: SC7180 clock driver is also refactored to use the common clock
: driver APIs.
> How did you verify it works the same? (Is there some test or log message?)
We have our test code which will set the desired frequencies and then we can measure(debugger connected tool) the frequencies requested.
https://review.coreboot.org/c/coreboot/+/56588/comment/9049150c_77eb7e31
PS2, Line 21:
> Please mention the datasheet name and revision.
Sorry Paul, we do not have any such data/revision which we can add here.
Patchset:
PS2:
> Yes, it's true that it still needs to compile and boot correctly in between the two patches. […]
Sure, will move the changes accordingly.
File src/soc/qualcomm/common/clock.c:
https://review.coreboot.org/c/coreboot/+/56588/comment/0c359740_9721b5e0
PS2, Line 20: /* Set clock vote bit */
> The comment is not needed, as the code line is self-explaining.
Done
https://review.coreboot.org/c/coreboot/+/56588/comment/d6963867_9e333b77
PS2, Line 25: return CB_ERR;
> If console works, can an error be logged?
Done
https://review.coreboot.org/c/coreboot/+/56588/comment/a11c66a7_470c981c
PS2, Line 84: idx
> Can a native type be used?
Done
https://review.coreboot.org/c/coreboot/+/56588/comment/2c0b65ff_d5aa6bee
PS2, Line 100: RCG*/
> Missing space.
Done
https://review.coreboot.org/c/coreboot/+/56588/comment/3ce4a425_e36a0210
PS2, Line 111: idx
> unsigned int?
Done
https://review.coreboot.org/c/coreboot/+/56588/comment/d20625da_dbf338be
PS2, Line 183: udelay(10);
> Why the delay? Please add a comment.
Done
https://review.coreboot.org/c/coreboot/+/56588/comment/6c9cf6f3_106ea6d3
PS2, Line 188: printk(BIOS_ERR, "ERROR: PLL did not lock!\n");
> Please not the consequence in the message. […]
Yes the CPU would be on a default general purpose PLL which would be at a very low frequency.
https://review.coreboot.org/c/coreboot/+/56588/comment/ef82d078_a9ea423c
PS2, Line 199: udelay(5);
> Why the delay? Please add a comment.
Done
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TeddyShih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56716 )
Change subject: mb/google/dedede: Create bugzzy variant
......................................................................
mb/google/dedede: Create bugzzy variant
Create the bugzzy variant of the waddledoo reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:192521391
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BUGZZY
Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com>
Change-Id: I0f1eefe80831f96b167e920e84bb7804e45e91d1
---
M src/mainboard/google/dedede/Kconfig
M src/mainboard/google/dedede/Kconfig.name
A src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h
A src/mainboard/google/dedede/variants/bugzzy/include/variant/gpio.h
A src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc
A src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt
A src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt
A src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
8 files changed, 100 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/56716/1
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 3cf1a3a..9437ddc 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -111,6 +111,7 @@
default "Haboki" if BOARD_GOOGLE_HABOKI
default "Cappy" if BOARD_GOOGLE_CAPPY
default "Cappy2" if BOARD_GOOGLE_CAPPY2
+ default "Bugzzy" if BOARD_GOOGLE_BUGZZY
config MAX_CPUS
int
@@ -148,6 +149,7 @@
default "haboki" if BOARD_GOOGLE_HABOKI
default "cappy" if BOARD_GOOGLE_CAPPY
default "cappy2" if BOARD_GOOGLE_CAPPY2
+ default "bugzzy" if BOARD_GOOGLE_BUGZZY
endif #BOARD_GOOGLE_BASEBOARD_DEDEDE
diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name
index 6cdd4de..98a2298 100644
--- a/src/mainboard/google/dedede/Kconfig.name
+++ b/src/mainboard/google/dedede/Kconfig.name
@@ -159,3 +159,10 @@
bool "-> Cappy2"
select BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
select BASEBOARD_DEDEDE_LAPTOP
+
+config BOARD_GOOGLE_BUGZZY
+ bool "-> Bugzzy"
+ select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
+ select BASEBOARD_DEDEDE_LAPTOP
+ select DRIVERS_GENERIC_MAX98357A
+ select DRIVERS_I2C_DA7219
diff --git a/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h b/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h
new file mode 100644
index 0000000..08870e0
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif
diff --git a/src/mainboard/google/dedede/variants/bugzzy/include/variant/gpio.h b/src/mainboard/google/dedede/variants/bugzzy/include/variant/gpio.h
new file mode 100644
index 0000000..9078664
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/include/variant/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <baseboard/gpio.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc b/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc
new file mode 100644
index 0000000..b0ca222
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/memory/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
+
+SPD_SOURCES = placeholder.spd.hex
diff --git a/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt
new file mode 100644
index 0000000..fa24790
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/memory/dram_id.generated.txt
@@ -0,0 +1 @@
+DRAM Part Name ID to assign
diff --git a/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt
new file mode 100644
index 0000000..e4258b5
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/memory/mem_parts_used.txt
@@ -0,0 +1,11 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.inc and dram_id.generated.txt by running the
+# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
+# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
+
+# Part Name
diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
new file mode 100644
index 0000000..69ea1e1
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
@@ -0,0 +1,58 @@
+chip soc/intel/jasperlake
+
+ # USB Port Configuration
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| I2C0 | Trackpad |
+ #| I2C1 | Digitizer |
+ #| I2C2 | Touchscreen |
+ #| I2C3 | Camera |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 66,
+ .fall_time_ns = 90,
+ .data_hold_time_ns = 350,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_FAST,
+ .scl_lcnt = 176,
+ .scl_hcnt = 95,
+ .sda_hold = 36,
+ }
+ },
+ }"
+ device domain 0 on
+ device pci 14.0 on end
+ device pci 15.0 on end
+ device pci 15.2 on end
+ device pci 1c.7 on end
+ device pci 19.0 on end
+ device pci 1f.3 on end
+ end
+end
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Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56715 )
Change subject: mb/google/brya/variants/gimble: add TcssAuxOri
......................................................................
mb/google/brya/variants/gimble: add TcssAuxOri
Gimble don't have retimer on port0, the port need to be configured for the SOC to handle Aux orientation flipping.
BUG=b:195087071
BRANCH=none
TEST=check both orientation can output display on type-c monitor.
Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com>
Change-Id: I057048c14110bb81bf5b5fd0e3151deb031ca5d4
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/56715/1
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 914a8bf..2c991ad 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -20,6 +20,7 @@
end
end
chip soc/intel/alderlake
+ register "TcssAuxOri" = "1"
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56165 )
Change subject: mb/google/brya: Update the FIVR configurations
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56165/comment/3db8cc7f_8ff44708
PS5, Line 9: This patch sets the disable the external voltage rails
It’s hard for me to understand.
> Disable the external voltage rails, since brya board …
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56687 )
Change subject: mb/google/dedede/var/cappy2: Disable external bypass VR
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56687/comment/94d7cd6a_0d6a98ff
PS4, Line 9: anpec apw8738bqbi
In what commit/change-set, was that removed?
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Hello build bot (Jenkins), Patrick Georgi, Henry Sun, Ben Kao, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56729
to look at the new patch set (#2).
Change subject: Revert "mb/google/dedede/var/cret: Disable SDCard controller"
......................................................................
Revert "mb/google/dedede/var/cret: Disable SDCard controller"
This reverts commit f29437862269de24f85392d49f6afa6fa60ac43e.
Reason for revert: It makes cret can't boot to os without depthcharge change. The depthcharge change related with fw_config and will effect other variants.
BUG=b:194961854
TEST=Build and boot to OS.
Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>
Change-Id: I929369c9419375e74be61a4ff3e5566b0f41ce65
---
M src/mainboard/google/dedede/variants/cret/overridetree.cb
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/56729/2
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56515 )
Change subject: mb/google/brya: create dynamic power limits mechanism for thermal
......................................................................
Patch Set 6:
(2 comments)
File src/mainboard/google/brya/variants/baseboard/ramstage.c:
https://review.coreboot.org/c/coreboot/+/56515/comment/68547b2c_26a2401a
PS5, Line 31: variant_update_power_limits
> Ah, I see. Let's go with this for now.
Sure, Thank you.
File src/mainboard/google/brya/variants/brya0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/56515/comment/5750da5a_400ea2b2
PS1, Line 30: field THERMAL 15 17
: option POWER_LIMITS_282 0
: option POWER_LIMITS_482 1
: option POWER_LIMITS_682 2
: end
> I think the FW_CONFIG bits aren't necessary for selecting power limits, if they can be done by CPU S […]
Ack
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Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56687 )
Change subject: mb/google/dedede/var/cappy2: Disable external bypass VR
......................................................................
Patch Set 4: Code-Review+1
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Change subject: mb/google/dedede/var/cappy2: Add Tpm2.0 device support
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Patch Set 5: Code-Review+1
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Aaron Durbin, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56515
to look at the new patch set (#6).
Change subject: mb/google/brya: create dynamic power limits mechanism for thermal
......................................................................
mb/google/brya: create dynamic power limits mechanism for thermal
Add dynamic power limits selection mechanism for brya board based on
CPU SKUs which is detectable at runtime.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya with below messages,
On brya (282):
Overriding DPTF power limits PL1 (3000, 15000) PL2 (39000, 39000)
On brya (482):
Overriding DPTF power limits PL1 (4000, 28000) PL2 (43000, 43000)
Change-Id: I86619516adeec13642f02ba7faf9fc4945ad774e
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/mainboard/google/brya/mainboard.c
M src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc
M src/mainboard/google/brya/variants/baseboard/brya/include/baseboard/variants.h
A src/mainboard/google/brya/variants/baseboard/ramstage.c
4 files changed, 73 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/56515/6
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