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Change subject: mb/intel/adlrvp_m: Enable SaGv support
......................................................................
Patch Set 6: Code-Review+1
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Tim Wawrzynczak has uploaded a new patch set (#2) to the change originally created by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/56511 )
Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01
......................................................................
vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01
The headers added are generated as per FSP v2265_01.
Previous FSP version was v2237_00.
Changes Include:
- Add Irms UPD in FspsUpd.h
- Adjust Reserved UPD Offset in FspsUpd.h
- Few UPDs description update in FspmUpd.h
BUG=b:194032028
BRANCH=None
TEST=Build and boot brya
Change-Id: I49b1187d9dcedade47951274db49b7bdc437679f
Cq-Depend:chrome-internal:4004482
Cq-Depend:chrome-internal:4003608
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h
2 files changed, 32 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/56511/2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56676 )
Change subject: soc/amd/common/block/acpimmio: add remote GPIO bank access helpers
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/acpimmio.h:
https://review.coreboot.org/c/coreboot/+/56676/comment/75252030_b164772c
PS2, Line 347: functons is the offset from the first remote GPIO which is GPIO 256. remote_gpio_read8 and
done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/common/block/acpimmio: add remote GPIO bank access helpers
......................................................................
soc/amd/common/block/acpimmio: add remote GPIO bank access helpers
Currently coreboot for the AMD SOCs only supports accessing the up to 4
main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne
have another GPIO bank in the ACPIMMIO region that can contain up to 48
GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The
first 0xc0 bytes of that ACPIMMIO bank are the 32 bit wide GPIO
registers and beginning at offset 0xc0 it has the corresponding 8 bit
wide GPIO MUX registers.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926
---
M src/soc/amd/common/block/acpimmio/mmio_util.c
M src/soc/amd/common/block/include/amdblocks/acpimmio.h
M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
3 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/56676/3
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Change subject: soc/amd/common/block/acpimmio: add remote GPIO bank access helpers
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/acpimmio.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-125499):
https://review.coreboot.org/c/coreboot/+/56676/comment/66cf416a_6a876016
PS2, Line 347: functons is the offset from the first remote GPIO which is GPIO 256. remote_gpio_read8 and
'functons' may be misspelled - perhaps 'functions'?
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56676
to look at the new patch set (#2).
Change subject: soc/amd/common/block/acpimmio: add remote GPIO bank access helpers
......................................................................
soc/amd/common/block/acpimmio: add remote GPIO bank access helpers
Currently coreboot for the AMD SOCs only supports accessing the up to 4
main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne
have another GPIO bank in the ACPIMMIO region that can contain up to 48
GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The
first 0xc0 bytes of that ACPIMMIO bank are the 32 bit wide GPIO
registers and beginning at offset 0xc0 it has the corresponding 8 bit
wide GPIO MUX registers.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926
---
M src/soc/amd/common/block/acpimmio/mmio_util.c
M src/soc/amd/common/block/include/amdblocks/acpimmio.h
M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h
3 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/56676/2
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56593 )
Change subject: util/lint/lint-stable: Add forbidden Kconfig check
......................................................................
Patch Set 2:
(1 comment)
File util/lint/lint-stable-028-forbidden-config-c:
https://review.coreboot.org/c/coreboot/+/56593/comment/e057bd2f_b300e2cc
PS2, Line 23: -I %
> Not sure why you'd want to use that. At least on a GNU system, it makes […]
We should probably use both methods, similar to what's done in the whitespace linter.
Here's where this pattern was introduced:
https://review.coreboot.org/c/coreboot/+/28429/
If we can speed this pattern up, that'd be great. It looks like this was the best I could find at the time that worked on bsd systems for the whitespace check. If we update it, let's make sure we check it there.
We should also probably break some of these patterns out into a library so that if we find a better solution, we don't have to rewrite it in all of the checkers.
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Change subject: util/kconfig: Provide default for DEFCONFIG
......................................................................
Patch Set 1: Code-Review+2
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