coreboot-gerrit July 2021

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Change in coreboot[master]: soc/amd/common/block/include/gpio_banks: use gpio_t for gpio numbers
by Marshall Dawson (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56693 ) Change subject: soc/amd/common/block/include/gpio_banks: use gpio_t for gpio numbers ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051 Gerrit-Change-Number: 56693 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jul 2021 22:08:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/gpio_banks/gpio: use gpio_t for GPIO numbers
by Marshall Dawson (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56700 ) Change subject: soc/amd/common/block/gpio_banks/gpio: use gpio_t for GPIO numbers ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Maybe change gpio_read32() and _write32() to accept gpio_t ahead of this patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/56700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cf9cbd2a287dcfe3a47a8a6b164c2b3d8ae95d6 Gerrit-Change-Number: 56700 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 30 Jul 2021 22:08:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/kconfig: detect ncurses on FreeBSD
by Martin Roth (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Idwer Vollering. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56677 ) Change subject: util/kconfig: detect ncurses on FreeBSD ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS4: I don't see an issue with adding this to support bsd. -- To view, visit https://review.coreboot.org/c/coreboot/+/56677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4344ba2116c0b8618357db4248d993509cbb666e Gerrit-Change-Number: 56677 Gerrit-PatchSet: 4 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Fri, 30 Jul 2021 21:47:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,tgl}: Make SOC_INTEL_CRASHLOG depend on DEBUG_SOC_HOOKS
by Tim Wawrzynczak (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56727 ) Change subject: soc/intel/{adl,tgl}: Make SOC_INTEL_CRASHLOG depend on DEBUG_SOC_HOOKS ...................................................................... soc/intel/{adl,tgl}: Make SOC_INTEL_CRASHLOG depend on DEBUG_SOC_HOOKS I consider this a "vendor-specific debug hook", therefore guard it with DEBUG_SOC_HOOKS. BUG=b:190626785 Change-Id: Idc3ca88a8d4b665a4c954183757542cd9779066d Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig.name M src/soc/intel/alderlake/Kconfig M src/soc/intel/tigerlake/Kconfig 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/56727/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 03a14e4..57f55fd 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -5,7 +5,7 @@ select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU - select SOC_INTEL_CRASHLOG + select SOC_INTEL_CRASHLOG if DEBUG_SOC_HOOKS config BOARD_GOOGLE_PRIMUS bool "-> Primus" diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f77b4c3..8888d28 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -303,6 +303,7 @@ config SOC_INTEL_CRASHLOG def_bool n + depends on DEBUG_SOC_HOOKS select SOC_INTEL_COMMON_BLOCK_CRASHLOG select ACPI_BERT help diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d506800..2b0b355 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -273,6 +273,7 @@ config SOC_INTEL_CRASHLOG def_bool n + depends on DEBUG_SOC_HOOKS select SOC_INTEL_COMMON_BLOCK_CRASHLOG select ACPI_BERT help -- To view, visit https://review.coreboot.org/c/coreboot/+/56727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc3ca88a8d4b665a4c954183757542cd9779066d Gerrit-Change-Number: 56727 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Add new Kconfig DEBUG_SOC_HOOKS
by Tim Wawrzynczak (Code Review) 31 Jul '21

31 Jul '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56726 ) Change subject: src: Add new Kconfig DEBUG_SOC_HOOKS ...................................................................... src: Add new Kconfig DEBUG_SOC_HOOKS The intent of this Kconfig is, when selected, to compile in any vendor-specific hooks that may be available. BUG=b:190626785 Change-Id: If0e7f076bb7e3b630c3ab9d28071312d3e21e927 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/56726/1 diff --git a/src/Kconfig b/src/Kconfig index 6b60767..fa87dbd 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1182,6 +1182,12 @@ Add the compiler switch `-gnata` to compile code guarded by `pragma Debug`. +config DEBUG_SOC_HOOKS + bool "Add SoC vendor debug support" + default n + help + Add in any debug hooks that SoC vendors provide. + config HAVE_EM100_SUPPORT bool "Platform can support the Dediprog EM100 SPI emulator" help -- To view, visit https://review.coreboot.org/c/coreboot/+/56726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0e7f076bb7e3b630c3ab9d28071312d3e21e927 Gerrit-Change-Number: 56726 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Configure H21 as GPO and A17 as low
by Tim Wawrzynczak (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56655 ) Change subject: mb/google/brya: Configure H21 as GPO and A17 as low ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I745169a5ab6a9c20b6e1bda792a43193d04ac48d Gerrit-Change-Number: 56655 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Fri, 30 Jul 2021 20:39:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Update entries for UFC to support IMX208
by Tim Wawrzynczak (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Varshit B Pandya, Paul Menzel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56621 ) Change subject: mb/google/brya: Update entries for UFC to support IMX208 ...................................................................... Patch Set 9: (2 comments) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/56621/comment/913b5d0f_90dd57b6 PS9, Line 437: 360 Update the comment? https://review.coreboot.org/c/coreboot/+/56621/comment/693c403b_eb787759 PS9, Line 438: 180 MHz Update the comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/56621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a3bf13ec844fb46e11ce58382057fcc7187c135 Gerrit-Change-Number: 56621 Gerrit-PatchSet: 9 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 30 Jul 2021 20:39:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Document USB mapping in devicetree
by Rob Barnes (Code Review) 31 Jul '21

31 Jul '21

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56725 ) Change subject: mb/google/guybrush: Document USB mapping in devicetree ...................................................................... mb/google/guybrush: Document USB mapping in devicetree Add a short documenting comment to each usb entry in devicetree so it is clear which function each usb port maps to. Fix inverted mapping in drivers/usb/acpi. BUG=None TEST=Build BRANCH=None Change-Id: I14cbb6af021bb27c89aa82456722f21aa09617be Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 20 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/56725/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index cf0f515..902a416 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -62,6 +62,7 @@ register "usb_phy_custom" = "1" register "usb_phy" = "{ + /* Left USB C0 Port */ .Usb2PhyPort[0] = { .compdstune = 3, .sqrxtune = 3, @@ -73,6 +74,7 @@ .txhsxvtune = 3, .txrestune = 1, }, + /* Left USB A0 Port or WWAN */ .Usb2PhyPort[1] = { .compdstune = 3, .sqrxtune = 3, @@ -84,6 +86,7 @@ .txhsxvtune = 3, .txrestune = 1, }, + /* User facing camera */ .Usb2PhyPort[2] = { .compdstune = 1, .sqrxtune = 3, @@ -95,6 +98,7 @@ .txhsxvtune = 3, .txrestune = 2, }, + /* World facing camera */ .Usb2PhyPort[3] = { .compdstune = 1, .sqrxtune = 3, @@ -106,6 +110,7 @@ .txhsxvtune = 3, .txrestune = 2, }, + /* Right USB C1 Port */ .Usb2PhyPort[4] = { .compdstune = 3, .sqrxtune = 3, @@ -117,6 +122,7 @@ .txhsxvtune = 3, .txrestune = 1, }, + /* Right USB A1 Port */ .Usb2PhyPort[5] = { .compdstune = 3, .sqrxtune = 3, @@ -128,6 +134,7 @@ .txhsxvtune = 3, .txrestune = 1, }, + /* WiFi / Bluetooth */ .Usb2PhyPort[6] = { .compdstune = 1, .sqrxtune = 3, @@ -139,6 +146,7 @@ .txhsxvtune = 3, .txrestune = 2, }, + /* Smart Card */ .Usb2PhyPort[7] = { .compdstune = 1, .sqrxtune = 3, @@ -150,25 +158,28 @@ .txhsxvtune = 3, .txrestune = 2, }, - + /* Left USB C0 Port */ .Usb3PhyPort[0] = { .tx_term_ctrl=2, .rx_term_ctrl=2, .tx_vboost_lvl_en=1, .tx_vboost_lvl=5, }, + /* Left USB A0 Port or WWAN */ .Usb3PhyPort[1] = { .tx_term_ctrl=2, .rx_term_ctrl=2, .tx_vboost_lvl_en=1, .tx_vboost_lvl=5, }, + /* Right USB C1 Port */ .Usb3PhyPort[2] = { .tx_term_ctrl=2, .rx_term_ctrl=2, .tx_vboost_lvl_en=1, .tx_vboost_lvl=5, }, + /* Right USB A1 Port */ .Usb3PhyPort[3] = { .tx_term_ctrl=2, .rx_term_ctrl=2, @@ -210,25 +221,25 @@ chip drivers/usb/acpi device ref xhci_0_root_hub on chip drivers/usb/acpi - register "desc" = ""Right Type-C Port"" + register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 1)" device ref usb3_port0 on end end chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" + register "desc" = ""Left Type-A Port"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 2)" device ref usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""Right Type-C Port"" + register "desc" = ""Left Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 1)" device ref usb2_port0 on end end chip drivers/usb/acpi - register "desc" = ""Right Type-A Port"" + register "desc" = ""Left Type-A Port"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 2)" device ref usb2_port1 on end @@ -250,25 +261,25 @@ chip drivers/usb/acpi device ref xhci_1_root_hub on chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" + register "desc" = ""Right Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 2)" device ref usb3_port4 on end end chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" + register "desc" = ""Right Type-A Port"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb3_port5 on end end chip drivers/usb/acpi - register "desc" = ""Left Type-C Port"" + register "desc" = ""Right Type-C Port"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 2)" device ref usb2_port4 on end end chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" + register "desc" = ""Right Type-A Port"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port5 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/56725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14cbb6af021bb27c89aa82456722f21aa09617be Gerrit-Change-Number: 56725 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Move WWAN PCIe config to brya0
by Tim Wawrzynczak (Code Review) 31 Jul '21

31 Jul '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56724 ) Change subject: mb/google/brya: Move WWAN PCIe config to brya0 ...................................................................... mb/google/brya: Move WWAN PCIe config to brya0 So far the PCIe WWAN configuration is specific to brya0, therefore move the configuration to the overridetree. While there, also add a new chip and device in order to add the ExternalFacingPort property to this same root port. BUG=b:190408519 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I53fa12dff25ba970b5d7d7be4bc1f8e52a0ed4ae --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/brya/variants/brya0/overridetree.cb 3 files changed, 14 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/56724/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d1b6f24..4c02495 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -9,6 +9,7 @@ select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_PCIE_EXTERNAL select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_SOUNDWIRE_MAX98373 select DRIVERS_SPI_ACPI diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 12bff55..90b4f1c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -138,14 +138,6 @@ end device ref heci1 on end device ref sata on end - device ref pcie_rp6 on - # Enable WWAN PCIE 6 using clk 5 - register "pch_pcie_rp[PCH_RP(6)]" = "{ - .clk_src = 5, - .clk_req = 5, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - }" - end #PCIE6 WWAN device ref pcie_rp8 on # Enable SD Card PCIE 8 using clk 3 register "pch_pcie_rp[PCH_RP(8)]" = "{ diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index d4653bc..11d6be9 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -162,7 +162,19 @@ end device ref pcie_rp6 on probe DB_LTE LTE_PCIE - end + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + chip drivers/pcie/external + device generic 0 on + probe DB_LTE LTE_PCIE + end + end + end #PCIE6 WWAN device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" -- To view, visit https://review.coreboot.org/c/coreboot/+/56724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53fa12dff25ba970b5d7d7be4bc1f8e52a0ed4ae Gerrit-Change-Number: 56724 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/pcie/: Add new `external` chip driver
by Tim Wawrzynczak (Code Review) 31 Jul '21

31 Jul '21

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56723 ) Change subject: drivers/pcie/: Add new `external` chip driver ...................................................................... drivers/pcie/: Add new `external` chip driver The soc/intel/common/block/pcie/rtd3 chip driver, which is an ACPI driver, in addition to other things, adds a _DSD that specifies the "ExternalFacingPort" property. This property is also useful on its own, as it usually tells the operating system that any downstream DMA is from an external source and should be handled especially carefully. Therefore, copy this section of that driver out into a new driver. BUG=b:190408519 TEST=With next patch, disassemble SSDT on brya0 and find: Scope (\_SB.PCI0.RP01) { Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"), Package (0x01) { Package (0x02) { "ExternalFacingPort", One } } }) } Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I357cd673ad816bb954815ed3c9e4d4f70843a01d --- A src/drivers/pcie/external/Kconfig A src/drivers/pcie/external/Makefile.inc A src/drivers/pcie/external/chip.c A src/drivers/pcie/external/chip.h 4 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/56723/1 diff --git a/src/drivers/pcie/external/Kconfig b/src/drivers/pcie/external/Kconfig new file mode 100644 index 0000000..5cef7bf --- /dev/null +++ b/src/drivers/pcie/external/Kconfig @@ -0,0 +1,8 @@ +config DRIVERS_PCIE_EXTERNAL + bool + default n + help + This config option adds the "ExternalFacingPort" property in a _DSD + for the PCIe root port any chip devices are added under. More + information can be found at + https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-… diff --git a/src/drivers/pcie/external/Makefile.inc b/src/drivers/pcie/external/Makefile.inc new file mode 100644 index 0000000..cca7e3b --- /dev/null +++ b/src/drivers/pcie/external/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_PCIE_EXTERNAL) += chip.c diff --git a/src/drivers/pcie/external/chip.c b/src/drivers/pcie/external/chip.c new file mode 100644 index 0000000..a9054a0 --- /dev/null +++ b/src/drivers/pcie/external/chip.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <console/console.h> +#include <device/device.h> + +/* + * The "ExternalFacingPort" property is defined at + * https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-… + */ +#define PCIE_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" +#define PCIE_EXTERNAL_PORT_PROPERTY "ExternalFacingPort" + +static void external_rp_fill_ssdt(const struct device *dev) +{ + const struct device *parent = dev->bus->dev; + const char *scope; + struct acpi_dp *dsd, *pkg; + + if (!parent || !is_dev_enabled(parent)) { + printk(BIOS_ERR, "%s: Disabled PCIe root port\n", __func__); + return; + } + + scope = acpi_device_path(parent); + if (!scope) { + printk(BIOS_ERR, "%s: root port scope not found\n", __func__); + return; + } + + /* Indicate to the OS if the device provides an External facing port. */ + dsd = acpi_dp_new_table("_DSD"); + pkg = acpi_dp_new_table(PCIE_EXTERNAL_PORT_UUID); + acpi_dp_add_integer(pkg, PCIE_EXTERNAL_PORT_PROPERTY, 1); + acpi_dp_add_package(dsd, pkg); + + printk(BIOS_INFO, "%s: Added " PCIE_EXTERNAL_PORT_PROPERTY " property\n", scope); + + acpi_dp_write(dsd); + acpigen_write_scope_end(); +} + +static struct device_operations external_rp_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = external_rp_fill_ssdt, +}; + +static void external_rp_acpi_enable(struct device *dev) +{ + dev->ops = &external_rp_ops; +} + +struct chip_operations drivers_pcie_external_ops = { + CHIP_NAME("Intel PCIe Runtime D3") + .enable_dev = external_rp_acpi_enable, +}; diff --git a/src/drivers/pcie/external/chip.h b/src/drivers/pcie/external/chip.h new file mode 100644 index 0000000..ff9a251 --- /dev/null +++ b/src/drivers/pcie/external/chip.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_PCIE_EXTERNAL_H__ +#define __DRIVERS_PCIE_EXTERNAL_H__ + +struct drivers_pcie_external_config { +}; + +#endif /* __DRIVERS_PCIE_EXTERNAL_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I357cd673ad816bb954815ed3c9e4d4f70843a01d Gerrit-Change-Number: 56723 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021