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Change subject: mb/google/brya/variants/gimble: add TcssAuxOri
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/brya/variants/gimble/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/56715/comment/5b48a08c_48c97183
PS1, Line 23: register "TcssAuxOri" = "1"
> Without a retimer on port 0, I think you will also need to do the following: […]
Done
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56715
to look at the new patch set (#2).
Change subject: mb/google/brya/variants/gimble: add TcssAuxOri
......................................................................
mb/google/brya/variants/gimble: add TcssAuxOri
Gimble don't have retimer on port0, the port need to be configured for the SOC to handle Aux orientation flipping.
Also add "typec_aux_bias_pads" lets the SoC IOM firmware control the Aux DC bias voltages.
BUG=b:195087071
BRANCH=none
TEST=check both orientation can output display on type-c monitor.
Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com>
Change-Id: I057048c14110bb81bf5b5fd0e3151deb031ca5d4
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
M src/mainboard/google/brya/variants/gimble/overridetree.cb
2 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/56715/2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56700 )
Change subject: soc/amd/common/block/gpio_banks/gpio: use gpio_t for GPIO numbers
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> IIRC I didn't do that since gpio_t is defined in gpio_banks.h and including that in acpimmio. […]
untangling that part of the gpio code a bit is probably a good idea; will look into that next week
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56705 )
Change subject: soc/amd/common/block/gpio_banks: use unsigned int for gevent parameter
......................................................................
soc/amd/common/block/gpio_banks: use unsigned int for gevent parameter
A valid GEVENT number is never negative. The local variable in
set_single_gpio still needs to be a signed integer, since the return
value of get_gpio_gevent being -1 indicates that the GPIO can't generate
a GEVENT. The check for that makes the function return before calling
program_smi of program_sci, so the parameter of those functions can be
changed to unsigned.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I6ce23ceed1585589932824b8cab2a138328672a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56705
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/common/block/gpio_banks/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 8cfca8b..8f84cb6 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -27,7 +27,7 @@
return -1;
}
-static void program_smi(uint32_t flags, int gevent_num)
+static void program_smi(uint32_t flags, unsigned int gevent_num)
{
uint8_t level;
@@ -52,7 +52,7 @@
* In a similar fashion, polarity (rising/falling, hi/lo) of each GPE is
* represented as a single bit in SMI_SCI_TRIG register.
*/
-static void program_sci(uint32_t flags, int gevent_num)
+static void program_sci(uint32_t flags, unsigned int gevent_num)
{
struct sci_source sci;
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56703 )
Change subject: soc/amd/common/block/gpio_banks/gpio: add comment in check_gpios
......................................................................
soc/amd/common/block/gpio_banks/gpio: add comment in check_gpios
Each bit in the GPIO wake status index registers is set to 1 when at
least one of 4 corresponding GPIO pins has its wake status register set.
Added the comment since the gpio_base + i * 4 in the next line looked as
if it calculates some absolute register value which is not what the code
does or should be doing.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/common/block/gpio_banks/gpio.c
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 7564aa2..24925bd 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -308,6 +308,7 @@
for (i = 0; i < bit_limit; i++) {
if (!(wake_stat & BIT(i)))
continue;
+ /* Each wake status register bit is for 4 GPIOs that then will be checked */
begin = gpio_base + i * 4;
end = begin + 4;
/* There is no gpio 63. */
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56702 )
Change subject: soc/amd/common/block/gpio_banks/gpio: use size_t where needed
......................................................................
soc/amd/common/block/gpio_banks/gpio: use size_t where needed
Since the parameter the variable gets compared with is size_t type, use
size_t as type for that variable too.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
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---
M src/soc/amd/common/block/gpio_banks/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c
index 108635a..7564aa2 100644
--- a/src/soc/amd/common/block/gpio_banks/gpio.c
+++ b/src/soc/amd/common/block/gpio_banks/gpio.c
@@ -18,7 +18,7 @@
static int get_gpio_gevent(gpio_t gpio, const struct soc_amd_event *table,
size_t items)
{
- int i;
+ size_t i;
for (i = 0; i < items; i++) {
if ((table + i)->gpio == gpio)
--
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Change subject: soc/amd/common/block/acpimmio: add remote GPIO bank access helpers
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/include/amdblocks/acpimmio.h:
https://review.coreboot.org/c/coreboot/+/56676/comment/f7bf2297_4411d945
PS3, Line 347: offset from the first remote GPIO which is GPIO 256
> Is there a good reason to do this vs. […]
i'd say that the parameter being the offset in 32 byte registers into the remote GPIO MMIO region is less unexpected than the MMIO access function subtracting 256 from the parameter which makes it easy to use the functions wrongly, since calling it with a parameter < 256 would result in rather unexpected behavior compared how the rest of the functions in here behave
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Change subject: ec/google/chromeec: Add code for KEY_MICMUTE and KEY_KBDILLUMTOGGLE
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Scott, src/ec/google/chromeec/ec_commands. […]
I also added a change on platform/ec/include/ec_commands.h. Please see https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060242
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Hello Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56728
to look at the new patch set (#2).
Change subject: MAINTAINERS: Update vboot maintainers
......................................................................
MAINTAINERS: Update vboot maintainers
Add current maintainers for vboot-related code, and combine the vboot
and vboot2 sections which are not really separate anymore. What's left
in vendorcode/google/chromeos isn't really related to vboot anymore
since the vboot code was moved under src/security, so take it out of
there.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I59a2df9c1580291a6d29537868aab0e1b339a2ce
---
M MAINTAINERS
1 file changed, 4 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/56728/2
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