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Change in coreboot[master]: Documentation: Add documentation for resource allocator
by Furquan Shaikh (Code Review) 25 Aug '21

25 Aug '21

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43603 ) Change subject: Documentation: Add documentation for resource allocator ...................................................................... Documentation: Add documentation for resource allocator This change adds documentation for resource allocator in coreboot which captures the expectations from device and platform drivers and details about resource allocator v3 and v4. Change-Id: I887284b44df2bf871f45c3a93fbef9cfc37e42a0 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- A Documentation/device/index.md A Documentation/device/resource_allocation.md M Documentation/index.md 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43603/1 diff --git a/Documentation/device/index.md b/Documentation/device/index.md new file mode 100644 index 0000000..9b703d6 --- /dev/null +++ b/Documentation/device/index.md @@ -0,0 +1,6 @@ +# Device management specific documentation + +This section contains documentation about device management in +coreboot. + +- [Resource allocation](resource_allocation.md) diff --git a/Documentation/device/resource_allocation.md b/Documentation/device/resource_allocation.md new file mode 100644 index 0000000..e82b1c1 --- /dev/null +++ b/Documentation/device/resource_allocation.md @@ -0,0 +1,88 @@ +# Resource allocation in coreboot + +## Introduction + +Resource allocator in coreboot is responsible for assigning parts of the address space to devices. It handles two types of resource requests from devices viz. IO (IORESOURCE_IO) and MMIO (IORESOURCE_MEM). It is typically used for PCI devices, but it also keeps track of other assignments to ensure that there are no conflicts + +## Principles followed by the resource allocator + +Resource allocator follows these basic principles: + +* Allocate address space for every device resource as long as its requirement can be satisfied. +* Don’t overlap with resources in fixed locations. +* Don’t overlap with other resource allocations and follow the rules of bridges i.e. downstream devices of bridges should use parts of the address space allocated to the bridge. + +## Pre-allocation and post-allocation requirements + +The main function that is responsible for allocating resources is `allocate_resources()` and gets called in the `BS_DEV_RESOURCES` boot state. The resource allocator depends upon the device and platform drivers to perform pre-allocation and post-allocation operations. Pre-allocation step requires that the device and platform drivers provide a complete map of fixed resources (resources not changed by the allocator) owned by the device/platform and a list of resource requests that need to be satisfied by the allocator. This is done as part of the `read_resources()` device operation. This step is critical to ensure that the resource allocator can perform its operation correctly as per the principles outlined above. In the post-allocation step, the device and platform drivers are expected to assign the address space allocated by the allocator to the resources requested by the device. This is done as part of the `set_resources()` device operation. This allows the resource allocator to perform its operation independent of platform and device type. + +## Input and output rules for the resource allocator + +As mentioned above, the entrypoint into the resource allocator is `allocate_resources()`. One of the important goals of the allocator is to perform its operation independent of platform and device type. In order to accomplish this, it is important to clearly define what goes into the allocator and what comes out of it. This determines the expected behavior from the device and platform drivers. + +The allocator processes all devices in each domain sub-tree and performs allocation for resources of the following types: +* IORESOURCE_IO +* IORESOURCE_MEM + +On the other hand, it does not change resources marked with IORESOURCE_FIXED flag. These are referred to as “fixed resources”. Resources that have the IORESOURCE_BRIDGE flag set are referred to as “bridge resources”. + + +### Input Rules + +1. IORESOURCE_IO and IORESOURCE_MEM are mutually exclusive. Both the flags must never be set for the same resource. +1. Resources that should not be changed by the allocator must be marked with IORESOURCE_FIXED flag. These resources must be pre-assigned a valid `base` address. It is used by the allocator to ensure there are no conflicts during the allocation step. +1. A fixed resource must not overlap with any other fixed resource within the same address space (IO / MEM), unless either of them is a bridge resource. +1. A fixed bridge resource must not overlap with any other fixed resource within the same address space and on the same bus (i.e. same device or its siblings), unless exactly one of them has IORESOURCE_SUBTRACTIVE set. + +### Output Rules + +1. All device attributes (members of `struct device` structure) beside non-fixed resources are left unaltered. +1. The structure of resource lists (`next` pointers) is left unaltered. +1. The `index` and `gran` attributes of all resources are left unaltered. +1. The `size`, `limit` and `align` attributes of all non-bridge resources are left unaltered. +1. All non-fixed assigned resources downstream of a bridge are covered by an assigned bridge resource of that bridge. +1. IORESOURCE_ASSIGNED flag is set for a non-fixed resource only if it is assigned address space by the allocator. If allocation for a non-fixed resource fails for any reason, all the attributes of that resource are left untouched including resource flags. It is the responsibility of the device and platform driver to check the IORESOURCE_ASSIGNED flag before using the values stored in the `base` field of the resource. + +## Resource allocator implementations + +Currently, there are two flavors of resource allocators implemented in coreboot - v3 and v4. + +### Resource Allocator v3 + +This is the older resource allocator which is used only on the following platforms: + +* northbridge/amd/pi/00630F01 +* northbridge/amd/pi/00730F01 +* northbridge/amd/pi/00660F01 +* northbridge/amd/agesa/family14 +* northbridge/amd/agesa/family15tn +* northbridge/amd/agesa/family16kb + +Resource allocator v3 is still retained and used for the above platforms because these platforms do not conform to the requirements of the allocator i.e. not all the fixed resources of the platform are provided during the `read_resources()` operation. This results in the resource allocator not getting a complete view of the address space. These platforms still work okay with the older resource allocator because of the way it performs allocation in a single window of the address space. No platform other than the ones listed above must use resource allocator v3 as it will be deprecated once the above platforms are fixed. It can be enabled by selecting the `RESOURCE_ALLOCATOR_V3` Kconfig option. + +#### Highlights + +* Contains two phases - resource computation phase and resource allocation phase. +* Finds a single window for resource allocation towards the top of addressable memory under 4G boundary. + +#### Limitations + +* Finds a single window for resource allocation towards the top of addressable memory under 4G boundary. +* Does not support allocation above 4G boundary. Thus, it might not be able to allocate resources for devices that request large allocations (e.g. USB4, discrete graphics, etc.). + + +### Resource Allocator v4 + +This is the latest resource allocator that uses multiple ranges for allocating resources. Unlike resource allocator v3, it does not use the topmost available window for allocation. Instead, it uses the first available window within the address space that is available and satisfies the resource request. This allows utilization of the entire available address space and also allows allocation above the 4G boundary. + +#### Highlights + +* Contains two phases - resource computation phase and resource allocation phase. +* In phase 1, the allocator walks in a DFS fashion gathering the requirements from leaf devices and propagates them back up to their upstream bridges until the requirements for all the downstream devices of the domain are gathered. +* Every domain is considered to have a fixed set of resources. These ranges cannot be relaxed based on the requirements of the downstream devices. They represent the available windows from which resources can be allocated to the different devices under the domain. +* In the second phase, the allocator walks down the tree allocating resources to downstream devices as per the resource requirements gathered in the first phase. +* In order to accomplish best fit for the resources, a list of ranges is maintained by each resource type (IO and MEM). +* Domain does not distinguish between mem and prefmem resources. Thus, the resource allocation at domain level considers mem and prefmem together when finding the best fit based on the biggest resource requirement. +* Allocation at bridge level works the same as at the domain level. One major difference at the bridge level is that it considers prefmem resources separately from mem resources. +* Device and platform drivers can request the allocator to perform allocation for a particular resource above 4G boundary by using the flag `IORESOURCE_ABOVE_4G`. + diff --git a/Documentation/index.md b/Documentation/index.md index a7c4869..ec26b4e 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -188,3 +188,4 @@ * [Utilities](util.md) * [Release notes for past releases](releases/index.md) * [Flashing firmware tutorial](flash_tutorial/index.md) +* [Device Management](device/index.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/43603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I887284b44df2bf871f45c3a93fbef9cfc37e42a0 Gerrit-Change-Number: 43603 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/alderlake: Select USE_CAR_NEM_ENHANCED_V3 for ADL
by Subrata Banik (Code Review) 19 Aug '21

19 Aug '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48345 ) Change subject: soc/intel/alderlake: Select USE_CAR_NEM_ENHANCED_V3 for ADL ...................................................................... soc/intel/alderlake: Select USE_CAR_NEM_ENHANCED_V3 for ADL TEST=Able to build and boot ADLRVP using eNEM mode. Change-Id: I08561c8f50bbc4afe2bcdff4cc50e74d8fa2f68e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/48345/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 7e693cb..df2967c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -22,7 +22,6 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -61,6 +60,7 @@ select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM + select USE_CAR_NEM_ENHANCED_V3 config MAX_CPUS int -- To view, visit https://review.coreboot.org/c/coreboot/+/48345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08561c8f50bbc4afe2bcdff4cc50e74d8fa2f68e Gerrit-Change-Number: 48345 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 19

Change in coreboot[master]: tests: Add lib/fmap-test test case
by Name of user not set (Code Review) 17 Aug '21

17 Aug '21

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48557 ) Change subject: tests: Add lib/fmap-test test case ...................................................................... tests: Add lib/fmap-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I885ea05d509d3b1330de7a18531f310d290c6965 --- A tests/include/lib/fmap/fmap_config.h A tests/include/lib/fmap/fmap_data.h M tests/lib/Makefile.inc A tests/lib/fmap-test.c 4 files changed, 563 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/48557/1 diff --git a/tests/include/lib/fmap/fmap_config.h b/tests/include/lib/fmap/fmap_config.h new file mode 100644 index 0000000..c735330 --- /dev/null +++ b/tests/include/lib/fmap/fmap_config.h @@ -0,0 +1,87 @@ +#ifndef FMAPTOOL_GENERATED_HEADER_H_ +#define FMAPTOOL_GENERATED_HEADER_H_ + +/* + * This file was generated using fmaptool from util/cbfstools using + * src/mainboard/google/octopus/chromeos.fmd + * FMAP_OFFSET was changed to zero for testing purposes. + */ +#define FMAP_OFFSET 0x204000 +#define FMAP_SIZE 0x620 + +#define FMAP_SECTION_FLASH_START 0 +#define FMAP_SECTION_FLASH_SIZE 0x1000000 +#define FMAP_SECTION_WP_RO_START 0 +#define FMAP_SECTION_WP_RO_SIZE 0x400000 +#define FMAP_SECTION_SI_DESC_START 0 +#define FMAP_SECTION_SI_DESC_SIZE 0x1000 +#define FMAP_SECTION_IFWI_START 0x1000 +#define FMAP_SECTION_IFWI_SIZE 0x1ff000 +#define FMAP_SECTION_RO_VPD_START 0x200000 +#define FMAP_SECTION_RO_VPD_SIZE 0x4000 +#define FMAP_SECTION_RO_SECTION_START 0x204000 +#define FMAP_SECTION_RO_SECTION_SIZE 0x1fc000 +#define FMAP_SECTION_FMAP_START 0x204000 +#define FMAP_SECTION_FMAP_SIZE 0x800 +#define FMAP_SECTION_RO_FRID_START 0x204800 +#define FMAP_SECTION_RO_FRID_SIZE 0x40 +#define FMAP_SECTION_RO_FRID_PAD_START 0x204840 +#define FMAP_SECTION_RO_FRID_PAD_SIZE 0x7c0 +#define FMAP_SECTION_COREBOOT_START 0x205000 +#define FMAP_SECTION_COREBOOT_SIZE 0x1f8000 +#define FMAP_SECTION_GBB_START 0x3fd000 +#define FMAP_SECTION_GBB_SIZE 0x3000 +#define FMAP_SECTION_MISC_RW_START 0x400000 +#define FMAP_SECTION_MISC_RW_SIZE 0x30000 +#define FMAP_SECTION_RW_PRESERVE_START 0x400000 +#define FMAP_SECTION_RW_PRESERVE_SIZE 0x21000 +#define FMAP_SECTION_UNIFIED_MRC_CACHE_START 0x400000 +#define FMAP_SECTION_UNIFIED_MRC_CACHE_SIZE 0x21000 +#define FMAP_SECTION_RECOVERY_MRC_CACHE_START 0x400000 +#define FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE 0x10000 +#define FMAP_SECTION_RW_MRC_CACHE_START 0x410000 +#define FMAP_SECTION_RW_MRC_CACHE_SIZE 0x10000 +#define FMAP_SECTION_RW_VAR_MRC_CACHE_START 0x420000 +#define FMAP_SECTION_RW_VAR_MRC_CACHE_SIZE 0x1000 +#define FMAP_SECTION_RW_ELOG_START 0x421000 +#define FMAP_SECTION_RW_ELOG_SIZE 0x3000 +#define FMAP_SECTION_RW_SHARED_START 0x424000 +#define FMAP_SECTION_RW_SHARED_SIZE 0x4000 +#define FMAP_SECTION_SHARED_DATA_START 0x424000 +#define FMAP_SECTION_SHARED_DATA_SIZE 0x2000 +#define FMAP_SECTION_VBLOCK_DEV_START 0x426000 +#define FMAP_SECTION_VBLOCK_DEV_SIZE 0x2000 +#define FMAP_SECTION_RW_VPD_START 0x428000 +#define FMAP_SECTION_RW_VPD_SIZE 0x2000 +#define FMAP_SECTION_RW_NVRAM_START 0x42a000 +#define FMAP_SECTION_RW_NVRAM_SIZE 0x5000 +#define FMAP_SECTION_FPF_STATUS_START 0x42f000 +#define FMAP_SECTION_FPF_STATUS_SIZE 0x1000 +#define FMAP_SECTION_RW_SECTION_A_START 0x430000 +#define FMAP_SECTION_RW_SECTION_A_SIZE 0x480000 +#define FMAP_SECTION_VBLOCK_A_START 0x430000 +#define FMAP_SECTION_VBLOCK_A_SIZE 0x10000 +#define FMAP_SECTION_FW_MAIN_A_START 0x440000 +#define FMAP_SECTION_FW_MAIN_A_SIZE 0x46ffc0 +#define FMAP_SECTION_RW_FWID_A_START 0x8affc0 +#define FMAP_SECTION_RW_FWID_A_SIZE 0x40 +#define FMAP_SECTION_RW_SECTION_B_START 0x8b0000 +#define FMAP_SECTION_RW_SECTION_B_SIZE 0x480000 +#define FMAP_SECTION_VBLOCK_B_START 0x8b0000 +#define FMAP_SECTION_VBLOCK_B_SIZE 0x10000 +#define FMAP_SECTION_FW_MAIN_B_START 0x8c0000 +#define FMAP_SECTION_FW_MAIN_B_SIZE 0x46ffc0 +#define FMAP_SECTION_RW_FWID_B_START 0xd2ffc0 +#define FMAP_SECTION_RW_FWID_B_SIZE 0x40 +#define FMAP_SECTION_SMMSTORE_START 0xd30000 +#define FMAP_SECTION_SMMSTORE_SIZE 0x40000 +#define FMAP_SECTION_RW_LEGACY_START 0xd70000 +#define FMAP_SECTION_RW_LEGACY_SIZE 0x1c0000 +#define FMAP_SECTION_BIOS_UNUSABLE_START 0xf30000 +#define FMAP_SECTION_BIOS_UNUSABLE_SIZE 0x4f000 +#define FMAP_SECTION_DEVICE_EXTENSION_START 0xf7f000 +#define FMAP_SECTION_DEVICE_EXTENSION_SIZE 0x80000 +//#define FMAP_SECTION_UNUSED_HOLE_START 0xfff000 +#define FMAP_SECTION_UNUSED_HOLE_SIZE 0x1000 + +#endif diff --git a/tests/include/lib/fmap/fmap_data.h b/tests/include/lib/fmap/fmap_data.h new file mode 100644 index 0000000..343feef --- /dev/null +++ b/tests/include/lib/fmap/fmap_data.h @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef TESTS_INCLUDE_LIB_FMAP_FMAP_DATA_H_ +#define TESTS_INCLUDE_LIB_FMAP_FMAP_DATA_H_ + +/* + * This file was converted using `xxd -i` from binary output of + * fmaptool from util/cbfstools. Data is based on output generated by + * mentioned tool using src/mainboard/google/octopus/chromeos.fmd file. + */ + +unsigned char tests_fmap_bin[] = { +0x5f, 0x5f, 0x46, 0x4d, 0x41, 0x50, 0x5f, 0x5f, 0x01, 0x01, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x46, 0x4c, +0x41, 0x53, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x40, 0x00, 0x57, 0x50, 0x5f, 0x52, 0x4f, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x53, 0x49, +0x5f, 0x44, 0x45, 0x53, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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cbmem_console-romstage-test tests-y += cbmem_console-ramstage-test tests-y += list-test +tests-y += fmap-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -44,3 +45,10 @@ list-test-srcs += tests/lib/list-test.c list-test-srcs += src/lib/list.c +fmap-test-srcs += tests/lib/fmap-test.c +fmap-test-srcs += src/lib/fmap.c +fmap-test-srcs += tests/stubs/console.c +fmap-test-srcs += src/lib/boot_device.c +fmap-test-srcs += src/commonlib/region.c +fmap-test-cflags += -I tests/include/lib/fmap +fmap-test-cflags += -I 3rdparty/vboot/firmware/include diff --git a/tests/lib/fmap-test.c b/tests/lib/fmap-test.c new file mode 100644 index 0000000..2b7605d --- /dev/null +++ b/tests/lib/fmap-test.c @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <string.h> + +#include <fmap.h> +#include <commonlib/region.h> + +#include <tests/test.h> + +#include <lib/fmap/fmap_data.h> +#include <lib/fmap/fmap_config.h> + +static struct region_device *rdev_root = NULL; +static char *flash_buffer = NULL; +static size_t flash_buffer_size = 0; + +static void *local_mmap(const struct region_device *rdev, size_t offset, size_t size) +{ + if (offset >= FMAP_SECTION_FLASH_START + && offset < FMAP_SECTION_FLASH_START + FMAP_SECTION_FLASH_SIZE) + return flash_buffer + offset; + + return NULL; +} + +static int local_unmap(const struct region_device *rdev, void *mapping) +{ + return 0; +} + +static ssize_t local_readat(const struct region_device *rdev, void *buffer, + size_t offset, size_t size) +{ + if (size + offset >= flash_buffer_size) + return -1; + + size = MIN(size, flash_buffer_size - offset); + + memcpy(buffer, flash_buffer + offset, size); + + return size; +} + +static ssize_t local_writeat(const struct region_device *rdev, const void *buffer, + size_t offset, size_t size) +{ + if (size + offset >= flash_buffer_size) + return -1; + + size = MIN(size, flash_buffer_size - offset); + + memcpy(flash_buffer + offset, buffer, size); + + return size; +} + +static ssize_t local_eraseat(const struct region_device *rdev, + size_t offset, size_t size) +{ + if (size + offset >= flash_buffer_size) + return -1; + + size = MIN(size, flash_buffer_size - offset); + + memset(flash_buffer + offset, 0, size); + + return size; +} + +static int setup_fmap_region_device(void **state) +{ + // Setup callbacks + struct region_device_ops *rdev_ops = malloc(sizeof(*rdev_ops)); + rdev_ops->mmap = local_mmap; + rdev_ops->munmap = local_unmap; + rdev_ops->readat = local_readat; + rdev_ops->writeat = local_writeat; + rdev_ops->eraseat = local_eraseat; + + // Prepare root region device + struct region_device rdev_new_root = REGION_DEV_INIT(rdev_ops, + FMAP_SECTION_FLASH_START, FMAP_SECTION_FLASH_SIZE); + rdev_root = malloc(sizeof(rdev_new_root)); + memcpy(rdev_root, &rdev_new_root, sizeof(rdev_new_root)); + + // Prepare fmap region device + struct region_device rdev_fmap = REGION_DEV_INIT(rdev_ops, + FMAP_SECTION_FMAP_START, FMAP_SECTION_FMAP_SIZE); + rdev_fmap.root = rdev_root; + + // Pass fmap region device to tests as state + *state = malloc(sizeof(rdev_fmap)); + memcpy(*state, &rdev_fmap, sizeof(rdev_fmap)); + + // Prepare flash buffer with dummy data and FMAP + flash_buffer = malloc(FMAP_SECTION_FLASH_SIZE); + flash_buffer_size = FMAP_SECTION_FLASH_SIZE; + memset(flash_buffer, 0, FMAP_SECTION_FLASH_SIZE); + for (int i = 0; i < FMAP_SECTION_FMAP_START; ++i) + flash_buffer[i] = 'a' + i % ('z' - 'a'); + memcpy(flash_buffer + FMAP_SECTION_FMAP_START, tests_fmap_bin, FMAP_SIZE); + for (int i = FMAP_SECTION_FMAP_START + FMAP_SECTION_FMAP_SIZE; + i < FMAP_SECTION_FLASH_SIZE; ++i) + flash_buffer[i] = 'a' + i % ('z' - 'a'); + + return 0; +} + +static int teardown_fmap_region_device(void **state) +{ + struct region_device *rdev_fmap = *state; + + free((void *)rdev_fmap->ops); + free(rdev_fmap); + + free(rdev_root); + rdev_root = NULL; + + free(flash_buffer); + flash_buffer = NULL; + flash_buffer_size = 0; + + return 0; +} + +void boot_device_init(void) +{ + // Setup in unit test setup function +} + +const struct region_device *boot_device_ro(void) +{ + return rdev_root; +} + +const struct region_device *boot_device_rw(void) +{ + return rdev_root; +} + +static void test_fmap_locate_area_as_rdev(void **state) +{ + struct region_device *rdev = *state; + + assert_int_not_equal(-1, fmap_locate_area_as_rdev("RO_VPD", rdev)); + + // Check if locating area second time works + assert_int_not_equal(-1, fmap_locate_area_as_rdev("RO_VPD", rdev)); + + assert_int_not_equal(-1, fmap_locate_area_as_rdev("RECOVERY_MRC_CACHE", rdev)); + + // Expect error when looking for non-existent area + assert_int_equal(-1, fmap_locate_area_as_rdev("NONEXISTENT_AREA", rdev)); + + assert_int_equal(-1, fmap_locate_area_as_rdev("", rdev)); + + // Expect error when passing invalid references + assert_int_equal(-1, fmap_locate_area_as_rdev(NULL, rdev)); + assert_int_equal(-1, fmap_locate_area_as_rdev("RW_SECTION_A", NULL)); +} + + +static void test_fmap_locate_area_as_rdev_rw(void **state) +{ + struct region_device *rdev = *state; + + assert_int_not_equal(-1, fmap_locate_area_as_rdev_rw("RW_SECTION_A", rdev)); + + // Check if locating area second time works + assert_int_not_equal(-1, fmap_locate_area_as_rdev_rw("RW_SECTION_A", rdev)); + + assert_int_not_equal(-1, fmap_locate_area_as_rdev_rw("MISC_RW", rdev)); + + // Expect error when looking for non-existent area + assert_int_equal(-1, fmap_locate_area_as_rdev_rw("NONEXISTENT_AREA", rdev)); + assert_int_equal(-1, fmap_locate_area_as_rdev_rw("", rdev)); + + // Expect error when passing invalid references + assert_int_equal(-1, fmap_locate_area_as_rdev_rw(NULL, rdev)); + assert_int_equal(-1, fmap_locate_area_as_rdev_rw("RW_SECTION_A", NULL)); +} + +static void test_fmap_locate_area(void **state) +{ + (void)state; + struct region ar; + + assert_int_not_equal(-1, fmap_locate_area("COREBOOT", &ar)); + + // Check if locating area second time works + assert_int_not_equal(-1, fmap_locate_area("COREBOOT", &ar)); + + assert_int_not_equal(-1, fmap_locate_area("GBB", &ar)); + + // Expect error when looking for non-existent area + assert_int_equal(-1, fmap_locate_area("NONEXISTENT_AREA", &ar)); + assert_int_equal(-1, fmap_locate_area("", &ar)); + + // Expect error when passing invalid references + assert_int_equal(-1, fmap_locate_area(NULL, &ar)); + assert_int_equal(-1, fmap_locate_area("SHARED_DATA", NULL)); +} + +static void test_fmap_find_region_name(void **state) +{ + (void)state; + struct region ar; + char found_area_name[FMAP_STRLEN] = ""; + const char *area_name = "RW_PRESERVE"; + + // Find area by name + assert_int_not_equal(-1, fmap_locate_area(area_name, &ar)); + + // Find name by previously find area + assert_int_not_equal(-1, fmap_find_region_name(&ar, found_area_name)); + assert_string_equal(area_name, found_area_name); + + // Expect error when passing invalid buffer + assert_int_equal(-1, fmap_find_region_name(&ar, NULL)); + + // Try to find non-existent area + ar.offset = 2142037; + ar.size = 636; + assert_int_equal(-1, fmap_find_region_name(&ar, found_area_name)); + + // Expect error when passing invalid region pointer + assert_int_equal(-1, fmap_find_region_name(NULL, found_area_name)); +} + +static void test_fmap_read_area(void **state) +{ + (void)state; + struct region ar; + char *buffer = malloc(FMAP_SECTION_RW_SECTION_A_SIZE); + + fmap_locate_area("RW_SECTION_A", &ar); + assert_int_equal(FMAP_SECTION_RW_SECTION_A_SIZE, + fmap_read_area("RW_SECTION_A", buffer, FMAP_SECTION_RW_SECTION_A_SIZE)); + assert_memory_equal(flash_buffer + FMAP_SECTION_RW_SECTION_A_START, buffer, + FMAP_SECTION_RW_SECTION_A_SIZE); + + assert_int_equal(-1, + fmap_read_area("NONEXISTENT_SECTION", + buffer, + FMAP_SECTION_RW_SECTION_A_SIZE)); + + assert_int_equal(-1, fmap_read_area(NULL, buffer, FMAP_SECTION_RW_SECTION_A_SIZE)); + assert_int_equal(-1, + fmap_read_area("RW_SECTION_A", NULL, FMAP_SECTION_RW_SECTION_A_SIZE)); + + free(buffer); +} + +static void test_fmap_overwrite_area(void **state) +{ + (void)state; + struct region ar; + char *buffer1 = malloc(FMAP_SECTION_FW_MAIN_A_SIZE); + char *buffer2 = malloc(FMAP_SECTION_FW_MAIN_A_SIZE); + char *new_data = malloc(FMAP_SECTION_FW_MAIN_A_SIZE); + + fmap_locate_area("FW_MAIN_A", &ar); + assert_int_equal(FMAP_SECTION_FW_MAIN_A_SIZE, + fmap_read_area("FW_MAIN_A", buffer1, FMAP_SECTION_FW_MAIN_A_SIZE)); + + memset(new_data, 0x42, FMAP_SECTION_FW_MAIN_A_SIZE); + assert_int_equal(FMAP_SECTION_FW_MAIN_A_SIZE, + fmap_overwrite_area("FW_MAIN_A", + new_data, + FMAP_SECTION_FW_MAIN_A_SIZE)); + + assert_int_equal(FMAP_SECTION_FW_MAIN_A_SIZE, + fmap_read_area("FW_MAIN_A", buffer2, FMAP_SECTION_FW_MAIN_A_SIZE)); + + assert_memory_not_equal(buffer1, buffer2, FMAP_SECTION_FW_MAIN_A_SIZE); + assert_memory_equal(buffer2, new_data, FMAP_SECTION_FW_MAIN_A_SIZE); + + assert_int_equal(-1, + fmap_overwrite_area("NONEXISTENT_SECTION", + new_data, + FMAP_SECTION_FW_MAIN_A_SIZE)); + + assert_int_equal(-1, + fmap_overwrite_area(NULL, new_data, FMAP_SECTION_FW_MAIN_A_SIZE)); + + assert_int_equal(-1, + fmap_overwrite_area("FW_MAIN_A", NULL, FMAP_SECTION_FW_MAIN_A_SIZE)); + + + free(buffer1); + free(buffer2); + free(new_data); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup_teardown(test_fmap_locate_area_as_rdev, + setup_fmap_region_device, + teardown_fmap_region_device), + cmocka_unit_test_setup_teardown(test_fmap_locate_area_as_rdev_rw, + setup_fmap_region_device, + teardown_fmap_region_device), + cmocka_unit_test_setup_teardown(test_fmap_locate_area, + setup_fmap_region_device, + teardown_fmap_region_device), + cmocka_unit_test_setup_teardown(test_fmap_find_region_name, + setup_fmap_region_device, + teardown_fmap_region_device), + cmocka_unit_test_setup_teardown(test_fmap_read_area, + setup_fmap_region_device, + teardown_fmap_region_device), + cmocka_unit_test_setup_teardown(test_fmap_overwrite_area, + setup_fmap_region_device, + teardown_fmap_region_device), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/48557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I885ea05d509d3b1330de7a18531f310d290c6965 Gerrit-Change-Number: 48557 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: [WIP] util/inteltool: add opt to override cores number
by Maxim Polyakov (Code Review) 17 Aug '21

17 Aug '21

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35919 ) Change subject: [WIP] util/inteltool: add opt to override cores number ...................................................................... [WIP] util/inteltool: add opt to override cores number In some cases, it is necessary to increase (if the server contains several processors) or decrease (dump should be more compact) the number of CPU cores for dump MSRs. Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/cpu.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h 3 files changed, 15 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35919/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index f100851..9ae46c9 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -219,7 +219,7 @@ return error; } -int print_intel_core_msrs(void) +int print_intel_core_msrs(unsigned int cores_num) { unsigned int i, core, id; msr_t msr; @@ -2256,8 +2256,10 @@ close(fd_msr); - unsigned int max_core_limit = cpu->max_core_limit ? 8 : cpu->max_core_limit; - for (core = 0; core < max_core_limit; core++) { + if (!cores_num) + cores_num = cpu->max_core_limit; + + for (core = 0; core < cores_num; core++) { #ifndef __DARWIN__ char msrfilename[64]; memset(msrfilename, 0, 64); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index db80bd2..bc9af2b 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -476,7 +476,7 @@ static void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMaAsfSRx]\n", name); + printf("usage: %s [-vh?gGrpmedPMcaAsfSRx]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -493,6 +493,7 @@ " -d | --dmibar: dump northbridge DMIBAR registers\n" " -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n" " -M | --msrs: dump CPU MSRs\n" + " -c <num> | --cores <num>: override CPU cores number for MSR dump\n\n" " -A | --ambs: dump AMB registers\n" " -x | --sgx: dump SGX status\n" " -a | --all: dump all known (safe) registers\n" @@ -508,6 +509,7 @@ struct pci_dev *sb = NULL, *nb, *gfx = NULL, *ahci = NULL, *dev; const char *dump_spd_file = NULL; int opt, option_index = 0; + unsigned int cores = 0; unsigned int id, i; char *sbname = "unknown", *nbname = "unknown", *gfxname = "unknown"; @@ -532,6 +534,7 @@ {"dmibar", 0, 0, 'd'}, {"pciexpress", 0, 0, 'P'}, {"msrs", 0, 0, 'M'}, + {"cores", required_argument, 0, 'c'}, {"ambs", 0, 0, 'A'}, {"spi", 0, 0, 's'}, {"spd", 0, 0, 'S'}, @@ -543,7 +546,7 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRS:x", + while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMc:aAsfRS:x", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -587,6 +590,9 @@ case 'M': dump_coremsrs = 1; break; + case 'c': + cores = strtoul(optarg, NULL, 0); + break; case 'a': dump_gpios = 1; show_gpio_diffs = 1; @@ -813,7 +819,7 @@ } if (dump_coremsrs) { - print_intel_core_msrs(); + print_intel_core_msrs(cores); printf("\n\n"); } diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..7708d70 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -385,7 +385,7 @@ void unmap_physical(void *virt_addr, size_t len); unsigned int cpuid(unsigned int op); -int print_intel_core_msrs(void); +int print_intel_core_msrs(unsigned int cores_num); int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file); int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); -- To view, visit https://review.coreboot.org/c/coreboot/+/35919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105 Gerrit-Change-Number: 35919 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

4 29

Change in coreboot[master]: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig
by Subrata Banik (Code Review) 16 Aug '21

16 Aug '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48344 ) Change subject: soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig ...................................................................... soc/intel/common/block/cpu: Introduce USE_CAR_NEM_ENHANCED_V3 Kconfig List of changes: 1. Default select USE_CAR_NEM_ENHANCED_V1 to use the existing algorithm 2. Select COS_MAPPED_TO_MSB 3. Add new MSR 0xc85 IA32_YMM 4. a. Update eNEM init flow: - Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = 0xFFFFF - (2^(non-eviction mask)-1) - Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(non-eviction mask)-1) - Set MSR 0xC85 L3_Protected_ways = (2^(no. of ways)-1) b. Update eNEM teardown flow: - Set MSR 0xC85 L3_Protected_ways = 0x00000 This new eNEM flow can be used for ADL SoC. Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/cpu/x86/msr.h M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/common/block/cpu/car/exit_car.S 4 files changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/48344/1 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 5ae3ddf..1b089c0 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -85,6 +85,7 @@ #define IA32_HWP_CAPABILITIES 0x771 #define IA32_HWP_REQUEST 0x774 #define IA32_HWP_STATUS 0x777 +#define IA32_YMM 0xc85 #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ #define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9023b58..7af664d 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -66,6 +66,14 @@ This config supports INTEL_CAR_NEM_ENHANCED mode on TGL platform. +config USE_CAR_NEM_ENHANCED_V3 + bool + select USE_CAR_NEM_ENHANCED_V1 + select COS_MAPPED_TO_MSB + help + This config supports INTEL_CAR_NEM_ENHANCED mode on + ADL platform. + config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 167342f..371ac73 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -413,7 +413,11 @@ set_eviction_mask: mov %ebx, %ecx /* back up the number of ways */ - mov %eax, %ebx /* back up the non-eviction mask*/ + mov %eax, %ebx /* back up the non-eviction mask */ +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + movd %ecx, %mm3 /* Store the number of ways in mm3 for later use */ + movd %ebx, %mm4 /* Store the non-eviction mask in mm4 for later use */ +#endif /* * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 * This MSR contain one bit per each way of LLC @@ -450,6 +454,37 @@ #endif xorl %edx, %edx wrmsr + +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + /* Set MSR 0x1891 IA32_CR_SF_QOS_MASK_1 = 0xFFFFF - (2^(non-eviction mask) - 1) */ + movd %mm4, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + mov %eax, %ebx + mov $0xFFFFF, %eax + subl %ebx, %eax + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_1, %ecx + wrmsr + + /* Set MSR 0x1892 IA32_CR_SF_QOS_MASK_2 = (2^(non-eviction mask) - 1) */ + movd %mm4, %ecx + movl $0x01, %eax + shl %cl, %eax + subl $0x01, %eax + xorl %edx, %edx + mov $IA32_CR_SF_QOS_MASK_2, %ecx + wrmsr + + /* Set MSR 0xC85 L3_Protected_ways = (2^(no. of ways) - 1) */ + movd %mm3, %ecx + shl %cl, %eax + subl $0x01, %eax + xorl %edx, %edx + mov $IA32_YMM, %ecx + wrmsr +#endif /* * Set IA32_PQR_ASSOC * diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S index 191232a..568a502 100644 --- a/src/soc/intel/common/block/cpu/car/exit_car.S +++ b/src/soc/intel/common/block/cpu/car/exit_car.S @@ -96,6 +96,13 @@ rdmsr and $~IA32_PQR_ASSOC_MASK, %edx wrmsr +#if CONFIG(USE_CAR_NEM_ENHANCED_V3) + /* Set MSR 0xC85 L3_Protected_ways = 0x00000 */ + mov $IA32_YMM, %ecx + mov $0x00000, %eax + xorl %edx, %edx + wrmsr +#endif #endif /* Return to caller. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/48344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb5a9ec74c50bda371c30e13aeadbb4326887fd6 Gerrit-Change-Number: 48344 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

6 46

Change in coreboot[master]: nb/intel/haswell/gma.c: Add ULX PCI device IDs
by Felix Held (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50137 ) Change subject: nb/intel/haswell/gma.c: Add ULX PCI device IDs ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: there are probably even more iGPU PCI IDs in that CPU generation; look for Haswell in here https://dgpu-docs.intel.com/devices/hardware-table.html -- To view, visit https://review.coreboot.org/c/coreboot/+/50137 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida3d2dcdf89342b084c8e1fbf3fae7e47a7238d2 Gerrit-Change-Number: 50137 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jamal Wright <Crabstorage(a)getbackinthe.kitchen> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 31 Jul 2021 23:56:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/broadwell: Drop unused function declarations
by Felix Held (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Nico Huber, Matt DeVillier, Angel Pons, Arthur Heymans, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55798 ) Change subject: soc/intel/broadwell: Drop unused function declarations ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4204265680d06bf83fc42f061fd7270ff8e3305e Gerrit-Change-Number: 55798 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 31 Jul 2021 23:35:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/broadwell/pch/pch.c: Drop unused include
by Felix Held (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Nico Huber, Matt DeVillier, Angel Pons, Arthur Heymans, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55583 ) Change subject: soc/intel/broadwell/pch/pch.c: Drop unused include ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5564e06b797d787f0d1093bd9bd572d1ee7b2d54 Gerrit-Change-Number: 55583 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 31 Jul 2021 23:34:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/broadwell: Rename `ramstage.h`
by Felix Held (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Nico Huber, Matt DeVillier, Angel Pons, Arthur Heymans, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55582 ) Change subject: soc/intel/broadwell: Rename `ramstage.h` ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6513f45b8914a84312b27ef4860870a89fd0aab3 Gerrit-Change-Number: 55582 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 31 Jul 2021 23:34:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/broadwell: Drop unused PCI device macros
by Felix Held (Code Review) 31 Jul '21

31 Jul '21

Attention is currently required from: Nico Huber, Matt DeVillier, Angel Pons, Arthur Heymans, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55529 ) Change subject: soc/intel/broadwell: Drop unused PCI device macros ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: i'd still keep those for completeness -- To view, visit https://review.coreboot.org/c/coreboot/+/55529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I366e064f3fe708b55fb381aee25b2795b1c61142 Gerrit-Change-Number: 55529 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 31 Jul 2021 23:33:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit July 2021