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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56718 )
Change subject: util/kconfig: Provide default for DEFCONFIG
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56718/comment/2074d2de_049f46bd
PS1, Line 12:
It’d be great if you added a Fixes: tag.
Patchset:
PS1:
One error, fixed by this change-set, is:
$ make savedefconfig
cp: missing destination file operand after '/dev/shm/coreboot/.config'
Try 'cp --help' for more information.
Thank you for fixing this.
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Change subject: util/lint/lint-stable: Add forbidden Kconfig check
......................................................................
Patch Set 2:
(1 comment)
File util/lint/lint-stable-028-forbidden-config-c:
https://review.coreboot.org/c/coreboot/+/56593/comment/10627e2e_33b0b1bf
PS2, Line 10: INCLUDED_FILES='\.[chsS]$\|\.asl$\|\.cb$\|\.ld$\|\.inc$'
> Also .adb, . […]
Oh, I forget the syntax would be different. We'd have to grep for
`Config.CBFS_SIZE` for instance.
Also what about boolean configs? i.e. shouldn't we grep for
`CONFIG(SYMBOL)` too?
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Change subject: util/lint/lint-stable: Add forbidden Kconfig check
......................................................................
Patch Set 2:
(2 comments)
File util/lint/lint-stable-028-forbidden-config-c:
https://review.coreboot.org/c/coreboot/+/56593/comment/ecfda79f_174263a4
PS2, Line 10: INCLUDED_FILES='\.[chsS]$\|\.asl$\|\.cb$\|\.ld$\|\.inc$'
Also .adb, .ads ;)
https://review.coreboot.org/c/coreboot/+/56593/comment/a03d65ab_7af7d333
PS2, Line 23: -I %
Not sure why you'd want to use that. At least on a GNU system, it makes
xargs invoke grep for each line of input. Without this, it's ~200 times
faster.
Another 2 times faster is using `git grep` directly e.g. with a command
line like this:
$ git grep -l CONFIG_CBFS_SIZE -- 'src/*.[chsS]' 'util/*.[chsS]' # etc.
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Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56718 )
Change subject: util/kconfig: Provide default for DEFCONFIG
......................................................................
util/kconfig: Provide default for DEFCONFIG
Our documentation claims that the DEFCONFIG make variable, used for
targets such as savedefconfig, defaults to 'defconfig'.
With the update to kconfig 5.13 we lost this default, so bring it back.
Change-Id: Idb88b69ffa855fa97df8c821601308e717575550
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
---
M util/kconfig/Makefile.inc
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/56718/1
diff --git a/util/kconfig/Makefile.inc b/util/kconfig/Makefile.inc
index bedb41d..c3b764b 100644
--- a/util/kconfig/Makefile.inc
+++ b/util/kconfig/Makefile.inc
@@ -6,6 +6,8 @@
export LC_ALL=C
export LANG=C
+DEFCONFIG ?= defconfig
+
# Include original Makefile, with just enough edits to work for us
$(objk)/Makefile.real: $(dir $(lastword $(MAKEFILE_LIST)))Makefile
mkdir -p $(objk)
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Change subject: soc/intel/common: Calculate and configure SF Mask 1
......................................................................
Patch Set 17:
(4 comments)
File src/soc/intel/common/block/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/51374/comment/d168b6fb_af5d8dab
PS16, Line 70: User to select this
> Not really for the user is it? It should be selected by the SoCs that require it.
Ack
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/51374/comment/af6aee81_831b352b
PS16, Line 512: dataway
> data_ways
Ack
https://review.coreboot.org/c/coreboot/+/51374/comment/312495c8_b2ea7740
PS16, Line 523: dataway
> data_ways
Ack
https://review.coreboot.org/c/coreboot/+/51374/comment/12db7395_922c57ba
PS16, Line 531: mov %ebx, %eax /* restore dataway in eax */
: movl $0x02, %ecx
: div %ecx
> WDYT about `shr` instead of `div`: […]
Done
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Change subject: soc/intel/common: Calculate and configure SF Mask 2
......................................................................
soc/intel/common: Calculate and configure SF Mask 2
As per TGL EDS, two ways will be controlled with one bit of SF QoS
register hence, this patch introduces SF_MASK_2BITS_PER_WAY Kconfig to
allow SoC users to select SF_MASK_2BITS_PER_WAY to follow the EDS
recommendation.
Calculate SF masks:
1. if CONFIG_SF_MASK_2BITS_PER_WAY:
a. data_ways = data_ways / 2
Also, program SF Mask#2 using below logic:
2. Set SF_MASK_2 = (1 << data_ways) - 1
Change-Id: I442bed75f13d26f357cfb32c54c5fe9efa4b474b
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/include/cpu/x86/msr.h
M src/soc/intel/common/block/cpu/Kconfig
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
3 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/56717/1
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 26f1dcb..9e7e6fd 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -88,6 +88,8 @@
#define IA32_HWP_CAPABILITIES 0x771
#define IA32_HWP_REQUEST 0x774
#define IA32_HWP_STATUS 0x777
+#define IA32_SF_QOS_INFO 0xc87
+#define IA32_SF_WAY_COUNT_MASK 0x3f
#define IA32_PQR_ASSOC 0xc8f
/* MSR bits 33:32 encode slot number 0-3 */
#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1)
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 16844d9..77e8429 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -63,6 +63,14 @@
IA32_L3_SF_MASK_x programming is required along with the data ways.
This is applicable for TGL and beyond.
+config SF_MASK_2BITS_PER_WAY
+ bool
+ depends on INTEL_CAR_NEM_ENHANCED
+ help
+ In the case of non-inclusive cache architecture when two ways in
+ the SF mask is used to control with one bit of SF QoS register.
+ This is applicable for TGL alone.
+
config COS_MAPPED_TO_MSB
bool
depends on INTEL_CAR_NEM_ENHANCED
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 5f39507..c0814fd 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -508,6 +508,9 @@
*/
mov $CONFIG_DCACHE_RAM_SIZE, %eax
div %ecx
+#if CONFIG(SF_MASK_2BITS_PER_WAY)
+ mov %eax, %edx /* back up data_ways in edx */
+#endif
mov %eax, %ecx
movl $0x01, %eax
shl %cl, %eax
@@ -516,8 +519,30 @@
set_eviction_mask:
mov %ebx, %edi /* back up number of ways */
mov %eax, %esi /* back up the non-eviction mask */
+#if CONFIG(SF_MASK_2BITS_PER_WAY)
+ mov %edx, %ebx /* back up data_ways in ebx */
+#endif
#if CONFIG(CAR_HAS_SF_MASKS)
/*
+ * Program MSR 0x1892 Non-Eviction Mask #2
+ * IA32_CR_SF_QOS_MASK_2 = ((1 << data_ways) - 1)
+ */
+#if CONFIG(SF_MASK_2BITS_PER_WAY)
+ movl $0x01, %ecx
+ shr %cl, %ebx
+ mov %ebx, %ecx
+ movl $0x01, %ebx
+ shl %cl, %ebx
+ subl $0x01, %ebx
+#else
+ mov %esi, %ebx
+#endif
+ mov %ebx, %eax /* restore data_ways in eax */
+ xorl %edx, %edx
+ mov $IA32_CR_SF_QOS_MASK_2, %ecx
+ wrmsr
+
+ /*
* SF mask is programmed with the double number of bits than
* the number of ways
*/
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#17).
Change subject: soc/intel/common: Calculate and configure SF Mask 1
......................................................................
soc/intel/common: Calculate and configure SF Mask 1
MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is used
to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87 indicates
the maximum number of bits that may be set in any of the SF MASK
register. Hence, this patch calculates SF way count using below logic:
Calculate SFWayCnt = (MSR 0xC87) & 0x3f
Calculate SF masks:
1. if CONFIG_SF_MASK_2BITS_PER_WAY:
a. SFWayCnt = SFWayCnt / 2
2. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - SF_MASK_2
Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 18 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/51374/17
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Change subject: mb/google/dedede/var/magolor: Modify SSFC for camera and touchscreen
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Need to update the ap firmware to support the 8M camera.
But the incorrect ssfc value has been shipped of Magolor/Maglia.
If the Cl can not be merged, the touch screen function will have no function.
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Change subject: mb/google/dedede/var/cappy2: Disable external bypass VR
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56687/comment/18ddcd79_ce1d505c
PS4, Line 9: anpec apw8738bqbi
> In what commit/change-set, was that removed?
Hi paul,about removing anpec.We have discussed with google and intel at issue:b/190727416 and the intel has uploaded the CL:55744 for it.Please know it!
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