coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

1 participants
5824 discussions

Change in coreboot[master]: commonlib/region: Add support for asynchronous readat
by Raul Rangel (Code Review) 03 Jul '21

03 Jul '21

Attention is currently required from: Furquan Shaikh, Marshall Dawson, Julius Werner, Angel Pons. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55856 ) Change subject: commonlib/region: Add support for asynchronous readat ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Sorry, I don't think it's a good idea to pull this kind of stuff so deep down into the rdev APIs. […] I have refactored the patch and provided a better explanation of the benefits. -- To view, visit https://review.coreboot.org/c/coreboot/+/55856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9702c9e6abe992ea401fa08ba71e5080c3c29d9a Gerrit-Change-Number: 55856 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Jul 2021 23:21:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/cbfstool: Allow setting alignment for payload
by Raul Rangel (Code Review) 03 Jul '21

03 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55973 ) Change subject: util/cbfstool: Allow setting alignment for payload ...................................................................... util/cbfstool: Allow setting alignment for payload The -a flag was already implemented, it just wasn't exposed for the add-payload command. Setting the alignment of the payload will enable using the SPI DMA controller to read the payload on AMD devices. BUG=b:179699789 TEST=cbfstool foo.bin add-payload -a 64 ... Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55973 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M util/cbfstool/cbfstool.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 48c9387..8fd81fe 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1723,7 +1723,7 @@ {"add", "H:r:f:n:t:c:b:a:p:yvA:j:gh?", cbfs_add, true, true}, {"add-flat-binary", "H:r:f:n:l:e:c:b:p:vA:gh?", cbfs_add_flat_binary, true, true}, - {"add-payload", "H:r:f:n:c:b:C:I:p:vA:gh?", cbfs_add_payload, + {"add-payload", "H:r:f:n:c:b:a:C:I:p:vA:gh?", cbfs_add_payload, true, true}, {"add-stage", "a:H:r:f:n:t:c:b:P:QS:p:yvA:gh?", cbfs_add_stage, true, true}, -- To view, visit https://review.coreboot.org/c/coreboot/+/55973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f4aea5f0cbeaa8e761212041099b37f4718ac39 Gerrit-Change-Number: 55973 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/espi: Fix debug message log level
by Raul Rangel (Code Review) 03 Jul '21

03 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55972 ) Change subject: soc/amd/common/espi: Fix debug message log level ...................................................................... soc/amd/common/espi: Fix debug message log level BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see the message printed. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55972 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index e698c8c..ebc8f45 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -482,7 +482,7 @@ uint32_t status; if (CONFIG(ESPI_DEBUG)) - printk(BIOS_ERR, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", + printk(BIOS_DEBUG, "eSPI cmd0-cmd2: %08x %08x %08x data: %08x.\n", cmd->hdr0.val, cmd->hdr1.val, cmd->hdr2.val, cmd->data.val); if (espi_wait_ready() == -1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/55972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22 Gerrit-Change-Number: 55972 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/intel/fsp2: Change FSPS returned message to INFO
by Raul Rangel (Code Review) 03 Jul '21

03 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55971 ) Change subject: drivers/intel/fsp2: Change FSPS returned message to INFO ...................................................................... drivers/intel/fsp2: Change FSPS returned message to INFO This message is not an error, but just informational. BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see it printed Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce Reviewed-on: https://review.coreboot.org/c/coreboot/+/55971 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index a43cc9d..a00699d 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -126,7 +126,7 @@ else status = silicon_init(upd); - printk(BIOS_ERR, "FSPS returned %x\n", status); + printk(BIOS_INFO, "FSPS returned %x\n", status); timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POST_FSP_SILICON_EXIT); -- To view, visit https://review.coreboot.org/c/coreboot/+/55971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb64edbe029cafa82aec99aa50de47f51cd50dce Gerrit-Change-Number: 55971 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
by Raul Rangel (Code Review) 03 Jul '21

03 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55987 ) Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads ...................................................................... soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads We are currently reading the uCode for each CPU. This is unnecessary since the uCode never changes. BUG=b:177909625 TEST=Boot guybrush and see "microcode: being updated to patch id" for each CPU. I no longer see CBFS access for each CPU. This drops device initialization time by 32 ms. Also boot Ezkinil and verify microcode was also updated. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/soc/amd/common/block/cpu/update_microcode.c 1 file changed, 37 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/update_microcode.c b/src/soc/amd/common/block/cpu/update_microcode.c index 2ba1802..2822d2f 100644 --- a/src/soc/amd/common/block/cpu/update_microcode.c +++ b/src/soc/amd/common/block/cpu/update_microcode.c @@ -34,6 +34,8 @@ uint8_t m_patch_data[MPB_MAX_SIZE-MPB_DATA_OFFSET]; } __packed; +_Static_assert(sizeof(struct microcode) == MPB_MAX_SIZE, "microcode size is invalid"); + static void apply_microcode_patch(const struct microcode *m) { uint32_t new_patch_id; @@ -65,29 +67,51 @@ return (uint16_t)((cpuid_family & 0xff0000) >> 8 | (cpuid_family & 0xff)); } -static void amd_update_microcode(const void *ucode, size_t ucode_len, - uint16_t equivalent_processor_rev_id) +static const struct microcode *find_microcode(const struct microcode *ucode, size_t ucode_len) { + uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id(); const struct microcode *m; - for (m = (struct microcode *)ucode; - m < (struct microcode *)ucode + ucode_len/MPB_MAX_SIZE; m++) { + for (m = ucode; m < ucode + ucode_len / MPB_MAX_SIZE; m++) { if (m->processor_rev_id == equivalent_processor_rev_id) - apply_microcode_patch(m); + return m; } + + printk(BIOS_WARNING, "Failed to find microcode for processor rev: %hx.\n", + equivalent_processor_rev_id); + + return NULL; } void amd_update_microcode_from_cbfs(void) { - const void *ucode; - size_t ucode_len; - uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id(); + static struct microcode ucode_cache; + static bool cache_valid; - ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len); - if (!ucode) { - printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n"); - return; + struct microcode *ucode_list; + const struct microcode *matching_ucode; + size_t ucode_len; + + /* Cache the buffer so each CPU doesn't need to read the uCode from flash */ + if (!cache_valid) { + ucode_list = cbfs_map("cpu_microcode_blob.bin", &ucode_len); + if (!ucode_list) { + printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n"); + return; + } + + matching_ucode = find_microcode(ucode_list, ucode_len); + + if (!matching_ucode) { + cbfs_unmap(ucode_list); + return; + } + + ucode_cache = *matching_ucode; + cache_valid = true; + + cbfs_unmap(ucode_list); } - amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id); + apply_microcode_patch(&ucode_cache); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 Gerrit-Change-Number: 55987 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/cezanne: Enable SPI DMA support
by Raul Rangel (Code Review) 03 Jul '21

03 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55855 ) Change subject: soc/amd/cezanne: Enable SPI DMA support ...................................................................... soc/amd/cezanne: Enable SPI DMA support Start using the custom boot device. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I4ae7272677f563e8827ba154fe5177c8c01155c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55855 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/cezanne/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 7dd3447..1bb9353 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -48,6 +48,7 @@ select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_I2C select SOC_AMD_COMMON_BLOCK_LPC + select SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF -- To view, visit https://review.coreboot.org/c/coreboot/+/55855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ae7272677f563e8827ba154fe5177c8c01155c0 Gerrit-Change-Number: 55855 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/block/lpc: Add custom SPI DMA boot device
by Raul Rangel (Code Review) 03 Jul '21

03 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55854 ) Change subject: soc/amd/common/block/lpc: Add custom SPI DMA boot device ...................................................................... soc/amd/common/block/lpc: Add custom SPI DMA boot device This is a copy of mmap_boot.c and mem_rdev_ro_ops. I split it up so it was easier to review. The next patches will add support for the SPI DMA controller. This will provide a minor speed up vs using mmap reads. It will also provide the facilities to perform asynchronous SPI loading. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Id26e2a69601d0f31e256d0010008904a447c8e21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55854 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/block/lpc/Kconfig M src/soc/amd/common/block/lpc/Makefile.inc A src/soc/amd/common/block/lpc/spi_dma.c 3 files changed, 78 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index bbc1650..23116a7 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -8,6 +8,12 @@ help Select this option if the LPC bridge supports ROM sharing. +config SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + bool + select X86_CUSTOM_BOOTMEDIA + help + Select this option to enable SPI DMA support. + config SOC_AMD_COMMON_BLOCK_HAS_ESPI bool help diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc index 4fbc061..7900b10d 100644 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -11,6 +11,16 @@ endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y) +bootblock-y += spi_dma.c +ifneq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +verstage-y += spi_dma.c +endif +romstage-y += spi_dma.c +ramstage-y += spi_dma.c +smm-y += spi_dma.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA + ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI),y) bootblock-y += espi_util.c diff --git a/src/soc/amd/common/block/lpc/spi_dma.c b/src/soc/amd/common/block/lpc/spi_dma.c new file mode 100644 index 0000000..470bfb1 --- /dev/null +++ b/src/soc/amd/common/block/lpc/spi_dma.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot_device.h> +#include <commonlib/helpers.h> +#include <commonlib/region.h> +#include <spi_flash.h> +#include <string.h> +#include <types.h> + +/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ +#define rom_base ((void *)(uintptr_t)(0x100000000ULL - CONFIG_ROM_SIZE)) + +static void *spi_dma_mmap(const struct region_device *rd, size_t offset, size_t size __unused) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + return &mdev->base[offset]; +} + +static int spi_dma_munmap(const struct region_device *rd __unused, void *mapping __unused) +{ + return 0; +} + +static ssize_t spi_dma_readat_mmap(const struct region_device *rd, void *b, size_t offset, + size_t size) +{ + const struct mem_region_device *mdev; + + mdev = container_of(rd, __typeof__(*mdev), rdev); + + memcpy(b, &mdev->base[offset], size); + + return size; +} + +const struct region_device_ops spi_dma_rdev_ro_ops = { + .mmap = spi_dma_mmap, + .munmap = spi_dma_munmap, + .readat = spi_dma_readat_mmap, +}; + +static const struct mem_region_device boot_dev = { + .base = rom_base, + .rdev = REGION_DEV_INIT(&spi_dma_rdev_ro_ops, 0, CONFIG_ROM_SIZE), +}; + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} + +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) +{ + table->flash_base = 0; + table->host_base = (uint32_t)(uintptr_t)rom_base; + table->size = CONFIG_ROM_SIZE; + + return 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/55854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id26e2a69601d0f31e256d0010008904a447c8e21 Gerrit-Change-Number: 55854 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: arch/x86: Add X86_CUSTOM_BOOTMEDIA
by Raul Rangel (Code Review) 03 Jul '21

03 Jul '21

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55853 ) Change subject: arch/x86: Add X86_CUSTOM_BOOTMEDIA ...................................................................... arch/x86: Add X86_CUSTOM_BOOTMEDIA In order to disable X86_TOP4G_BOOTMEDIA_MAP it requires the definition to be overridden. This makes it a little less ergonomic to use. Instead introduce the inverse option that can be selected. I chose to leave X86_TOP4G_BOOTMEDIA_MAP since it keeps the Makefiles simple. BUG=b:179699789 TEST=none Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I65bbc118bde88687a7d7749c87acf1cbdc56a269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55853 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/arch/x86/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/common/block/fast_spi/Kconfig 3 files changed, 14 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index ef07a2a..6af3fa8 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -137,11 +137,15 @@ # Traditionally BIOS region on SPI flash boot media was memory mapped right below # 4G and it was the last region in the IFD. This way translation between CPU # address space to flash address was trivial. However some IFDs on newer SoCs -# have BIOS region sandwiched between descriptor and other regions. Turning off -# this option enables soc code to provide custom mmap_boot.c which can be used to -# implement complex translation. +# have BIOS region sandwiched between descriptor and other regions. Turning on +# X86_CUSTOM_BOOTMEDIA disables X86_TOP4G_BOOTMEDIA_MAP which allows the +# soc code to provide custom mmap_boot.c. +config X86_CUSTOM_BOOTMEDIA + bool + config X86_TOP4G_BOOTMEDIA_MAP bool + depends on !X86_CUSTOM_BOOTMEDIA default y # This is something you almost certainly don't want to mess with. diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d81015e..6395f16 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -112,6 +112,9 @@ select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI select HAVE_ASAN_IN_ROMSTAGE + # This SoC does not map SPI flash like many previous SoC. Therefore we + # provide a custom media driver that facilitates mapping + select X86_CUSTOM_BOOTMEDIA config MAX_CPUS int @@ -173,12 +176,6 @@ hex default 0x8000 -# This SoC does not map SPI flash like many previous SoC. Therefore we provide -# a custom media driver that facilitates mapping -config X86_TOP4G_BOOTMEDIA_MAP - bool - default n - config ROMSTAGE_ADDR hex default 0xfef20000 diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig index eb2373c..9257bde 100644 --- a/src/soc/intel/common/block/fast_spi/Kconfig +++ b/src/soc/intel/common/block/fast_spi/Kconfig @@ -15,6 +15,10 @@ config FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW bool depends on SOC_INTEL_COMMON_BLOCK_FAST_SPI + # Enable X86_CUSTOM_BOOTMEDIA because the fast SPI controller + # driver provides a custom boot media device when multiple decode + # windows are used for the BIOS region. + select X86_CUSTOM_BOOTMEDIA help Fast SPI controller on the platform supports additional window for memory mapping BIOS region (region 1) on the SPI @@ -45,14 +49,3 @@ Maximum size of the extended window reserved for mapping BIOS region greater than 16MiB. The actual mapped window might be smaller depending upon the size of the BIOS region. - -if FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW - -# Disable X86_TOP4G_BOOTMEDIA_MAP because the fast SPI controller -# driver provides a custom boot media device when multiple decode -# windows are used for the BIOS region. - -config X86_TOP4G_BOOTMEDIA_MAP - default n - -endif -- To view, visit https://review.coreboot.org/c/coreboot/+/55853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65bbc118bde88687a7d7749c87acf1cbdc56a269 Gerrit-Change-Number: 55853 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/dedede: Fix the pointer/address used in memcpy
by Evan Green (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Martin Roth, Paul Menzel, Karthik Ramasubramanian. Evan Green has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56046 ) Change subject: mb/google/dedede: Fix the pointer/address used in memcpy ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa Gerrit-Change-Number: 56046 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Henry Sun <henrysun(a)google.com> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 02 Jul 2021 21:53:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: intel/harcuvar/Kconfig: Clean up unused code
by Nico Huber (Code Review) 02 Jul '21

02 Jul '21

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Arthur Heymans, Michal Motyl. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56043 ) Change subject: intel/harcuvar/Kconfig: Clean up unused code ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f243d8ef4682bfc51fb6ba5af939308a875a0d1 Gerrit-Change-Number: 56043 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Comment-Date: Fri, 02 Jul 2021 21:47:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2021