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I'd like you to reexamine a change. Please visit
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Change subject: drivers/usb/acpi: Create function to get PLD information
......................................................................
drivers/usb/acpi: Create function to get PLD information
Create a separate function to get PLD information from USB device.
This is helpful in retimer driver where we can attach same USB
port information to retimer instance and we can avoid duplication
of information.
BUG=None
BRANCH=None
TEST=Check if code compiles and function returns correct value
Change-Id: Iaaf140ce1965dce3a812aa2701ce0e29b34ab3e7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/drivers/usb/acpi/chip.h
M src/drivers/usb/acpi/usb_acpi.c
2 files changed, 28 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/56024/4
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Change subject: drivers/intel/usb4/retimer: Update code to assign correct port number
......................................................................
Patch Set 8:
(5 comments)
File src/drivers/intel/usb4/retimer/retimer.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123283):
https://review.coreboot.org/c/coreboot/+/55945/comment/8e328fd5_be7ffd6b
PS8, Line 359: printk(BIOS_ERR,"%s: No DFP%1d power GPIO for %s\n", __func__, dfp_port,
space required after that ',' (ctx:VxV)
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123283):
https://review.coreboot.org/c/coreboot/+/55945/comment/f625fd3f_26633e65
PS8, Line 360: dev_path(dev));
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123283):
https://review.coreboot.org/c/coreboot/+/55945/comment/d2cdc93f_735f9046
PS8, Line 360: dev_path(dev));
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123283):
https://review.coreboot.org/c/coreboot/+/55945/comment/0cad8315_29852c75
PS8, Line 379: printk(BIOS_ERR,"Error retrieving PLD for USB Type-C %d\n", usb_port);
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123283):
https://review.coreboot.org/c/coreboot/+/55945/comment/14e17bb9_89a90961
PS8, Line 379: printk(BIOS_ERR,"Error retrieving PLD for USB Type-C %d\n", usb_port);
space required after that ',' (ctx:VxV)
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Change subject: drivers/usb/acpi: Create function to get PLD information
......................................................................
Patch Set 3:
(1 comment)
File src/drivers/usb/acpi/usb_acpi.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123282):
https://review.coreboot.org/c/coreboot/+/56024/comment/2137bc17_7e8d02b0
PS3, Line 131: if (!usb_device || !usb_device->chip_info || usb_device->chip_ops != &drivers_usb_acpi_ops)
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Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/common/block/cpu/update_microcode.c:
https://review.coreboot.org/c/coreboot/+/55987/comment/41bf2a42_4dd56fbf
PS3, Line 112: ucode_list
> Since the parent CL was abandoned, this needs to be reworked.
Dropped the const.
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Hello build bot (Jenkins), Jason Glenesk, Furquan Shaikh, Martin Roth, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55987
to look at the new patch set (#4).
Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
......................................................................
soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
We are currently reading the uCode for each CPU. This is unnecessary
since the uCode never changes.
BUG=b:177909625
TEST=Boot guybrush and see "microcode: being updated to patch id" for
each CPU. I no longer see CBFS access for each CPU. This drops device
initialization time by 32 ms.
Also boot Ezkinil and verify microcode was also updated.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: I98b9d4ce8290a1f08063176809e903e671663208
---
M src/soc/amd/common/block/cpu/update_microcode.c
1 file changed, 37 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/55987/4
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Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/common/block/cpu/update_microcode.c:
https://review.coreboot.org/c/coreboot/+/55987/comment/428f51da_c898919f
PS3, Line 112: ucode_list
Since the parent CL was abandoned, this needs to be reworked.
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Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
......................................................................
Removed Code-Review+2 by Furquan Shaikh <furquan(a)google.com>
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Change subject: configs: Build test x86_64 on Sandy Bridge
......................................................................
Patch Set 11:
(1 comment)
File configs/config.hp_compaq_8200_elite_sff_pc.x86_64:
https://review.coreboot.org/c/coreboot/+/55472/comment/4fc26bea_cafa9cb3
PS10, Line 4: CONFIG_NO_GFX_INIT=y
> looks like that. I'll rebase the patch.
Done
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Change subject: configs/config.foxconn_g41m: Buildtest with X86_64
......................................................................
Patch Set 1: Code-Review+2
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