coreboot-gerrit July 2021

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Change in coreboot[master]: HACK sc7280: Fix TPM failures HACK
by Ravi kumar (Code Review) 04 Jul '21

04 Jul '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56064 ) Change subject: HACK sc7280: Fix TPM failures HACK ...................................................................... HACK sc7280: Fix TPM failures HACK fix boot tpm failures with below upstream gerrit https://review.coreboot.org/c/coreboot/+/55829 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I56d3576ddc078021a7d7ad0af074e01ef982d614 --- M src/mainboard/google/herobrine/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/56064/1 diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index 7f88b94..afada30 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -17,8 +17,8 @@ select SPI_FLASH_WINBOND select SPI_FLASH_MACRONIX select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_SENOR - select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_SENOR +# select MAINBOARD_HAS_SPI_TPM_CR50 if !BOARD_GOOGLE_SENOR +# select MAINBOARD_HAS_TPM2 if !BOARD_GOOGLE_SENOR config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES if !BOARD_GOOGLE_SENOR -- To view, visit https://review.coreboot.org/c/coreboot/+/56064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56d3576ddc078021a7d7ad0af074e01ef982d614 Gerrit-Change-Number: 56064 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/qualcomm/sc7280: Replace gpio offset value with macro
by Ravi kumar (Code Review) 04 Jul '21

04 Jul '21

Attention is currently required from: Ravi kumar, Taniya Das. Hello build bot (Jenkins), Taniya Das, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55949 to look at the new patch set (#2). Change subject: soc/qualcomm/sc7280: Replace gpio offset value with macro ...................................................................... soc/qualcomm/sc7280: Replace gpio offset value with macro Use the gpio offset macro instead of a constant value. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Change-Id: Ia9e4b9ca7216092665f0a06ce467da01963c2364 --- M src/soc/qualcomm/sc7280/include/soc/gpio.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55949/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9e4b9ca7216092665f0a06ce467da01963c2364 Gerrit-Change-Number: 55949 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common/gpio: Define a macro for the gpio offset
by Ravi kumar (Code Review) 04 Jul '21

04 Jul '21

Attention is currently required from: Ravi kumar, Taniya Das, Ravi Kumar Bokka. Hello build bot (Jenkins), Taniya Das, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55948 to look at the new patch set (#2). Change subject: soc/qualcomm/common/gpio: Define a macro for the gpio offset ...................................................................... soc/qualcomm/common/gpio: Define a macro for the gpio offset Defining a macro for the gpio offset instead of a constant value. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Change-Id: Iefdde8f8331cf1df2e88a2c8915aefb4fa091d65 --- M src/soc/qualcomm/common/include/soc/gpio_common.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/55948/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefdde8f8331cf1df2e88a2c8915aefb4fa091d65 Gerrit-Change-Number: 55948 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7180: Add display support for mipi panels
by Ravi kumar (Code Review) 04 Jul '21

04 Jul '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner, mturney mturney. Hello Shelley Chen, build bot (Jenkins), Julius Werner, mturney mturney, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52662 to look at the new patch set (#22). Change subject: sc7180: Add display support for mipi panels ...................................................................... sc7180: Add display support for mipi panels Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Signed-off-by: Vinod Polimera <vpolimer(a)codeaurora.org> --- M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/mainboard.c M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/display/dsi.c A src/soc/qualcomm/sc7180/display/panel_driver.c M src/soc/qualcomm/sc7180/include/soc/display/mipi_dsi.h A src/soc/qualcomm/sc7180/include/soc/display/panel.h 7 files changed, 264 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/52662/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/52662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Gerrit-Change-Number: 52662 Gerrit-PatchSet: 22 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Vinod Polimera <vpolimer(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/amd/hudson: Skip setting up LPC decode for base < 0x20
by Paul Menzel (Code Review) 04 Jul '21

04 Jul '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54669 ) Change subject: sb/amd/hudson: Skip setting up LPC decode for base < 0x20 ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Some resource log messages:x ``` Done reading resources. skipping PNP: 002e.7@f4 fixed resource, size=0! skipping PNP: 002e.7@e0 fixed resource, size=0! skipping PNP: 002e.7@e1 fixed resource, size=0! skipping PNP: 002e.108@e0 fixed resource, size=0! skipping PNP: 002e.108@e2 fixed resource, size=0! skipping PNP: 002e.108@e4 fixed resource, size=0! skipping PNP: 002e.108@f0 fixed resource, size=0! skipping PNP: 002e.108@f4 fixed resource, size=0! skipping PNP: 002e.108@f5 fixed resource, size=0! skipping PNP: 002e.108@f6 fixed resource, size=0! skipping PNP: 002e.108@f7 fixed resource, size=0! skipping PNP: 002e.209@e0 fixed resource, size=0! skipping PNP: 002e.309@e4 fixed resource, size=0! skipping PNP: 002e.309@e5 fixed resource, size=0! skipping PNP: 002e.409@f0 fixed resource, size=0! skipping PNP: 002e.a@e6 fixed resource, size=0! skipping PNP: 002e.a@e7 fixed resource, size=0! skipping PNP: 002e.b@e2 fixed resource, size=0! skipping PNP: 002e.b@e4 fixed resource, size=0! skipping PNP: 002e.f@e6 fixed resource, size=0! skipping PNP: 002e.14@e0 fixed resource, size=0! Setting resources... !! Resource didn't fit !! aligned base 1000 size 1000 limit 28f 1fff needs to be <= 28f (limit) PCI: 00:15.2 1c * [0x0 - 0xfff] io !! Resource didn't fit !! aligned base 400 size 10 limit 28f 40f needs to be <= 28f (limit) PCI: 00:11.0 20 * [0x1400 - 0x140f] io !! Resource didn't fit !! aligned base 400 size 8 limit 28f 407 needs to be <= 28f (limit) PCI: 00:11.0 10 * [0x1410 - 0x1417] io !! Resource didn't fit !! aligned base 400 size 8 limit 28f 407 needs to be <= 28f (limit) PCI: 00:11.0 18 * [0x1418 - 0x141f] io !! Resource didn't fit !! aligned base 400 size 4 limit 28f 403 needs to be <= 28f (limit) PCI: 00:11.0 14 * [0x1420 - 0x1423] io !! Resource didn't fit !! aligned base 400 size 4 limit 28f 403 needs to be <= 28f (limit) PCI: 00:11.0 1c * [0x1424 - 0x1427] io !! Resource didn't fit !! aligned base 400 size 2 limit 28f 401 needs to be <= 28f (limit) PNP: 002e.b 62 * [0x1428 - 0x1429] io node 0: mmio_basek=00200000, basek=00400000, limitk=005e0000 add_uma_resource_below_tolm: uma size 0x20000000, memory start 0x60000000 PCI: 00:00.2 44 <- [0x00f0200000 - 0x00f027ffff] size 0x00080000 gran 0x13 mem PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 14 <- [0x0000000100 - 0x00000001ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 18 <- [0x00f0280000 - 0x00f02bffff] size 0x00040000 gran 0x12 mem PCI: 00:01.1 10 <- [0x00f02c0000 - 0x00f02c3fff] size 0x00004000 gran 0x0e mem ERROR: PCI: 00:11.0 10 io size: 0x0000000008 not assigned ERROR: PCI: 00:11.0 14 io size: 0x0000000004 not assigned ERROR: PCI: 00:11.0 18 io size: 0x0000000008 not assigned ERROR: PCI: 00:11.0 1c io size: 0x0000000004 not assigned ERROR: PCI: 00:11.0 20 io size: 0x0000000010 not assigned PCI: 00:11.0 24 <- [0x00f02cc000 - 0x00f02cc7ff] size 0x00000800 gran 0x0b mem PCI: 00:12.0 10 <- [0x00f02c8000 - 0x00f02c8fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 10 <- [0x00f02cd000 - 0x00f02cd0ff] size 0x00000100 gran 0x08 mem PCI: 00:13.0 10 <- [0x00f02c9000 - 0x00f02c9fff] size 0x00001000 gran 0x0c mem PCI: 00:13.2 10 <- [0x00f02ce000 - 0x00f02ce0ff] size 0x00000100 gran 0x08 mem PCI: 00:14.2 10 <- [0x00f02c4000 - 0x00f02c7fff] size 0x00004000 gran 0x0e mem64 PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.7 missing set_resources PNP: 002e.108 e0 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq PNP: 002e.108 e2 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq PNP: 002e.108 e4 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq PNP: 002e.108 f0 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq PNP: 002e.108 f4 <- [0x0000000008 - 0x0000000007] size 0x00000000 gran 0x00 irq PNP: 002e.108 f5 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq PNP: 002e.108 f6 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq PNP: 002e.108 f7 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq PNP: 002e.209 e0 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq PNP: 002e.309 e4 <- [0x000000007f - 0x000000007e] size 0x00000000 gran 0x00 irq PNP: 002e.309 e5 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq PNP: 002e.409 f0 <- [0x00000000ff - 0x00000000fe] size 0x00000000 gran 0x00 irq PNP: 002e.509 f4 <- [0x00000000ff - 0x00000000ff] size 0x00000001 gran 0x00 irq WARNING: PNP: 002e.509 f5 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.609 f4 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.609 f5 irq size: 0x0000000001 not assigned in devicetree PNP: 002e.a e6 <- [0x000000004c - 0x000000004b] size 0x00000000 gran 0x00 irq PNP: 002e.a e7 <- [0x0000000011 - 0x0000000010] size 0x00000000 gran 0x00 irq PNP: 002e.a f2 <- [0x000000005d - 0x000000005d] size 0x00000001 gran 0x00 irq PNP: 002e.b 60 <- [0x0000000290 - 0x0000000291] size 0x00000002 gran 0x01 io PNP: 002e.b e2 <- [0x000000007f - 0x000000007e] size 0x00000000 gran 0x00 irq PNP: 002e.b e4 <- [0x00000000f1 - 0x00000000f0] size 0x00000000 gran 0x00 irq ERROR: PNP: 002e.b 62 io size: 0x0000000002 not assigned in devicetree ERROR: PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree WARNING: PNP: 002e.b f0 irq size: 0x0000000001 not assigned in devicetree PNP: 002e.f e6 <- [0x0000000007 - 0x0000000006] size 0x00000000 gran 0x00 irq PNP: 002e.14 e0 <- [0x0000000000 - 0xffffffffffffffff] size 0x00000000 gran 0x00 irq PCI: 00:14.4 1c <- [0x000000028f - 0x000000028e] size 0x00000000 gran 0x0c bus 01 io PCI: 00:14.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:14.4 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 mem PCI: 00:14.5 10 <- [0x00f02ca000 - 0x00f02cafff] size 0x00001000 gran 0x0c mem PCI: 00:15.0 1c <- [0x000000028f - 0x000000028e] size 0x00000000 gran 0x0c bus 02 io PCI: 00:15.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:15.0 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:15.1 1c <- [0x000000028f - 0x000000028e] size 0x00000000 gran 0x0c bus 03 io PCI: 00:15.1 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:15.1 20 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 03:00.0 10 <- [0x00f0000000 - 0x00f0007fff] size 0x00008000 gran 0x0f mem64 PCI: 00:15.2 1c <- [0x0000000000 - 0x0000000fff] size 0x00001000 gran 0x0c bus 04 io PCI: 00:15.2 24 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran 0x14 bus 04 prefmem PCI: 00:15.2 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 04 mem PCI: 04:00.0 10 <- [0x0000000000 - 0x00000000ff] size 0x00000100 gran 0x08 io PCI: 04:00.0 18 <- [0x00f0104000 - 0x00f0104fff] size 0x00001000 gran 0x0c prefmem64 PCI: 04:00.0 20 <- [0x00f0100000 - 0x00f0103fff] size 0x00004000 gran 0x0e prefmem64 PCI: 00:16.0 10 <- [0x00f02cb000 - 0x00f02cbfff] size 0x00001000 gran 0x0c mem PCI: 00:16.2 10 <- [0x00f02cf000 - 0x00f02cf0ff] size 0x00000100 gran 0x08 mem Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 1 / 352 ms ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/54669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idec3832d8d1ab95ae9747ce87792ee7b474540c7 Gerrit-Change-Number: 54669 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 04 Jul 2021 17:56:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/board_status: Do not display grep message
by Paul Menzel (Code Review) 04 Jul '21

04 Jul '21

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56056 ) Change subject: util/board_status: Do not display grep message ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56056/comment/e7f1d96c_7cf3f15d PS1, Line 14: Datei oder Verzeichnis nicht gefunden > No such file or directory Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5400d4bd17e957b4cc1bf75bbd332d60ad226f5 Gerrit-Change-Number: 56056 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sun, 04 Jul 2021 17:51:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: Continue in ahci_cmdslot_exec() despite unset HBA_PxCMD_CR
by Paul Menzel (Code Review) 04 Jul '21

04 Jul '21

Attention is currently required from: Raul Rangel, Nico Huber, Michał Żygowski, Marshall Dawson, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56062 ) Change subject: libpayload: Continue in ahci_cmdslot_exec() despite unset HBA_PxCMD_CR ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Those folks working with AMD devices, have you seen this on your systems? Or are you only using NVMe, so are not affected? -- To view, visit https://review.coreboot.org/c/coreboot/+/56062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b94cf4aa40dce587f52350ff4624946aeaafcc0 Gerrit-Change-Number: 56062 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 04 Jul 2021 17:49:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Set xHCI LFPS period sampling off time
by Ben Kao (Code Review) 04 Jul '21

04 Jul '21

Ben Kao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56063 ) Change subject: soc/intel/jasperlake: Set xHCI LFPS period sampling off time ...................................................................... soc/intel/jasperlake: Set xHCI LFPS period sampling off time Provide a option to set xHCI LFPS period sampling off time. If the option is set in the devicetree, the bits[7:4] in xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated. BUG=b:187801363 TEST=build coreboot with XhciLfpsSamplingOffTime and flash the image to the device. Run following command to check the bits[7:4]: iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Ben Kao <ben.kao(a)intel.com> Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/finalize.c 3 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/56063/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 9064297..ae4d5a3 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -206,6 +206,9 @@ # Enable HECI register "HeciEnabled" = "1" + # Set xHCI LFPS period sampling off time, the default is 9. + register "XhciLfpsSamplingOffTime" = "9" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 36e9a13..cd71501 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -85,6 +85,11 @@ /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; + /* Set the LFPS periodic sampling off time for USB3 Ports. + * Default value of PMCTRL_REG bits[7:4] is 9 which means periodic + * sampling off interval is 9ms, the range is from 0 to 15. */ + uint8_t XhciLfpsSamplingOffTime; + /* SATA related */ uint8_t SataMode; uint8_t SataSalpSupport; diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 8219f0c..0ff55ee 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -26,6 +26,11 @@ #define MIPI_CLK (1 << 0) #define HDPLL_CLK (0 << 0) +#define XHCI_PMCTRL 0x80A4 +/* BIT[7:4] LFPS periodic sampling off time for USB3 Ports */ +#define PMCTRL_LFPS_OFFTIME_OFFSET 4 +#define PMCTRL_LFPS_OFFTIME_MAX 0xF + static void pch_enable_isclk(void) { pcr_or32(PID_ISCLK, CAMERA1_CLK, CAM_CLK_EN | MIPI_CLK); @@ -38,6 +43,32 @@ pch_enable_isclk(); } +static void set_xhci_lfps_sampling_offtime(uint8_t time_ms) +{ + void *addr; + uint32_t reg; + struct device *xhci_dev = PCH_DEV_XHCI; + const struct resource *res; + + res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + if (time_ms > PMCTRL_LFPS_OFFTIME_MAX) + time_ms = PMCTRL_LFPS_OFFTIME_MAX; + + addr = (void *)(uintptr_t)(res->base + XHCI_PMCTRL); + reg = read32(addr); + if ((reg >> PMCTRL_LFPS_OFFTIME_OFFSET & PMCTRL_LFPS_OFFTIME_MAX) == + time_ms) + return; + + reg &= ~(PMCTRL_LFPS_OFFTIME_MAX << PMCTRL_LFPS_OFFTIME_OFFSET); + reg |= time_ms << PMCTRL_LFPS_OFFTIME_OFFSET; + write32(addr, reg); + printk(BIOS_DEBUG, "Set XHCI PMCTRL register value 0x%x\n", reg); +} + static void pch_finalize(void) { uint32_t reg32; @@ -75,6 +106,9 @@ write32(pmcbase + CPPMVRIC3, reg32); } + /* Set xHCI LFPS period sampling off time */ + set_xhci_lfps_sampling_offtime(config->XhciLfpsSamplingOffTime); + pch_handle_sideband(config); pmc_clear_pmcon_sts(); -- To view, visit https://review.coreboot.org/c/coreboot/+/56063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73 Gerrit-Change-Number: 56063 Gerrit-PatchSet: 1 Gerrit-Owner: Ben Kao <ben.kao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Add public gerrit account
by Felix Singer (Code Review) 04 Jul '21

04 Jul '21

Attention is currently required from: Martin Roth, Stefan Reinauer, David Hendricks, Angel Pons, Public Gerrit, Werner Zeh. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51208 ) Change subject: Add public gerrit account ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Nothing to add to my previous writers. I only can give -1, but I would give -2 if I could. -- To view, visit https://review.coreboot.org/c/coreboot/+/51208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf6d7c47bba10d89956cbb683b8da2e8e04e269d Gerrit-Change-Number: 51208 Gerrit-PatchSet: 4 Gerrit-Owner: Public Gerrit <public-gerrit(a)guerrillamail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Public Gerrit <public-gerrit(a)guerrillamail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sun, 04 Jul 2021 13:33:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Add public gerrit account
by Felix Singer (Code Review) 04 Jul '21

04 Jul '21

Attention is currently required from: Martin Roth, Stefan Reinauer, David Hendricks, Angel Pons, Public Gerrit, Werner Zeh. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51208 ) Change subject: Add public gerrit account ...................................................................... Patch Set 4: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf6d7c47bba10d89956cbb683b8da2e8e04e269d Gerrit-Change-Number: 51208 Gerrit-PatchSet: 4 Gerrit-Owner: Public Gerrit <public-gerrit(a)guerrillamail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Public Gerrit <public-gerrit(a)guerrillamail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Sun, 04 Jul 2021 13:30:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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