coreboot-gerrit July 2021

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by EricR Lai (Code Review) 05 Jul '21

05 Jul '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56074 ) Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... mb/google/brya: Add UsbTcPortEn in devicetree CB:2976591 add new parameter in FSP. Brya uses TCSS port 0/1/2, we need to enable it in devicetree. BUG=b:188481987 TEST=check typeC 3.0 works. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 3 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/56074/1 diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index ce69213..2486b20 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -58,6 +58,9 @@ register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC2)" + # TCSS USB3 + register "UsbTcPortEn" = "0x7" + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 58daa25..ce9372a 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -112,6 +112,12 @@ uint16_t usb3_wake_enable_bitmap; /* Program OC pins for TCSS */ struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; + /* + * Specifies which Type-C Ports are enabled on the system + * each bit represents a port starting at 0 + * Example: set value to 0x3 for ports 0 and 1 to be enabled + */ + uint8_t UsbTcPortEn; /* SATA related */ uint8_t SataEnable; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index e29133e..07aab22 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -289,6 +289,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { + s_cfg->UsbTcPortEn = config->UsbTcPortEn; s_cfg->TcssAuxOri = config->TcssAuxOri; /* Explicitly clear this field to avoid using defaults */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(0x906a0) sil...
by Sridhar Siricilla (Code Review) 05 Jul '21

05 Jul '21

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56073 ) Change subject: mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(0x906a0) silicon ...................................................................... mb/intel/adlrvp: Update PMC Descriptor for Alder lake A0(0x906a0) silicon The patch updates PMC Descriptor which is part of Descriptor Region if system equipped with Alder lake A0 silicon. This change allows to use unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0 (CPUD ID:0x906a1) silicons. BUG=B:187431859 TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon if not updated. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 --- M src/mainboard/intel/adlrvp/bootblock.c 1 file changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/56073/1 diff --git a/src/mainboard/intel/adlrvp/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c index eeee406..e292d1d 100644 --- a/src/mainboard/intel/adlrvp/bootblock.c +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -2,8 +2,64 @@ #include <baseboard/variants.h> #include <bootblock_common.h> +#include <console/console.h> +#include <intelblocks/mp_init.h> +#include <fmap.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <intelblocks/pmclib.h> +#include <cf9_reset.h> + +#define SI_DESC_REGION "SI_DESC" +#define SI_DESC_REGION_SZ 4096 +#define PMC_DESC_7_BYTE3 0xc32 + +/* It updates PMC Descriptor in the Descriptor Region */ +static void configure_pmc_descriptor(void) +{ + uint8_t si_desc_buf[SI_DESC_REGION_SZ]; + struct region_device desc_rdev; + + if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + return; + } + + if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + return; + } + + if (si_desc_buf[PMC_DESC_7_BYTE3] == 0x40) { + si_desc_buf[PMC_DESC_7_BYTE3] = 0x44; + + if (rdev_eraseat(&desc_rdev, 0, SI_DESC_REGION_SZ) != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); + return; + } + + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_REGION_SZ) + != SI_DESC_REGION_SZ) { + printk(BIOS_ERR, "Failed to update Descriptor Region\n"); + return; + } + + printk(BIOS_DEBUG, "Update of PMC Descriptor successful, trigger GLOBAL RESET\n"); + + pmc_global_reset_enable(1); + do_full_reset(); + die("Failed to trigger GLOBAL RESET\n"); + } + + printk(BIOS_DEBUG, "Update of PMC Descriptor is not required!\n"); +} void bootblock_mainboard_early_init(void) { variant_configure_early_gpio_pads(); } +void bootblock_mainboard_init(void) +{ + if (cpu_get_cpuid() == CPUID_ALDERLAKE_A0) + configure_pmc_descriptor(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a1f60fda7575212bb694fc423bd229452515903 Gerrit-Change-Number: 56073 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset
by Subrata Banik (Code Review) 05 Jul '21

05 Jul '21

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54305 ) Change subject: util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > In #coreboot (IRC) a user reports, that this breaks (cold) booting on the Supermicro X11SSH-LN4F. […] this CL basically enforce all IFDv2 platform to use -p at building or parsing binary offline. The assumption being made that if you don't pass -p then its IFDv1. This patch doesn't really change any chipset behavior. Can you please suggest me what is really broken here ? So chipset detection works fine at first place ? -- To view, visit https://review.coreboot.org/c/coreboot/+/54305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Gerrit-Change-Number: 54305 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Jul 2021 08:51:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset
by Paul Menzel (Code Review) 05 Jul '21

05 Jul '21

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54305 ) Change subject: util/ifdtool: Use -p platform name to detect IFDv2 platform and chipset ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: In #coreboot (IRC) a user reports, that this breaks (cold) booting on the Supermicro X11SSH-LN4F. > now everything makes sense, I read somewhere that the JPME2/ME MANUFACTURING MODE pin unlocks the flash descriptor, and that commit breaks the IFD by setting read access to disabled, that's why JPME2 = 2-3 fixes it. -- To view, visit https://review.coreboot.org/c/coreboot/+/54305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25f69ce775454409974056d8326c02e29038ec8a Gerrit-Change-Number: 54305 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Mon, 05 Jul 2021 08:46:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0
by Michael Niewöhner (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Jan Tatje. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56071 ) Change subject: supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0 ...................................................................... Patch Set 2: (1 comment) File src/mainboard/supermicro/x11-lga1151-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/56071/comment/f782d181_ec74c6b6 PS2, Line 4: register "SkipExtGfxScan" = "0" rather drop the whole line, since 0 is the default anyways -- To view, visit https://review.coreboot.org/c/coreboot/+/56071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Gerrit-Change-Number: 56071 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Tatje <jan(a)jnt.io> Gerrit-Comment-Date: Mon, 05 Jul 2021 08:39:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0
by Michael Niewöhner (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Jan Tatje. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56071 ) Change subject: supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: hmm, interesting. could you share your .config, please? I wonder what config was set in regard to libgfxinit -- To view, visit https://review.coreboot.org/c/coreboot/+/56071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Gerrit-Change-Number: 56071 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jan Tatje <jan(a)jnt.io> Gerrit-Comment-Date: Mon, 05 Jul 2021 08:38:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add GFx Device ID 0x46a6
by Maulik V Vaghela (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56026 ) Change subject: soc/intel/alderlake: Add GFx Device ID 0x46a6 ...................................................................... Patch Set 1: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/56026/comment/b026b21d_32841487 PS1, Line 3821: #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6 0x46a6 > Done Sorry Paul, this might interfere with order of Macros. Is that okay? -- To view, visit https://review.coreboot.org/c/coreboot/+/56026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Gerrit-Change-Number: 56026 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 07:25:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add GFx Device ID 0x46a6
by Maulik V Vaghela (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Patrick Rudolph. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56026 ) Change subject: soc/intel/alderlake: Add GFx Device ID 0x46a6 ...................................................................... Patch Set 1: (1 comment) File src/include/device/pci_ids.h: https://review.coreboot.org/c/coreboot/+/56026/comment/508d418d_98f458a2 PS1, Line 3821: #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6 0x46a6 > Please sort by the id. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Gerrit-Change-Number: 56026 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 07:22:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc: common: i2c: Add support for I2C common driver
by Rajesh Patil (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, Paul Menzel, mturney mturney, Julius Werner. Rajesh Patil has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55952 ) Change subject: soc: common: i2c: Add support for I2C common driver ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55952/comment/43a35c44_e5a13c47 PS2, Line 9: This implements i2c driver for qualcomm chipsets > Is this copied? Implemented from scratch from datasheet? Moved Existing SoC specific code to common code -- To view, visit https://review.coreboot.org/c/coreboot/+/55952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16e6fc2c1c24b9814d1803bffd5cfbb657201cfb Gerrit-Change-Number: 55952 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 07:02:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0
by Jan Tatje (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Michael Niewöhner. Hello build bot (Jenkins), Michael Niewöhner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56071 to look at the new patch set (#2). Change subject: supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0 ...................................................................... supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0 Scan for external graphics, allows SeaBIOS to use the AST2400 without disabling the IGD. Tested on X11SSH-LN4F. Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Signed-off-by: Jan Tatje <jan(a)jnt.io> --- M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/56071/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Gerrit-Change-Number: 56071 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021