coreboot-gerrit July 2021

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Change in coreboot[master]: config.emulation_qemu_x86_i440fx: Drop unneeded file
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Werner Zeh, Patrick Rudolph. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56078 ) Change subject: config.emulation_qemu_x86_i440fx: Drop unneeded file ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: tests/Makefile.inc:TEST_DEFAULT_CONFIG = $(top)/configs/config.emulation_qemu_x86_i440fx the test suite relies on it (right now) -- To view, visit https://review.coreboot.org/c/coreboot/+/56078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83faef88673efc86cc813ef6035f67b4c38f1752 Gerrit-Change-Number: 56078 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 10:56:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Provide a proper scheme for variants
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56033 ) Change subject: mb/siemens/mc_ehl: Provide a proper scheme for variants ...................................................................... mb/siemens/mc_ehl: Provide a proper scheme for variants There will be more variants of this mainboard so prepare the scheme for Kconfig to handle the variants properly. Change-Id: If1cf418836d77a45955ee55d30ba670db8ff2533 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56033 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/Kconfig M src/mainboard/siemens/mc_ehl/Kconfig.name 2 files changed, 14 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig index c2eb56e..b5a5a90 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -1,7 +1,5 @@ -if BOARD_SIEMENS_MC_EHL - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_SIEMENS_BASEBOARD_MC_EHL + def_bool n select BOARD_ROMSIZE_KB_32768 select DRIVERS_I2C_HID select DRIVERS_INTEL_DPTF @@ -14,21 +12,21 @@ select HAVE_ACPI_TABLES select SOC_INTEL_ELKHARTLAKE +source "src/mainboard/siemens/mc_ehl/variants/*/Kconfig" + +if BOARD_SIEMENS_BASEBOARD_MC_EHL + config MAINBOARD_DIR string default "siemens/mc_ehl" config VARIANT_DIR string - default "mc_ehl1" if BOARD_SIEMENS_MC_EHL + default "mc_ehl1" if BOARD_SIEMENS_MC_EHL1 config MAINBOARD_PART_NUMBER string - default "MC EHL" - -config MAINBOARD_FAMILY - string - default "Siemens EHL" + default "MC EHL1" if BOARD_SIEMENS_MC_EHL1 config DEVICETREE string @@ -47,4 +45,4 @@ default 2 if INTEL_LPSS_UART_FOR_CONSOLE default 0 -endif +endif # BOARD_SIEMENS_BASEBOARD_MC_EHL diff --git a/src/mainboard/siemens/mc_ehl/Kconfig.name b/src/mainboard/siemens/mc_ehl/Kconfig.name index 0560d39..e38e1e4 100644 --- a/src/mainboard/siemens/mc_ehl/Kconfig.name +++ b/src/mainboard/siemens/mc_ehl/Kconfig.name @@ -1,2 +1,5 @@ -config BOARD_SIEMENS_MC_EHL - bool "MC EHL" +comment "MC EHLx" + +config BOARD_SIEMENS_MC_EHL1 + bool "-> MC EHL1" + select BOARD_SIEMENS_BASEBOARD_MC_EHL -- To view, visit https://review.coreboot.org/c/coreboot/+/56033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1cf418836d77a45955ee55d30ba670db8ff2533 Gerrit-Change-Number: 56033 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crb
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56032 ) Change subject: mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crb ...................................................................... mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crb Add a new mainboard called mc_ehl which is based on Intel's 'elkhartlake_crb'. This commit simply copies the mainboard directory and adjusts the naming to match the new board's name. Follow-up commits will introduce the needed changes for the new mainboard. Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56032 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- A src/mainboard/siemens/mc_ehl/Kconfig A src/mainboard/siemens/mc_ehl/Kconfig.name A src/mainboard/siemens/mc_ehl/Makefile.inc A src/mainboard/siemens/mc_ehl/board_info.txt A src/mainboard/siemens/mc_ehl/bootblock.c A src/mainboard/siemens/mc_ehl/dsdt.asl A src/mainboard/siemens/mc_ehl/mainboard.c A src/mainboard/siemens/mc_ehl/romstage_fsp_params.c A src/mainboard/siemens/mc_ehl/spd/Makefile.inc A src/mainboard/siemens/mc_ehl/spd/empty.spd.hex A src/mainboard/siemens/mc_ehl/spd/mc_ehl.spd.hex A src/mainboard/siemens/mc_ehl/spd/spd.h A src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c 17 files changed, 860 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_ehl/Kconfig b/src/mainboard/siemens/mc_ehl/Kconfig new file mode 100644 index 0000000..c2eb56e --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/Kconfig @@ -0,0 +1,50 @@ +if BOARD_SIEMENS_MC_EHL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_DPTF + select DRIVERS_I2C_GENERIC + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select EC_ACPI + select HAVE_SPD_IN_CBFS + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select SOC_INTEL_ELKHARTLAKE + +config MAINBOARD_DIR + string + default "siemens/mc_ehl" + +config VARIANT_DIR + string + default "mc_ehl1" if BOARD_SIEMENS_MC_EHL + +config MAINBOARD_PART_NUMBER + string + default "MC EHL" + +config MAINBOARD_FAMILY + string + default "Siemens EHL" + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config DIMM_SPD_SIZE + int + default 512 + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2 + +config UART_FOR_CONSOLE + int + default 2 if INTEL_LPSS_UART_FOR_CONSOLE + default 0 + +endif diff --git a/src/mainboard/siemens/mc_ehl/Kconfig.name b/src/mainboard/siemens/mc_ehl/Kconfig.name new file mode 100644 index 0000000..0560d39 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SIEMENS_MC_EHL + bool "MC EHL" diff --git a/src/mainboard/siemens/mc_ehl/Makefile.inc b/src/mainboard/siemens/mc_ehl/Makefile.inc new file mode 100644 index 0000000..382ec2e --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/Makefile.inc @@ -0,0 +1,15 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/siemens/mc_ehl/board_info.txt b/src/mainboard/siemens/mc_ehl/board_info.txt new file mode 100644 index 0000000..72f257d --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Siemens +Board name: MC EHL +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/siemens/mc_ehl/bootblock.c b/src/mainboard/siemens/mc_ehl/bootblock.c new file mode 100644 index 0000000..c39a8ff --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/bootblock.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootblock_common.h> +#include <soc/gpio.h> + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/siemens/mc_ehl/dsdt.asl b/src/mainboard/siemens/mc_ehl/dsdt.asl new file mode 100644 index 0000000..5e93d62 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/elkhartlake/acpi/southbridge.asl> + } + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/siemens/mc_ehl/mainboard.c b/src/mainboard/siemens/mc_ehl/mainboard.c new file mode 100644 index 0000000..c63beb74 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <soc/gpio.h> + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c new file mode 100644 index 0000000..259870a --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static struct spd_info spd_info; + const struct mb_cfg *board_cfg = variant_memcfg_config(); + + /* TODO: Read the resistor strap to get number of memory segments */ + bool half_populated = false; + /* Initialize spd information for LPDDR4x board */ + spd_info.read_type = READ_SPD_CBFS; + spd_info.spd_spec.spd_index = 0x00; + + /* Initialize variant specific configurations */ + memcfg_init(&memupd->FspmConfig, board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/siemens/mc_ehl/spd/Makefile.inc b/src/mainboard/siemens/mc_ehl/spd/Makefile.inc new file mode 100644 index 0000000..6d9e908 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/spd/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = mc_ehl # 0b000 diff --git a/src/mainboard/siemens/mc_ehl/spd/empty.spd.hex b/src/mainboard/siemens/mc_ehl/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_ehl/spd/mc_ehl.spd.hex b/src/mainboard/siemens/mc_ehl/spd/mc_ehl.spd.hex new file mode 100644 index 0000000..71e5456 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/spd/mc_ehl.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/siemens/mc_ehl/spd/spd.h b/src/mainboard/siemens/mc_ehl/spd/spd.h new file mode 100644 index 0000000..f667e74 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/spd/spd.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <stdint.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr); +void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr); +void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr); +void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000..bf05765 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> + +/* The following 2 functions return the gpio table and fill in the number + * of entries for each table. */ +const struct pad_config *variant_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); + +/* This function returns SPD related FSP-M mainboard configs */ +const struct mb_cfg *variant_memcfg_config(void); + +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc new file mode 100644 index 0000000..641e814 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += memory.c +ramstage-y += gpio.c diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb new file mode 100644 index 0000000..7c1d48a --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -0,0 +1,259 @@ +chip soc/intel/elkhartlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_F" + register "pmc_gpe0_dw2" = "GPP_E" + + # Enable heci1 communication + register "HeciEnabled" = "1" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "Heci2Enable" = "1" + + # Display related UPDs + # Enable HPD for DDI ports C + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI ports C + register "DdiPortCDdc" = "1" + + # USB related UPDs + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # USB2 WWAN + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Bluetooth + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-C Port1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port3 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port4 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Type A port2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # USB3 WLAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # UNUSED + + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + + # PCIe root ports related UPDs + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + + register "PcieClkSrcUsage[0]" = "0x00" + register "PcieClkSrcUsage[1]" = "0x06" + register "PcieClkSrcUsage[2]" = "0x04" + register "PcieClkSrcUsage[3]" = "0xFF" + register "PcieClkSrcUsage[4]" = "0xFF" + register "PcieClkSrcUsage[5]" = "0xFF" + + register "PcieClkSrcClkReq[0]" = "0x0" + register "PcieClkSrcClkReq[1]" = "0x1" + register "PcieClkSrcClkReq[2]" = "0x2" + register "PcieClkSrcClkReq[3]" = "0x3" + register "PcieClkSrcClkReq[4]" = "0x4" + register "PcieClkSrcClkReq[5]" = "0x5" + + # Storage (SATA/SDCARD/EMMC) related UPDs + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" + + register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcDdr50Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + # LPSS Serial IO (I2C/UART/GSPI) related UPDs + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexI2C6] = PchSerialIoPci, + [PchSerialIoIndexI2C7] = PchSerialIoPci, + }" + + register "SerialIoI2cPadsTermination" = "{ + [PchSerialIoIndexI2C0] = 1, + [PchSerialIoIndexI2C1] = 1, + [PchSerialIoIndexI2C2] = 1, + [PchSerialIoIndexI2C3] = 1, + [PchSerialIoIndexI2C4] = 1, + [PchSerialIoIndexI2C5] = 1, + [PchSerialIoIndexI2C6] = 1, + [PchSerialIoIndexI2C7] = 1, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoHidden, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsEnable" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + register "SerialIoUartDmaEnable" = "{ + [PchSerialIoIndexUART0] = 1, + [PchSerialIoIndexUART1] = 1, + [PchSerialIoIndexUART2] = 1, + }" + + # TSN GBE related UPDs + register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" + register "PchTsnGbeSgmiiEnable" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 08.0 off end # GNA + device pci 09.0 off end # CPU Intel Trace Hub + + device pci 10.0 on end # I2C6 + device pci 10.1 on end # I2C7 + device pci 10.5 on end # Integrated Error Handler + + device pci 11.0 off end # Intel PSE UART0 + device pci 11.1 off end # Intel PSE UART1 + device pci 11.2 off end # Intel PSE UART2 + device pci 11.3 off end # Intel PSE UART3 + device pci 11.4 off end # Intel PSE UART4 + device pci 11.5 off end # Intel PSE UART5 + device pci 11.6 off end # Intel PSE IS20 + device pci 11.7 off end # Intel PSE IS21 + + device pci 12.0 on end # GSPI2 + device pci 12.3 on end # Management Engine UMA Access + device pci 12.4 on end # Management Engine PTT DMA Controller + device pci 12.5 off end # UFS0 + device pci 12.7 off end # UFS1 + + device pci 13.0 off end # Intel PSE GSPI0 + device pci 13.1 off end # Intel PSE GSPI1 + device pci 13.2 off end # Intel PSE GSPI2 + device pci 13.3 off end # Intel PSE GSPI3 + device pci 13.4 off end # Intel PSE GPIO0 + device pci 13.5 off end # Intel PSE GPIO1 + + device pci 14.0 on end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI (OTG) + + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 16.4 on end # Management Engine Interface 3 + device pci 16.5 on end # Management Engine Interface 4 + + device pci 17.0 on end # SATA + + device pci 18.0 off end # Intel PSE I2C7 + device pci 18.1 off end # Intel PSE CAN0 + device pci 18.2 off end # Intel PSE CAN1 + device pci 18.3 off end # Intel PSE QEP0 + device pci 18.4 off end # Intel PSE QEP1 + device pci 18.5 off end # Intel PSE QEP2 + device pci 18.6 off end # Intel PSE QEP3 + + device pci 19.0 on end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 on end # UART2 + + device pci 1a.0 on end # eMMC + device pci 1a.1 off end # SD + device pci 1a.3 off end # Intel Safety Island + + device pci 1b.0 off end # Intel PSE I2C0 + device pci 1b.1 off end # Intel PSE I2C1 + device pci 1b.2 off end # Intel PSE I2C2 + device pci 1b.3 off end # Intel PSE I2C3 + device pci 1b.4 off end # Intel PSE I2C4 + device pci 1b.5 off end # Intel PSE I2C5 + device pci 1b.6 off end # Intel PSE I2C6 + + device pci 1c.0 on end # RP1 (pcie0 single VC) + device pci 1c.1 on end # RP2 (pcie0 single VC) + device pci 1c.2 on end # RP3 (pcie0 single VC) + device pci 1c.3 on end # RP4 (pcie0 single VC) + device pci 1c.4 on end # RP5 (pcie1 multi VC) + device pci 1c.5 on end # RP6 (pcie2 multi VC) + device pci 1c.6 on end # RP7 (pcie3 multi VC) + + device pci 1d.0 off end # Intel PSE IPC (local host to PSE) + device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0 + device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1 + device pci 1d.3 off end # Intel PSE DMA0 + device pci 1d.4 off end # Intel PSE DMA1 + device pci 1d.5 off end # Intel PSE DMA2 + device pci 1d.6 off end # Intel PSE PWM + device pci 1d.7 off end # Intel PSE ADC + + device pci 1e.0 on end # UART0 + device pci 1e.1 on end # UART1 + device pci 1e.2 on end # GSPI0 + device pci 1e.3 on end # GSPI1 + device pci 1e.4 on end # PCH Time-Sensitive Networking GbE + device pci 1e.6 on end # HPET + device pci 1e.7 on end # IOAPIC + + device pci 1f.0 on end # eSPI Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 off end # Intel cAVS/HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI (flash & TPM) + device pci 1f.7 off end # PCH Intel Trace Hub + end +end diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c new file mode 100644 index 0000000..9d17c80 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/gpio.c @@ -0,0 +1,280 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { +/*BT_RF_KILL_N*/ +PAD_CFG_GPO(GPP_E11, 1, DEEP), + +/*WIFI_RF_KILL_N*/ +PAD_CFG_GPO(GPP_E10, 1, DEEP), + +/*M.2_WLAN_PERST_N*/ +PAD_CFG_GPO(GPD7, 1, PLTRST), + +/*M.2_WLAN_SLP*/ +PAD_CFG_GPO(GPD9, 1, PLTRST), + +/*WIFI_WAKE_N*/ +PAD_CFG_GPI_SCI(GPP_F4, UP_5K, DEEP, LEVEL, INVERT), + +/*UART_BT_WAKE_N*/ +PAD_CFG_GPI_SCI(GPP_F20, NONE, DEEP, LEVEL, INVERT), + +/*ONBOARD_X4_PCIE_SLOT1_RESET_N*/ +PAD_CFG_GPO(GPD11, 1, PLTRST), + +/*ONBOARD_X4_PCIE_SLOT1_WAKE_N*/ +PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + +/*M.2_WWAN_PWR_EN*/ +PAD_CFG_GPO(GPP_F21, 1, PLTRST), + +/*M.2_WWAN_RST_N*/ +PAD_CFG_GPO(GPP_V13, 1, PLTRST), + +/*M.2_WWAN_PE_RST_N*/ +PAD_CFG_GPO(GPP_B14, 1, PLTRST), + +/*M.2_WWAN_PE_WAKE_N*/ +PAD_CFG_GPO(GPP_B17, 1, PLTRST), + +/*M.2_WWAN_FCP_OFF_N*/ +PAD_CFG_GPO(GPP_E0, 1, PLTRST), + +/*M.2_SSD_SATA_DEVSLP_1*/ +PAD_CFG_NF(GPP_E8, NONE, DEEP, NF2), + +/*BC_PROCHOT_N*/ +PAD_CFG_GPI_SCI(GPP_B2, NONE, PLTRST, EDGE_SINGLE, INVERT), + +/*FPS_RST_N*/ +PAD_CFG_GPO(GPP_V14, 1, PLTRST), + +/*FPS_INT*/ +PAD_CFG_GPI_APIC(GPP_V15, NONE, PLTRST, LEVEL, NONE), + +/*CODEC_INT_N*/ +PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + +/*TCH_PNL_PWR_EN*/ +PAD_CFG_GPO(GPP_B16, 1, PLTRST), + +/*THC0_SPI1_INT_N*/ +PAD_CFG_GPI_APIC(GPP_E17, NONE, PLTRST, LEVEL, INVERT), + +/*SPI_TPM_INT_N*/ +PAD_CFG_GPI_APIC(GPP_G19, NONE, DEEP, LEVEL, NONE), + +/*EMMC_CMD*/ +PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), + +/*EMMC_DATA0*/ +PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), + +/*EMMC_DATA1*/ +PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), + +/*EMMC_DATA2*/ +PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), + +/*EMMC_DATA3*/ +PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), + +/*EMMC_DATA4*/ +PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), + +/*EMMC_DATA5*/ +PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), + +/*EMMC_DATA6*/ +PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), + +/*EMMC_DATA7*/ +PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), + +/*EMMC_RCLK*/ +PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), + +/*EMMC_CLK*/ +PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), + +/*EMMC_RESET*/ +PAD_CFG_NF(GPP_V11, UP_20K, DEEP, NF1), + +/*ACPRESENT*/ +PAD_CFG_NF(GPD1, NONE, PLTRST, NF1), + +/*RGMII0_MDC*/ +PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + +/*RGMII0_MDIO*/ +PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + +/*RGMII0_INT*/ +PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + +/*RGMII0_RESETB*/ +PAD_CFG_GPO(GPP_T5, 1, DEEP), + +/*RGMII0_AUXTS*/ +PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + +/*RGMII0_PPS*/ +PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + +/*RGMII1_MDC*/ +PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + +/*RGMII1_MDIO*/ +PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + +/*RGMII1_INT*/ +PAD_CFG_NF(GPP_H0, NONE, DEEP, NF1), + +/*RGMII1_RESETB*/ +PAD_CFG_GPO(GPP_H1, 1, DEEP), + +/*RGMII1_AUXTS*/ +PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + +/*RGMII1_PPS*/ +PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), + +/*RGMII2_MDC*/ +PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + +/*RGMII2_MDIO*/ +PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + +/*RGMII2_INT*/ +PAD_CFG_NF(GPP_U0, NONE, DEEP, NF1), + +/*RGMII2_RESETB*/ +PAD_CFG_GPO(GPP_U1, 1, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* UART1 RX */ +PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), + +/* UART1 TX */ +PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), + +/* UART2 RX */ +PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), + +/* UART2 TX */ +PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), + +/*WWAN_FCP_OFF_N*/ +PAD_CFG_GPO(GPP_E0, 1, PLTRST), + +/*WWAN_PWREN*/ +PAD_CFG_GPO(GPP_F21, 1, PLTRST), + +/*WWAN_PERST_N*/ +PAD_CFG_GPO(GPP_B14, 0, PLTRST), + +/*WWAN_RST_N*/ +PAD_CFG_GPO(GPP_V13, 0, PLTRST), + +/* LAN_WAKEB*/ +PAD_CFG_GPI_SCI(GPD2, NONE, DEEP, EDGE_SINGLE, INVERT), + +/*WWAN_RST_N*/ +PAD_CFG_GPO(GPP_V13, 0, PWROK), + +/*WWAN_PERST_N*/ +PAD_CFG_GPO(GPP_B14, 0, PWROK), + +/*WWAN_FCP_OFF_N*/ +PAD_CFG_GPO(GPP_E0, 0, PWROK), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c new file mode 100644 index 0000000..7b7dad1 --- /dev/null +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/memory.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6}, + .dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* LPDDR4x does not allow interleaved memory */ + .dq_pins_interleaved = 0, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &mc_ehl_lpddr4x_memcfg_cfg; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7c0616098046d975aa698910ac81f435d7882cb Gerrit-Change-Number: 56032 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: device: Reflow strings in printk statements
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56057 ) Change subject: device: Reflow strings in printk statements ...................................................................... device: Reflow strings in printk statements To ease finding some log messages, reflow their strings to use one line. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5284429ca6d07debf2d6c4fdbffa286140fb7694 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56057 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/device/device_util.c M src/device/pci_device.c M src/device/pci_rom.c 3 files changed, 25 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/device/device_util.c b/src/device/device_util.c index a5d1860..8ee8afc 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -870,8 +870,8 @@ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR " - "0x%08lx-0x%08lx.\n", (unsigned long)(resource->base), + printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", + (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 63c1dc5..4b5e73b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -149,8 +149,7 @@ */ if (moving == 0) { if (value != 0) { - printk(BIOS_DEBUG, "%s register %02lx(%08lx), " - "read-only ignoring it\n", + printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n", dev_path(dev), index, value); } resource->flags = 0; @@ -234,8 +233,7 @@ resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY; } else { if (value != 0) { - printk(BIOS_DEBUG, "%s register %02lx(%08lx), " - "read-only ignoring it\n", + printk(BIOS_DEBUG, "%s register %02lx(%08lx), read-only ignoring it\n", dev_path(dev), index, value); } resource->flags = 0; @@ -512,8 +510,8 @@ we can treat it like an empty resource. */ resource->size = 0; } else { - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not " - "assigned\n", dev_path(dev), resource->index, + printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not assigned\n", + dev_path(dev), resource->index, resource_type(resource), resource->size); return; } @@ -980,9 +978,9 @@ default: bad: if (dev->enabled) { - printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown " - "header type %02x, ignoring.\n", dev_path(dev), - dev->vendor, dev->device, + printk(BIOS_ERR, + "%s [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n", + dev_path(dev), dev->vendor, dev->device, dev->class >> 8, dev->hdr_type); } } @@ -1107,8 +1105,9 @@ if ((id == 0xffffffff) || (id == 0x00000000) || (id == 0x0000ffff) || (id == 0xffff0000)) { if (dev->enabled) { - printk(BIOS_INFO, "PCI: Static device %s not " - "found, disabling it.\n", dev_path(dev)); + printk(BIOS_INFO, + "PCI: Static device %s not found, disabling it.\n", + dev_path(dev)); dev->enabled = 0; } return dev; diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index 663895c..334d99b 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -78,14 +78,14 @@ rom_header = (struct rom_header *)rom_address; } - printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, " - "INIT size 0x%04x, data ptr 0x%04x\n", + printk(BIOS_SPEW, + "PCI expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n", le32_to_cpu(rom_header->signature), rom_header->size * 512, le32_to_cpu(rom_header->data)); if (le32_to_cpu(rom_header->signature) != PCI_ROM_HDR) { - printk(BIOS_ERR, "Incorrect expansion ROM header " - "signature %04x\n", le32_to_cpu(rom_header->signature)); + printk(BIOS_ERR, "Incorrect expansion ROM header signature %04x\n", + le32_to_cpu(rom_header->signature)); return NULL; } @@ -97,13 +97,13 @@ if ((dev->vendor != rom_data->vendor || dev->device != rom_data->device) && (vendev == mapped_vendev)) { - printk(BIOS_ERR, "ID mismatch: vendor ID %04x, " - "device ID %04x\n", dev->vendor, dev->device); + printk(BIOS_ERR, "ID mismatch: vendor ID %04x, device ID %04x\n", + dev->vendor, dev->device); return NULL; } - printk(BIOS_SPEW, "PCI ROM image, Class Code %04x%02x, " - "Code Type %02x\n", rom_data->class_hi, rom_data->class_lo, + printk(BIOS_SPEW, "PCI ROM image, Class Code %04x%02x, Code Type %02x\n", + rom_data->class_hi, rom_data->class_lo, rom_data->type); if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { @@ -152,17 +152,17 @@ if (dev != vga_pri) return NULL; /* Only one VGA supported. */ #endif if ((void *)PCI_VGA_RAM_IMAGE_START != rom_header) { - printk(BIOS_DEBUG, "Copying VGA ROM Image from %p to " - "0x%x, 0x%x bytes\n", rom_header, - PCI_VGA_RAM_IMAGE_START, rom_size); + printk(BIOS_DEBUG, + "Copying VGA ROM Image from %p to 0x%x, 0x%x bytes\n", + rom_header, PCI_VGA_RAM_IMAGE_START, rom_size); memcpy((void *)PCI_VGA_RAM_IMAGE_START, rom_header, rom_size); } return (struct rom_header *) (PCI_VGA_RAM_IMAGE_START); } - printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x " - "bytes\n", rom_header, pci_ram_image_start, rom_size); + printk(BIOS_DEBUG, "Copying non-VGA ROM image from %p to %p, 0x%x bytes\n", + rom_header, pci_ram_image_start, rom_size); memcpy(pci_ram_image_start, rom_header, rom_size); pci_ram_image_start += rom_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/56057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5284429ca6d07debf2d6c4fdbffa286140fb7694 Gerrit-Change-Number: 56057 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/intel/adlrvp_m: Remove ASL code and enable dynamic SSDT creation f...
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55733 ) Change subject: mb/intel/adlrvp_m: Remove ASL code and enable dynamic SSDT creation for camera ACPI ...................................................................... mb/intel/adlrvp_m: Remove ASL code and enable dynamic SSDT creation for camera ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/intel/adlrvp/Kconfig.name M src/mainboard/intel/adlrvp/devicetree_m.cb 2 files changed, 104 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name index c05074b..341b717 100644 --- a/src/mainboard/intel/adlrvp/Kconfig.name +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -15,7 +15,11 @@ bool "Alderlake-M RVP" select DRIVERS_UART_8250IO select MAINBOARD_USES_IFD_EC_REGION + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_INTEL_ADLRVP_M_EXT_EC bool "Alderlake-M RVP with Chrome EC" select INTEL_LPSS_UART_FOR_CONSOLE + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 0462a2b..34aee72 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -157,7 +157,21 @@ device ref pcie5 on end device ref igpu on end device ref dtt on end - device ref ipu on end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1"" + register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 0 on end + end + end device ref pcie4_0 on end device ref pcie4_1 on end device ref tbt_pcie_rp0 on end @@ -198,12 +212,95 @@ end end device ref i2c0 on end - device ref i2c1 on end + device ref i2c1 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + end device ref i2c2 on end device ref i2c3 on end device ref heci1 on end device ref sata on end - device ref i2c5 on end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end device ref pcie_rp1 on end device ref pcie_rp3 on end # W/A to FSP issue device ref pcie_rp4 on end # W/A to FSP issue -- To view, visit https://review.coreboot.org/c/coreboot/+/55733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599 Gerrit-Change-Number: 55733 Gerrit-PatchSet: 6 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/intel/adlrvp: Remove ASL code and enable dynamic SSDT creation for...
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55526 ) Change subject: mb/intel/adlrvp: Remove ASL code and enable dynamic SSDT creation for camera ACPI ...................................................................... mb/intel/adlrvp: Remove ASL code and enable dynamic SSDT creation for camera ACPI This change updates device tree to enable SSDT generation for world facing camera and user facing camera for ADLRVP. Also reverts DSDT changes related to both camera. TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl Compared SSDT with this patch against DSDT without this patch, they are same Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/intel/adlrvp/Kconfig.name D src/mainboard/intel/adlrvp/acpi/mipi_camera.asl M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/dsdt.asl 4 files changed, 104 insertions(+), 506 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name index 743253e..c05074b 100644 --- a/src/mainboard/intel/adlrvp/Kconfig.name +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -2,10 +2,14 @@ bool "Alderlake-P RVP" select DRIVERS_UART_8250IO select MAINBOARD_USES_IFD_EC_REGION + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_INTEL_ADLRVP_P_EXT_EC bool "Alderlake-P RVP with Chrome EC" select INTEL_LPSS_UART_FOR_CONSOLE + select DRIVERS_INTEL_MIPI_CAMERA + select SOC_INTEL_COMMON_BLOCK_IPU config BOARD_INTEL_ADLRVP_M bool "Alderlake-M RVP" diff --git a/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl b/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl deleted file mode 100644 index b8bd6dc..0000000 --- a/src/mainboard/intel/adlrvp/acpi/mipi_camera.asl +++ /dev/null @@ -1,499 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Scope (\_SB.PCI0.IPU0) -{ - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x02) - { - Package (0x02) - { - "port0", - "PRT0" - }, - Package (0x02) - { - "port1", - "PRT1" - } - } - }) - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - 2 - } - }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - Name (PRT1, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - One - } - }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP10" - } - } - }) -} - -Scope (\_SB.PCI0.IPU0) -{ - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - Package (0x02) - { - "clock-lanes", - Zero - }, - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02, - } - }, - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - ^I2C5.CAM1, - Zero, - Zero - } - } - } - }) - Name (EP10, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x04) - { - Package (0x02) - { - "endpoint", - Zero - }, - Package (0x02) - { - "clock-lanes", - Zero - }, - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02, - } - }, - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - ^I2C1.CAM0, - Zero, - Zero - } - } - } - }) -} - -Scope (\_SB.PCI0.I2C1) -{ - PowerResource (RCPR, 0x00, 0x0000) - { - Name (STA, Zero) - Method (_ON, 0, Serialized) /* Rear camera_ON_: Power On */ - { - If ((STA == Zero)) - { - /* Enable IMG_CLK */ - MCON(0,1) /* Clock 0, 19.2MHz */ - /* Pull PWREN high */ - STXS(GPP_B23) - Sleep(2) /* reset pulse width */ - /* Pull RST low */ - CTXS(GPP_R5) - Sleep(1) /* t2 */ - /* Pull RST high */ - STXS(GPP_R5) - Sleep(1) /* t2 */ - Store(1,STA) - } - } - Method (_OFF, 0, Serialized) /* Rear camera _OFF: Power Off */ - { - If ((STA == One)) - { - /* Disable IMG_CLK */ - Sleep(1) /* t0+t1 */ - MCOF(0) /* Clock 0 */ - /* Pull RST low */ - CTXS(GPP_R5) - /* Pull PWREN low */ - CTXS(GPP_B23) - Store(0,STA) - } - } - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (STA) - } - } - Device (CAM0) - { - Name (_HID, "OVTI5675") /* _HID: Hardware ID */ - Name (_UID, Zero) /* _UID: Unique ID */ - Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C1", - 0x00, ResourceConsumer, , - ) - }) - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - RCPR - }) - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - RCPR - }) - Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port0", - "PRT0" - } - }, - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x02) - { - Package (0x02) - { - "clock-frequency", - 0x0124F800 - }, - Package (0x02) - { - "lens-focus", - Package (0x01) - { - VCM0 - } - } - } - }) - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x05) - { - Package (0x02) - { - "endpoint", - Zero - }, - Package (0x02) - { - "clock-lanes", - Zero - }, - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02 - } - }, - Package (0x02) - { - "link-frequencies", - Package (0x01) - { - 0x1AD27480 - } - }, - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - IPU0, - Zero, - Zero - } - } - } - }) - } - Device (VCM0) - { - Name (_HID, "PRP0001") /* _HID: Hardware ID */ - Name (_UID, 0x03) /* _UID: Unique ID */ - Name (_DDN, "DW AF DAC") /* _DDN: DOS Device Name */ - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C1", - 0x00, ResourceConsumer, , - ) - }) - Name (_DEP, Package (0x01) /* _DEP: Dependencies */ - { - CAM0 - }) - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - RCPR - }) - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - RCPR - }) - Name (_DSD, Package (0x02) /* _DSD: Device-Specific Data */ - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "compatible", - "dongwoon,dw9714" - } - } - }) - } -} - -Scope (\_SB.PCI0.I2C5) -{ - PowerResource (FCPR, 0x00, 0x0000) - { - Name (STA, Zero) - Method (_ON, 0, Serialized) /* Front camera_ON_: Power On */ - { - If ((STA == Zero)) - { - /* Enable IMG_CLK */ - MCON(1,1) /* Clock 1, 19.2MHz */ - /* Pull PWREN high */ - STXS(GPP_E16) - Sleep(2) /* reset pulse width */ - /* Pull RST low */ - CTXS(GPP_E15) - Sleep(1) /* t2 */ - /* Pull RST high */ - STXS(GPP_E15) - Sleep(1) /* t2 */ - Store(1,STA) - } - } - Method (_OFF, 0, Serialized) /* Front camera_OFF_: Power Off */ - { - If ((STA == One)) - { - /* Disable IMG_CLK */ - Sleep(1) /* t0+t1 */ - MCOF(1) /* Clock 1 */ - /* Pull RST low */ - CTXS(GPP_E15) - /* Pull PWREN low */ - CTXS(GPP_E16) - Store(0,STA) - } - } - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (STA) - } - } - Device (CAM1) - { - Name (_HID, "OVTI5675") /* _HID: Hardware ID */ - Name (_UID, Zero) /* _UID: Unique ID */ - Name (_DDN, "Ov 5675 Camera") /* _DDN: DOS Device Name */ - Method (_STA, 0, NotSerialized) /* _STA: Status */ - { - Return (0x0F) - } - Name (_CRS, ResourceTemplate () /* _CRS: Current Resource Settings */ - { - I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, - AddressingMode7Bit, "\\_SB.PCI0.I2C5", - 0x00, ResourceConsumer, , - ) - }) - Name (_PR0, Package (0x01) /* _PR0: Power Resources for D0 */ - { - FCPR - }) - Name (_PR3, Package (0x01) /* _PR3: Power Resources for D3hot */ - { - FCPR - }) - Name (_DSD, Package (0x04) /* _DSD: Device-Specific Data */ - { - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "port0", - "PRT0" - } - }, - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "clock-frequency", - 0x0124F800 - } - } - }) - Name (PRT0, Package (0x04) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x01) - { - Package (0x02) - { - "port", - Zero - } - }, - ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), - Package (0x01) - { - Package (0x02) - { - "endpoint0", - "EP00" - } - } - }) - Name (EP00, Package (0x02) - { - ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package (0x05) - { - Package (0x02) - { - "endpoint", - Zero - }, - Package (0x02) - { - "clock-lanes", - Zero - }, - Package (0x02) - { - "data-lanes", - Package (0x02) - { - One, - 0x02 - } - }, - Package (0x02) - { - "link-frequencies", - Package (0x01) - { - 0x1AD27480 - } - }, - Package (0x02) - { - "remote-endpoint", - Package (0x03) - { - IPU0, - One, - Zero - } - } - } - }) - } -} diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index affa6f8..8c823cd 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -312,7 +312,21 @@ device generic 0 on end end end - device ref ipu on end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1"" + register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 0 on end + end + end device ref pcie4_0 on end device ref pcie4_1 on end device ref tbt_pcie_rp0 on end @@ -344,12 +358,95 @@ end end device ref i2c0 on end - device ref i2c1 on end + device ref i2c1 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM0"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "ssdb.vcm_type" = "0x0C" + register "vcm_name" = ""VCM0"" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + chip drivers/intel/mipi_camera + register "acpi_uid" = "3" + register "acpi_name" = ""VCM0"" + register "chip_name" = ""DW AF VCM"" + register "device_type" = "INTEL_ACPI_CAMERA_VCM" + + register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC"" + register "vcm_compat" = ""dongwoon,dw9714"" + + device i2c 0C on end + end + end device ref i2c2 on end device ref i2c3 on end device ref heci1 on end device ref sata on end - device ref i2c5 on end + device ref i2c5 on + chip drivers/intel/mipi_camera + register "acpi_hid" = ""OVTI5675"" + register "acpi_uid" = "0" + register "acpi_name" = ""CAM1"" + register "chip_name" = ""Ov 5675 Camera"" + register "device_type" = "INTEL_ACPI_CAMERA_SENSOR" + + register "ssdb.lanes_used" = "2" + register "num_freq_entries" = "1" + register "link_freq[0]" = "450000000" + register "remote_name" = ""IPU0"" + + register "has_power_resource" = "1" + #Controls + register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 + register "clk_panel.clks[0].freq" = "1" #19.2 Mhz + register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable + register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset + + #_ON + register "on_seq.ops_cnt" = "4" + register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)" + register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)" + register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)" + register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)" + + #_OFF + register "off_seq.ops_cnt" = "3" + register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)" + register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" + register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" + + device i2c 36 on end + end + end device ref pcie_rp1 on end device ref pcie_rp3 on end # W/A to FSP issue device ref pcie_rp4 on end # W/A to FSP issue diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl index 6a4f512..4b41b22 100644 --- a/src/mainboard/intel/adlrvp/dsdt.asl +++ b/src/mainboard/intel/adlrvp/dsdt.asl @@ -25,12 +25,8 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> #include <soc/intel/alderlake/acpi/tcss.asl> - #include <soc/intel/common/block/acpi/acpi/ipu.asl> } - /* Camera */ - #include <acpi/mipi_camera.asl> - #if CONFIG(EC_GOOGLE_CHROMEEC) /* Chrome OS Embedded Controller */ Scope (\_SB.PCI0.LPCB) -- To view, visit https://review.coreboot.org/c/coreboot/+/55526 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f Gerrit-Change-Number: 55526 Gerrit-PatchSet: 18 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: util/board_status: Do not display grep message
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56056 ) Change subject: util/board_status: Do not display grep message ...................................................................... util/board_status: Do not display grep message Redirect stdout and stderr from grep to check for unknown timestamps, when no timestamps are stored, which is already logged earlier. Failed to run "/root/coreboot/util/cbmem/cbmem -t", ignoring Getting remote dmesg grep: /tmp/coreboot_board_status.dXmbUIBP/emulation/qemu-i440fx/4.14-876-gdb28040ee1/2021-07-02T23_14_33Z/coreboot_timestamps.txt: No such file or directory Change-Id: Ib5400d4bd17e957b4cc1bf75bbd332d60ad226f5 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56056 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/board_status/board_status.sh 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 292bffa..f5254f1 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -501,7 +501,7 @@ exit $EXIT_FAILURE fi -if [ $(grep -- unknown "${tmpdir}/${results}/coreboot_timestamps.txt") ]; then +if [ $(grep -- unknown "${tmpdir}/${results}/coreboot_timestamps.txt" >/dev/null 2>&1) ]; then echo "Unknown timestamps found in 'coreboot_timestamps.txt'." \ "Please rebuild the 'cbmem' utility and try again." exit $EXIT_FAILURE -- To view, visit https://review.coreboot.org/c/coreboot/+/56056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5400d4bd17e957b4cc1bf75bbd332d60ad226f5 Gerrit-Change-Number: 56056 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/dedede: Fix the pointer/address used in memcpy
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56046 ) Change subject: mb/google/dedede: Fix the pointer/address used in memcpy ...................................................................... mb/google/dedede: Fix the pointer/address used in memcpy The caller is already passing the address to the required LTE reset and enable GPIO. During memcpy, the address to that pointer is used which will lead to copying undefined data. Fix the pointer/address used in memcpy. BUG=None BRANCH=dedede TEST=Build Kracko, Drawcia and Metaknight mainboards which use this function. Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Found-by: Coverity CID 1458053, 1458054. Reviewed-on: https://review.coreboot.org/c/coreboot/+/56046 Reviewed-by: Evan Green <evgreen(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/baseboard/ramstage.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Evan Green: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c index 136fe13..aedaa3f 100644 --- a/src/mainboard/google/dedede/variants/baseboard/ramstage.c +++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c @@ -35,10 +35,10 @@ config->type = UPC_TYPE_INTERNAL; if (port->path.usb.port_type == LTE_USB_PORT_TYPE) { config->has_power_resource = 1; - memcpy(&config->reset_gpio, &lte_reset_gpio, + memcpy(&config->reset_gpio, lte_reset_gpio, sizeof(config->reset_gpio)); config->reset_off_delay_ms = 20; - memcpy(&config->enable_gpio, &lte_enable_gpio, + memcpy(&config->enable_gpio, lte_enable_gpio, sizeof(config->enable_gpio)); config->enable_delay_ms = 20; } -- To view, visit https://review.coreboot.org/c/coreboot/+/56046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79d6d9af03acd59ab5e1cd7df97bf451011dfeaa Gerrit-Change-Number: 56046 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Henry Sun <henrysun(a)google.com> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: timestamp,vc/google/chromeos/cr50: Add timestamp for enable update
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55402 ) Change subject: timestamp,vc/google/chromeos/cr50: Add timestamp for enable update ...................................................................... timestamp,vc/google/chromeos/cr50: Add timestamp for enable update cr50_enable_update takes a non-trivial amount of time. TEST=Boot guybrush and dump timestamps 553:started TPM enable update 3,615,156 (444) 554:finished TPM enable update 3,632,810 (17,654) Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I522d0638a4a6ae9624965e49b47bca8743c3206c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55402 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/vendorcode/google/chromeos/cr50_enable_update.c 2 files changed, 10 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 09985b7..300aa2a 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -77,6 +77,8 @@ TS_START_COPYVPD = 550, TS_END_COPYVPD_RO = 551, TS_END_COPYVPD_RW = 552, + TS_START_TPM_ENABLE_UPDATE = 553, + TS_END_TPM_ENABLE_UPDATE = 554, /* 900-940 reserved for vendorcode extensions (900-940: AMD) */ TS_AGESA_INIT_RESET_START = 900, @@ -204,6 +206,8 @@ { TS_END_TPMPCR, "finished TPM PCR extend" }, { TS_START_TPMLOCK, "starting locking TPM" }, { TS_END_TPMLOCK, "finished locking TPM" }, + { TS_START_TPM_ENABLE_UPDATE, "started TPM enable update" }, + { TS_END_TPM_ENABLE_UPDATE, "finished TPM enable update" }, { TS_START_COPYVPD, "starting to load Chrome OS VPD" }, { TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" }, diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c index e30fe2a..a8243e1 100644 --- a/src/vendorcode/google/chromeos/cr50_enable_update.c +++ b/src/vendorcode/google/chromeos/cr50_enable_update.c @@ -9,6 +9,7 @@ #include <vb2_api.h> #include <security/vboot/vboot_common.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <timestamp.h> #define CR50_RESET_DELAY_MS 1000 @@ -89,6 +90,8 @@ return; } + timestamp_add_now(TS_START_TPM_ENABLE_UPDATE); + /* Reboot in 1000 ms if necessary. */ ret = tlcl_cr50_enable_update(CR50_RESET_DELAY_MS, &num_restored_headers); @@ -115,8 +118,10 @@ * If the Cr50 doesn't requires a reset, continue booting. */ cr50_reset_reqd = cr50_is_reset_needed(); - if (!cr50_reset_reqd) + if (!cr50_reset_reqd) { + timestamp_add_now(TS_END_TPM_ENABLE_UPDATE); return; + } printk(BIOS_INFO, "Waiting for CR50 reset to enable TPM.\n"); elog_add_event(ELOG_TYPE_CR50_NEED_RESET); -- To view, visit https://review.coreboot.org/c/coreboot/+/55402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I522d0638a4a6ae9624965e49b47bca8743c3206c Gerrit-Change-Number: 55402 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: device/resource_allocator_v4: Only highlight log message with ===
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56045 ) Change subject: device/resource_allocator_v4: Only highlight log message with === ...................................................................... device/resource_allocator_v4: Only highlight log message with === Currently, four instead of three = are used in one log message. Done reading resources. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === As the ending mark is `===` change it to `===` in the beginning. Done reading resources. === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === Change-Id: I40c3876e1f895b7f9771479234c9529cca2b97ba Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56045 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/resource_allocator_v4.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 3a11032..b94c295 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -670,7 +670,7 @@ post_log_path(child); /* Pass 1 - Gather requirements. */ - printk(BIOS_INFO, "==== Resource allocator: %s - Pass 1 (gathering requirements) ===\n", + printk(BIOS_INFO, "=== Resource allocator: %s - Pass 1 (gathering requirements) ===\n", dev_path(child)); compute_domain_resources(child); -- To view, visit https://review.coreboot.org/c/coreboot/+/56045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40c3876e1f895b7f9771479234c9529cca2b97ba Gerrit-Change-Number: 56045 Gerrit-PatchSet: 2 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit July 2021