coreboot-gerrit July 2021

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Change in coreboot[master]: sb/intel/i82801gx: Prepare for x86_64
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56020 ) Change subject: sb/intel/i82801gx: Prepare for x86_64 ...................................................................... sb/intel/i82801gx: Prepare for x86_64 Do the usual int conversions. TESTED: BUILD_TIMELESS=1 produces identical image on foxconn/g41m. Change-Id: Idebfe4669854b307bee653df6d93e46ae3f39dec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56020 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/i82801gx/azalia.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 3ace204..fde06b4 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -8,6 +8,7 @@ #include <device/mmio.h> #include <delay.h> #include <device/azalia_device.h> +#include <stdint.h> #include "chip.h" #include "i82801gx.h" @@ -192,7 +193,7 @@ // NOTE this will break as soon as the Azalia get's a bar above 4G. // Is there anything we can do about it? base = res2mmio(res, 0, 0); - printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); + printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)(uintptr_t)base); codec_mask = codec_detect(base); if (codec_mask) { -- To view, visit https://review.coreboot.org/c/coreboot/+/56020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idebfe4669854b307bee653df6d93e46ae3f39dec Gerrit-Change-Number: 56020 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Use write32p and read32p
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56029 ) Change subject: nb/intel/x4x: Use write32p and read32p ...................................................................... nb/intel/x4x: Use write32p and read32p This removes the need for type conversions all over the place. Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56029 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c 3 files changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index cda503e..e4cc888 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -170,13 +170,13 @@ if ((count1 % 16) == 0) mchbar_write32(0xf90, 1); const u32 pattern = write_training_schedule[count1]; - write32((u32 *)(uintptr_t)address + 8 * count1, pattern); - write32((u32 *)(uintptr_t)address + 8 * count1 + 4, pattern); + write32p(address + 8 * count1, pattern); + write32p(address + 8 * count1 + 4, pattern); } const u32 good = write_training_schedule[count]; - write32(&data[0], read32((u32 *)(uintptr_t)address + 8 * count)); - write32(&data[4], read32((u32 *)(uintptr_t)address + 8 * count + 4)); + write32(&data[0], read32p(address + 8 * count)); + write32(&data[4], read32p(address + 8 * count + 4)); FOR_EACH_BYTELANE(lane) { u8 expected = (good >> ((lane % 4) * 8)) & 0xff; if (data[lane] != expected) @@ -353,8 +353,8 @@ address = test_address(channel, rank); for (i = 0; i < RT_PATTERN_SIZE; i++) { const u32 good = read_training_schedule[i]; - write32(&data[0], read32((u32 *)(uintptr_t)address + i * 8)); - write32(&data[4], read32((u32 *)(uintptr_t)address + i * 8 + 4)); + write32(&data[0], read32p(address + i * 8)); + write32(&data[4], read32p(address + i * 8 + 4)); FOR_EACH_BYTELANE(lane) { if (data[lane] != (good & 0xff)) @@ -442,8 +442,8 @@ address = test_address(channel, rank); for (i = 0; i < RT_PATTERN_SIZE; i++) { content = read_training_schedule[i]; - write32((u32 *)(uintptr_t)address + 8 * i, content); - write32((u32 *)(uintptr_t)address + 8 * i + 4, content); + write32p(address + 8 * i, content); + write32p(address + 8 * i + 4, content); } } @@ -617,8 +617,8 @@ memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0])); for (samples = 0; samples < N_SAMPLES; samples++) { - write32((u32 *)(uintptr_t)address, 0x12341234); - write32((u32 *)(uintptr_t)address + 4, 0x12341234); + write32p(address, 0x12341234); + write32p(address + 4, 0x12341234); udelay(5); FOR_EACH_BYTELANE(lane) { u8 dq_high = (mchbar_read8(0x561 + 0x400 * channel diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 126a44b..d19a83a 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1283,7 +1283,7 @@ } data32 <<= 3; - read32((void *)(uintptr_t)(data32 | addr)); + read32p(data32 | addr); udelay(10); mchbar_clrsetbits8(0x271, 0x3e, NORMALOP_CMD); mchbar_clrsetbits8(0x671, 0x3e, NORMALOP_CMD); @@ -2090,7 +2090,7 @@ if (s->boot_path == BOOT_PATH_NORMAL) { FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) - read32((u32 *)(uintptr_t)(test_address(ch, r) | 0x800000 | (bank << 12))); + read32p(test_address(ch, r) | 0x800000 | (bank << 12)); } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 5bb395a..1f8be79 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -38,7 +38,7 @@ } mfence(); /* Read strobe */ - read32((void *)(uintptr_t)addr); + read32p(addr); mfence(); return mchbar_read8(sample_offset) >> 6 & 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/56029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c Gerrit-Change-Number: 56029 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/x4x: Prepare for x86_64 support
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56019 ) Change subject: nb/intel/x4x: Prepare for x86_64 support ...................................................................... nb/intel/x4x: Prepare for x86_64 support Do the usual type conversions TESTED: Same image with BUILD_TIMELESS=1 Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56019 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c 4 files changed, 16 insertions(+), 14 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 854e143..cda503e 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> +#include <stdint.h> #include <string.h> #include <types.h> #include "raminit.h" @@ -169,13 +170,13 @@ if ((count1 % 16) == 0) mchbar_write32(0xf90, 1); const u32 pattern = write_training_schedule[count1]; - write32((u32 *)address + 8 * count1, pattern); - write32((u32 *)address + 8 * count1 + 4, pattern); + write32((u32 *)(uintptr_t)address + 8 * count1, pattern); + write32((u32 *)(uintptr_t)address + 8 * count1 + 4, pattern); } const u32 good = write_training_schedule[count]; - write32(&data[0], read32((u32 *)address + 8 * count)); - write32(&data[4], read32((u32 *)address + 8 * count + 4)); + write32(&data[0], read32((u32 *)(uintptr_t)address + 8 * count)); + write32(&data[4], read32((u32 *)(uintptr_t)address + 8 * count + 4)); FOR_EACH_BYTELANE(lane) { u8 expected = (good >> ((lane % 4) * 8)) & 0xff; if (data[lane] != expected) @@ -352,8 +353,8 @@ address = test_address(channel, rank); for (i = 0; i < RT_PATTERN_SIZE; i++) { const u32 good = read_training_schedule[i]; - write32(&data[0], read32((u32 *)address + i * 8)); - write32(&data[4], read32((u32 *)address + i * 8 + 4)); + write32(&data[0], read32((u32 *)(uintptr_t)address + i * 8)); + write32(&data[4], read32((u32 *)(uintptr_t)address + i * 8 + 4)); FOR_EACH_BYTELANE(lane) { if (data[lane] != (good & 0xff)) @@ -441,8 +442,8 @@ address = test_address(channel, rank); for (i = 0; i < RT_PATTERN_SIZE; i++) { content = read_training_schedule[i]; - write32((u32 *)address + 8 * i, content); - write32((u32 *)address + 8 * i + 4, content); + write32((u32 *)(uintptr_t)address + 8 * i, content); + write32((u32 *)(uintptr_t)address + 8 * i + 4, content); } } @@ -616,8 +617,8 @@ memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0])); for (samples = 0; samples < N_SAMPLES; samples++) { - write32((u32 *)address, 0x12341234); - write32((u32 *)address + 4, 0x12341234); + write32((u32 *)(uintptr_t)address, 0x12341234); + write32((u32 *)(uintptr_t)address + 4, 0x12341234); udelay(5); FOR_EACH_BYTELANE(lane) { u8 dq_high = (mchbar_read8(0x561 + 0x400 * channel diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 2245f96..c92fd45 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -72,7 +72,7 @@ /* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tomk as unusable */ - delta_cbmem = tomk - ((uint32_t)cbmem_top() >> 10); + delta_cbmem = tomk - ((uint32_t)(uintptr_t)cbmem_top() >> 10); tomk -= delta_cbmem; uma_sizek += delta_cbmem; diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 2d70b96..126a44b 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1283,7 +1283,7 @@ } data32 <<= 3; - read32((void *)((data32 | addr))); + read32((void *)(uintptr_t)(data32 | addr)); udelay(10); mchbar_clrsetbits8(0x271, 0x3e, NORMALOP_CMD); mchbar_clrsetbits8(0x671, 0x3e, NORMALOP_CMD); @@ -2090,7 +2090,7 @@ if (s->boot_path == BOOT_PATH_NORMAL) { FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { for (bank = 0; bank < 4; bank++) - read32((u32 *)(test_address(ch, r) | 0x800000 | (bank << 12))); + read32((u32 *)(uintptr_t)(test_address(ch, r) | 0x800000 | (bank << 12))); } } printk(BIOS_DEBUG, "Done dummy reads\n"); diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 9e58ef3..5bb395a 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <console/console.h> #include <delay.h> +#include <stdint.h> #include "raminit.h" #include "x4x.h" @@ -37,7 +38,7 @@ } mfence(); /* Read strobe */ - read32((u32 *)addr); + read32((void *)(uintptr_t)addr); mfence(); return mchbar_read8(sample_offset) >> 6 & 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/56019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84 Gerrit-Change-Number: 56019 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/car/p4-netburst: Prepare for x86_64
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56018 ) Change subject: cpu/intel/car/p4-netburst: Prepare for x86_64 ...................................................................... cpu/intel/car/p4-netburst: Prepare for x86_64 Use proper car symbols. Change-Id: I169fd6020e5b81da66dbe4fe83ba446eedc882e9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56018 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/car/cache_as_ram_symbols.inc M src/cpu/intel/car/p4-netburst/cache_as_ram.S 2 files changed, 11 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc index 857e039..2d2f4bd 100644 --- a/src/cpu/intel/car/cache_as_ram_symbols.inc +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -18,3 +18,6 @@ car_mtrr_start: .uintptr_t _car_mtrr_start + +xip_mtrr_mask: +.uintptr_t _xip_mtrr_mask diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 103d9e9..71ec9e3 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -11,6 +11,8 @@ .section .init .global bootblock_pre_c_entry +#include <cpu/intel/car/cache_as_ram_symbols.inc> + .code32 _cache_as_ram_setup: @@ -212,7 +214,7 @@ /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx - movl $_car_mtrr_start, %eax + movl car_mtrr_start, %eax orl $MTRR_TYPE_WRBACK, %eax xorl %edx, %edx wrmsr @@ -220,7 +222,7 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + movl car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -272,12 +274,12 @@ /* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $_rom_mtrr_base, %eax + movl rom_mtrr_base, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_rom_mtrr_mask, %eax + movl rom_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -324,12 +326,12 @@ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx movl $_program, %eax - andl $_xip_mtrr_mask, %eax + andl xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_xip_mtrr_mask, %eax + movl xip_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr -- To view, visit https://review.coreboot.org/c/coreboot/+/56018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I169fd6020e5b81da66dbe4fe83ba446eedc882e9 Gerrit-Change-Number: 56018 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Update the FIVR configurations
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55703 ) Change subject: mb/intel/adlrvp: Update the FIVR configurations ...................................................................... mb/intel/adlrvp: Update the FIVR configurations This patch sets the optimized FIVR configuration for adlrvp cutomized based on the pnp measurements to achieve the better power savings in sleep states. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 states. * Update the supported voltage states. * Set the ICC max to 500mA for v1p05 and vnn. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/devicetree.cb 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index be26592..affa6f8 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -199,6 +199,21 @@ }, }" + # FIVR configurations + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 1050, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + device domain 0 on device ref pcie5 on end device ref igpu on end -- To view, visit https://review.coreboot.org/c/coreboot/+/55703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19 Gerrit-Change-Number: 55703 Gerrit-PatchSet: 8 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add support to update the FIVR configs
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55702 ) Change subject: soc/intel/alderlake: Add support to update the FIVR configs ...................................................................... soc/intel/alderlake: Add support to update the FIVR configs This patch adds the supports to update the optimal FIVR configurations for external voltage rails via devicetree. Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55702 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 89 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 58daa25..709ab3c 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -43,6 +43,35 @@ DDI_ENABLE_HPD = 1 << 1, }; +/* + * Enable External V1P05/Vnn/VnnSx Rail in: BIT0:S0i1/S0i2, + * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 + */ +enum fivr_enable_states { + FIVR_ENABLE_S0i1_S0i2 = BIT(0), + FIVR_ENABLE_S0i3 = BIT(1), + FIVR_ENABLE_S3 = BIT(2), + FIVR_ENABLE_S4 = BIT(3), + FIVR_ENABLE_S5 = BIT(4), +}; + +/* + * Enable the following for External V1p05 rail + * BIT0: Retention active switch support + * BIT1: Normal Active voltage supported + * BIT2: Minimum active voltage supported + * BIT3: Minimum Retention voltage supported + */ +enum fivr_voltage_supported { + FIVR_RET_ACTIVE_SWITCH_SUPPORT = BIT(0), + FIVR_VOLTAGE_NORMAL = BIT(1), + FIVR_VOLTAGE_MIN_ACTIVE = BIT(2), + FIVR_VOLTAGE_MIN_RETENTION = BIT(3), +}; + +#define FIVR_ENABLE_ALL_SX (FIVR_ENABLE_S0i1_S0i2 | FIVR_ENABLE_S0i3 | \ + FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5) + struct soc_intel_alderlake_config { /* Common struct containing soc config data required by common code */ @@ -324,6 +353,26 @@ ISA_SERIAL_BASE_ADDR_3F8, ISA_SERIAL_BASE_ADDR_2F8, } IsaSerialUartBase; + + /* structure containing various settings for PCH FIVRs */ + struct { + bool configure_ext_fivr; + enum fivr_enable_states v1p05_enable_bitmap; + enum fivr_enable_states vnn_enable_bitmap; + enum fivr_enable_states vnn_sx_enable_bitmap; + enum fivr_voltage_supported v1p05_supported_voltage_bitmap; + enum fivr_voltage_supported vnn_supported_voltage_bitmap; + /* V1p05 Rail Voltage in mv */ + int v1p05_voltage_mv; + /* Vnn Rail Voltage in mv */ + int vnn_voltage_mv; + /* VnnSx Rail Voltage in mv */ + int vnn_sx_voltage_mv; + /* External Icc Max for V1p05 rail in mA */ + int v1p05_icc_max_ma; + /* External Icc Max for VnnSx rail in mA */ + int vnn_icc_max_ma; + } ext_fivr_settings; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index e29133e..5b0d631 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -549,6 +549,45 @@ printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); } +static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + /* PCH FIVR settings override */ + if (!config->ext_fivr_settings.configure_ext_fivr) + return; + + s_cfg->PchFivrExtV1p05RailEnabledStates = + config->ext_fivr_settings.v1p05_enable_bitmap; + + s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = + config->ext_fivr_settings.v1p05_supported_voltage_bitmap; + + s_cfg->PchFivrExtVnnRailEnabledStates = + config->ext_fivr_settings.vnn_enable_bitmap; + + s_cfg->PchFivrExtVnnRailSupportedVoltageStates = + config->ext_fivr_settings.vnn_supported_voltage_bitmap; + + s_cfg->PchFivrExtVnnRailSxEnabledStates = + config->ext_fivr_settings.vnn_enable_bitmap; + + /* Convert the voltages to increments of 2.5mv */ + s_cfg->PchFivrExtV1p05RailVoltage = + (config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25; + + s_cfg->PchFivrExtVnnRailVoltage = + (config->ext_fivr_settings.vnn_voltage_mv * 10) / 25; + + s_cfg->PchFivrExtVnnRailSxVoltage = + (config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25); + + s_cfg->PchFivrExtV1p05RailIccMaximum = + config->ext_fivr_settings.v1p05_icc_max_ma; + + s_cfg->PchFivrExtVnnRailIccMaximum = + config->ext_fivr_settings.vnn_icc_max_ma; +} + static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg) { /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ @@ -583,6 +622,7 @@ fill_fsps_pcie_params, fill_fsps_misc_power_params, fill_fsps_irq_params, + fill_fsps_fivr_params, }; for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) -- To view, visit https://review.coreboot.org/c/coreboot/+/55702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 Gerrit-Change-Number: 55702 Gerrit-PatchSet: 8 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/brya0: Enable Crashlog
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55326 ) Change subject: mb/google/brya/brya0: Enable Crashlog ...................................................................... mb/google/brya/brya0: Enable Crashlog brya0 is a reference and development platform, therefore it would be helpful to have Crashlog enabled. Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55326 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 7562fb0..f63e46f 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -7,6 +7,7 @@ select DRIVERS_GENESYSLOGIC_GL9755 select DRIVERS_INTEL_MIPI_CAMERA select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_CRASHLOG config BOARD_GOOGLE_PRIMUS bool "-> Primus" -- To view, visit https://review.coreboot.org/c/coreboot/+/55326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I936e73e808e0a05e8b7822cddbb5ee3fa7dee13e Gerrit-Change-Number: 55326 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Azhar Shaikh <azhar.shaikh(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55988 ) Change subject: mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask ...................................................................... mb/google/brya: Add HANG_DETECT host event to EC S0ix wake mask The brya EC supports S0ix hang detection, but it was not enabled in coreboot as well, masking that event out of S0ix, therefore add it in to the EC S0ix wake mask. TEST=After EC prints "Warning: Detected sleep hang! Waking host up!", the host actually wakes up Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55988 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h index 3d5dde8..c76274e 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/ec.h @@ -45,7 +45,9 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) -#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) +#define MAINBOARD_EC_S0IX_WAKE_EVENTS \ + (MAINBOARD_EC_S3_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_HANG_DETECT)) /* Log EC wake events plus EC shutdown events */ #define MAINBOARD_EC_LOG_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ -- To view, visit https://review.coreboot.org/c/coreboot/+/55988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c699114abcd9a045a41858c731e4b6fe99d3000 Gerrit-Change-Number: 55988 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Boris Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/cret: Disable SDCard controller
by Patrick Georgi (Code Review) 05 Jul '21

05 Jul '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55935 ) Change subject: mb/google/dedede/var/cret: Disable SDCard controller ...................................................................... mb/google/dedede/var/cret: Disable SDCard controller Cret doesn't support SDCard. Disable SDCard contorller for Cret. BUG=b:191232222 TEST=Build and boot to check lspci Cq-Depend: chromium:2993724 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I889f0545883aa75813dd91dc3e6a4dcfc246687f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55935 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/cret/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index be84c79..8b26d5d 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -100,6 +100,7 @@ end end end # USB xHCI + device pci 14.5 off end # SDCard device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/55935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I889f0545883aa75813dd91dc3e6a4dcfc246687f Gerrit-Change-Number: 55935 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ben Kao <ben.kao(a)intel.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: configs: Explicitly specify vendor and mainboard
by Angel Pons (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Arthur Heymans, Werner Zeh, Patrick Rudolph. Hello Nico Huber, Tim Wawrzynczak, Arthur Heymans, Werner Zeh, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56079 to review the following change. Change subject: configs: Explicitly specify vendor and mainboard ...................................................................... configs: Explicitly specify vendor and mainboard Relying on the implicit defaults for these settings can cause issues in the future. For example, commit 8cc4c5a1e76c0c8aee3a14618c15d38e3bd2bd61 (config.dell_optiplex_9010_sff: Specify board model) was done to prevent a build failure when adding support for other Dell mainboards which make the default board change. Change-Id: Ie0da6254def8b38e9fb053fc7d530dfb46760861 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support M configs/config.emulation_qemu_aarch64_fit_support_timestamps M configs/config.emulation_qemu_riscv_rv64 M configs/config.emulation_qemu_x86_i440fx_asan M configs/config.emulation_qemu_x86_i440fx_debug M configs/config.emulation_qemu_x86_i440fx_noserial M configs/config.emulation_qemu_x86_i440fx_x86_64 M configs/config.emulation_qemu_x86_q35_smm_tseg M configs/config.facebook_fbg1701.mboot_vboot M configs/config.libretrend_lt1000 M configs/config.ocp_deltalake_cbnt M configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi M configs/config.up_squared.vboot_spi_flash_console 13 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/56079/1 diff --git a/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support b/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support index 951855e..1727cc7 100644 --- a/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support +++ b/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support @@ -1,4 +1,5 @@ CONFIG_VENDOR_CAVIUM=y +CONFIG_BOARD_CAVIUM_CN8100_SFF_EVB=y CONFIG_CAVIUM_BDK_VERBOSE_INIT=y CONFIG_CAVIUM_BDK_VERBOSE_DRAM=y CONFIG_CAVIUM_BDK_VERBOSE_DRAM_TEST=y diff --git a/configs/config.emulation_qemu_aarch64_fit_support_timestamps b/configs/config.emulation_qemu_aarch64_fit_support_timestamps index 7d0054c..2b5234a 100644 --- a/configs/config.emulation_qemu_aarch64_fit_support_timestamps +++ b/configs/config.emulation_qemu_aarch64_fit_support_timestamps @@ -1,3 +1,4 @@ +CONFIG_VENDOR_EMULATION=y CONFIG_COLLECT_TIMESTAMPS=y CONFIG_TIMESTAMPS_ON_CONSOLE=y CONFIG_MAINBOARD_VENDOR="Emulation" diff --git a/configs/config.emulation_qemu_riscv_rv64 b/configs/config.emulation_qemu_riscv_rv64 index d41963c..f5bce48 100644 --- a/configs/config.emulation_qemu_riscv_rv64 +++ b/configs/config.emulation_qemu_riscv_rv64 @@ -1,2 +1,3 @@ +CONFIG_VENDOR_EMULATION=y CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64=y CONFIG_RISCV_OPENSBI=y diff --git a/configs/config.emulation_qemu_x86_i440fx_asan b/configs/config.emulation_qemu_x86_i440fx_asan index a4b504e..3d7f059 100644 --- a/configs/config.emulation_qemu_x86_i440fx_asan +++ b/configs/config.emulation_qemu_x86_i440fx_asan @@ -1 +1,3 @@ +CONFIG_VENDOR_EMULATION=y +CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y CONFIG_ASAN=y diff --git a/configs/config.emulation_qemu_x86_i440fx_debug b/configs/config.emulation_qemu_x86_i440fx_debug index e39ff59..85f5499 100644 --- a/configs/config.emulation_qemu_x86_i440fx_debug +++ b/configs/config.emulation_qemu_x86_i440fx_debug @@ -1,3 +1,5 @@ +CONFIG_VENDOR_EMULATION=y +CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y CONFIG_GDB_STUB=y CONFIG_GDB_WAIT=y CONFIG_FATAL_ASSERTS=y diff --git a/configs/config.emulation_qemu_x86_i440fx_noserial b/configs/config.emulation_qemu_x86_i440fx_noserial index 2902d02..f71c0ae 100644 --- a/configs/config.emulation_qemu_x86_i440fx_noserial +++ b/configs/config.emulation_qemu_x86_i440fx_noserial @@ -1,3 +1,5 @@ +CONFIG_VENDOR_EMULATION=y +CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_POST_IO is not set # CONFIG_POST_DEVICE is not set diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64 index d31bbf2..7123646 100644 --- a/configs/config.emulation_qemu_x86_i440fx_x86_64 +++ b/configs/config.emulation_qemu_x86_i440fx_x86_64 @@ -1 +1,3 @@ +CONFIG_VENDOR_EMULATION=y +CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y CONFIG_USE_EXP_X86_64_SUPPORT=y diff --git a/configs/config.emulation_qemu_x86_q35_smm_tseg b/configs/config.emulation_qemu_x86_q35_smm_tseg index 6484c6c..6d64715 100644 --- a/configs/config.emulation_qemu_x86_q35_smm_tseg +++ b/configs/config.emulation_qemu_x86_q35_smm_tseg @@ -1,3 +1,4 @@ +CONFIG_VENDOR_EMULATION=y CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y CONFIG_CPU_QEMU_X86_PARALLEL_MP=y CONFIG_CPU_QEMU_X86_TSEG_SMM=y diff --git a/configs/config.facebook_fbg1701.mboot_vboot b/configs/config.facebook_fbg1701.mboot_vboot index 34d349a..08f0c70 100644 --- a/configs/config.facebook_fbg1701.mboot_vboot +++ b/configs/config.facebook_fbg1701.mboot_vboot @@ -1,4 +1,5 @@ CONFIG_VENDOR_FACEBOOK=y +CONFIG_BOARD_FACEBOOK_FBG1701=y CONFIG_ONBOARD_SAMSUNG_MEM=y CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y diff --git a/configs/config.libretrend_lt1000 b/configs/config.libretrend_lt1000 index 33159f1..0d4f543 100644 --- a/configs/config.libretrend_lt1000 +++ b/configs/config.libretrend_lt1000 @@ -1,4 +1,5 @@ CONFIG_VENDOR_LIBRETREND=y +CONFIG_BOARD_LIBRETREND_LT1000=y CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_TPM2=y diff --git a/configs/config.ocp_deltalake_cbnt b/configs/config.ocp_deltalake_cbnt index 4df1043..4e77566 100644 --- a/configs/config.ocp_deltalake_cbnt +++ b/configs/config.ocp_deltalake_cbnt @@ -1,4 +1,5 @@ CONFIG_VENDOR_OCP=y +CONFIG_BOARD_OCP_DELTALAKE=y CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/intel-sec-tools/testdata/fake_acm/biosacm_cbnt_fake.bin" CONFIG_INTEL_TXT_LOGGING=y CONFIG_INTEL_CBNT_SUPPORT=y diff --git a/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi index 09dfbe3..0861af3 100644 --- a/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi +++ b/configs/config.portwell_m107.debug_smmstore_oxpcie_em100spi @@ -8,6 +8,7 @@ # + EM100Pro SPI console # + Debug options CONFIG_VENDOR_PORTWELL=y +CONFIG_BOARD_PORTWELL_M107=y CONFIG_CONSOLE_POST=y # CONFIG_CONSOLE_SERIAL is not set CONFIG_ENABLE_BUILTIN_COM1=y diff --git a/configs/config.up_squared.vboot_spi_flash_console b/configs/config.up_squared.vboot_spi_flash_console index a537035..351e1ca 100644 --- a/configs/config.up_squared.vboot_spi_flash_console +++ b/configs/config.up_squared.vboot_spi_flash_console @@ -1,3 +1,4 @@ CONFIG_VENDOR_UP=y +CONFIG_BOARD_UP_SQUARED=y CONFIG_VBOOT=y CONFIG_CONSOLE_SPI_FLASH=y -- To view, visit https://review.coreboot.org/c/coreboot/+/56079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0da6254def8b38e9fb053fc7d530dfb46760861 Gerrit-Change-Number: 56079 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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2016

2015

2014

2013

coreboot-gerrit July 2021