coreboot-gerrit July 2021

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Change in coreboot[master]: supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0
by Jan Tatje (Code Review) 05 Jul '21

05 Jul '21

Jan Tatje has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56071 ) Change subject: supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0 ...................................................................... supermicro/x11-lga1151-series: Set SkipExtGfxScan = 0 Scan for external graphics, allows SeaBIOS to use the AST2400. Tested on X11SSH-LN4F. Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Signed-off-by: Jan Tatje <jan(a)jnt.io> --- M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/56071/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 1196629..650f625 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -1,7 +1,7 @@ chip soc/intel/skylake # FSP Configuration - register "SkipExtGfxScan" = "1" + register "SkipExtGfxScan" = "0" # SATA configuration register "SataSalpSupport" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/56071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce Gerrit-Change-Number: 56071 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/ifdtool: Add sklkbl to IFDv2 platforms
by Jan Tatje (Code Review) 05 Jul '21

05 Jul '21

Jan Tatje has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56070 ) Change subject: util/ifdtool: Add sklkbl to IFDv2 platforms ...................................................................... util/ifdtool: Add sklkbl to IFDv2 platforms Currently ifdtool breaks the descriptor because it treats it as IFDv1. This change adds it to the list of IFDv2 platforms. Fixes boot for X11SSH-LN4F. Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594 Signed-off-by: Jan Tatje <jan(a)jnt.io> --- M util/ifdtool/ifdtool.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/56070/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index e99cdec..b91c90c 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -205,9 +205,8 @@ return CHIPSET_9_SERIES_WILDCAT_POINT; } else if (nm == 6) { return CHIPSET_C620_SERIES_LEWISBURG; - } else { - return CHIPSET_100_200_SERIES_SUNRISE_POINT; } + return CHIPSET_PCH_UNKNOWN; } static enum ich_chipset ifd2_platform_to_chipset(const int pindex) @@ -219,6 +218,8 @@ return CHIPSET_N_SERIES_JASPER_LAKE; case PLATFORM_EHL: return CHIPSET_x6000_SERIES_ELKHART_LAKE; + case PLATFORM_SKLKBL: + return CHIPSET_100_200_SERIES_SUNRISE_POINT; case PLATFORM_CNL: return CHIPSET_300_SERIES_CANNON_POINT; case PLATFORM_TGL: @@ -250,6 +251,7 @@ PLATFORM_JSL, PLATFORM_EHL, PLATFORM_ADL, + PLATFORM_SKLKBL, }; unsigned int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/56070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f92b090e929336b5c18b442d1504ee1000f5594 Gerrit-Change-Number: 56070 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Tatje <jan(a)jnt.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/storo: Update DPTF parameters
by Tao Xia (Code Review) 05 Jul '21

05 Jul '21

Tao Xia has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56069 ) Change subject: mb/google/dedede/var/storo: Update DPTF parameters ...................................................................... mb/google/dedede/var/storo: Update DPTF parameters Update DPTF parameters from internal thermal team. BUG=b:180875582 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 --- M src/mainboard/google/dedede/variants/storo/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/56069/1 diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 7ddadbd..e824652 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -77,16 +77,16 @@ .tdp_pl2_override = 20, }" - register "tcc_offset" = "5" # TCC of 100C + register "tcc_offset" = "10" # TCC of 95C device domain 0 on device pci 04.0 on chip drivers/intel/dptf ## Passive Policy register "policies.passive" = "{ - [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 60, 3000), - [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 60, 3000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 60, 3000),}" + [0] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 67, 3000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 67, 3000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 67, 3000),}" ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), -- To view, visit https://review.coreboot.org/c/coreboot/+/56069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d87bc63a66ff38bc2f706d58b8537c052bf4594 Gerrit-Change-Number: 56069 Gerrit-PatchSet: 1 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/qualcomm/common/gpio: Define a macro for the gpio offset
by Ravi Kumar Bokka (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, Taniya Das. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55948 ) Change subject: soc/qualcomm/common/gpio: Define a macro for the gpio offset ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55948/comment/b16b379f_0ea960a6 PS1, Line 7: soc: common: gpio > Hi shelly, […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefdde8f8331cf1df2e88a2c8915aefb4fa091d65 Gerrit-Change-Number: 55948 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 05:35:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller
by Subrata Banik (Code Review) 05 Jul '21

05 Jul '21

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55998 ) Change subject: soc/intel/alderlake: Correct Bus and Device of Touch Host Controller ...................................................................... soc/intel/alderlake: Correct Bus and Device of Touch Host Controller Correct Bus and Device for THC0 and THC1 Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/include/soc/pci_devs.h 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 7085263..b05a1e9 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -79,8 +79,8 @@ device pci 0d.2 alias tcss_dma0 off end device pci 0d.3 alias tcss_dma1 off end device pci 0e.0 alias vmd off end - device pci 10.0 alias thc0 off end - device pci 10.1 alias thc1 off end + device pci 10.6 alias thc0 off end + device pci 10.7 alias thc1 off end device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end device pci 13.0 alias gspi3 off end diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index 730808d..1e8ecc7 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -79,10 +79,10 @@ /* PCH Devices */ #define MIN_PCH_SLOT PCH_DEV_SLOT_SIO0 #define PCH_DEV_SLOT_SIO0 0x10 -#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 0) -#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 1) -#define PCH_DEV_THC0 _PCH_DEV(SIO0, 0) -#define PCH_DEV_THC1 _PCH_DEV(SIO0, 1) +#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6) +#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7) +#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6) +#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7) #define PCH_DEV_SLOT_ISH 0x12 #define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/55998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Gerrit-Change-Number: 55998 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/elkhartlake: Expose FIVR config to mainboard
by Werner Zeh (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55861 ) Change subject: soc/intel/elkhartlake: Expose FIVR config to mainboard ...................................................................... Patch Set 3: Code-Review+1 (3 comments) File src/soc/intel/elkhartlake/chip.h: https://review.coreboot.org/c/coreboot/+/55861/comment/6078cf5c_1ed76b58 PS3, Line 77: I would align FIVR_VOLTAGE_MIN_RETENTION with FIVR_VOLTAGE_NORMAL as it belongs to the same bitmask. https://review.coreboot.org/c/coreboot/+/55861/comment/007c911b_78568caf PS3, Line 382: enum fivr_states v1p05_state_bitmap; : enum fivr_states vnn_state_bitmap; : enum fivr_states vnn_sx_state_bitmap; : enum fivr_supported_voltage v1p05_volt_bitmap; : enum fivr_supported_voltage vnn_volt_bitmap; Is there any benefit in calling all the members *_bitmap? The type is clear with the enum, so why not drop _bitmap and use it as state? And for the fivr_supported_voltage-members, I would rather call them v1p05_rail and vnn_rail respectively and drop the _bitmap, too. https://review.coreboot.org/c/coreboot/+/55861/comment/5758b58c_419b3689 PS3, Line 393: unsigned int vcc_low_high_usec; : /* From retention mode voltage to high current mode voltage */ : unsigned int vcc_ret_high_usec; : /* From retention mode voltage to low current mode voltage */ : unsigned int vcc_ret_low_usec; : /* From off(0V) to high current mode voltage */ : unsigned int vcc_off_high_usec; It seems like "us" is more often used for µs along the tree than usec. If you would like to have shorter member names I would adapt. -- To view, visit https://review.coreboot.org/c/coreboot/+/55861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5 Gerrit-Change-Number: 55861 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 05:12:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_ehl: Move SPD data to variant directory
by Werner Zeh (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Werner Zeh. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56036 to look at the new patch set (#2). Change subject: mb/siemens/mc_ehl: Move SPD data to variant directory ...................................................................... mb/siemens/mc_ehl: Move SPD data to variant directory Since the variants can have different memory move the SPD related content to the variant directory. Change-Id: I38aa5e7514437bfcc61c38d64f0ba6f19350810d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- D src/mainboard/siemens/mc_ehl/spd/Makefile.inc M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Makefile.inc R src/mainboard/siemens/mc_ehl/variants/mc_ehl1/spd/empty.spd.hex R src/mainboard/siemens/mc_ehl/variants/mc_ehl1/spd/mc_ehl1.spd.hex R src/mainboard/siemens/mc_ehl/variants/mc_ehl1/spd/spd.h 5 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/56036/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38aa5e7514437bfcc61c38d64f0ba6f19350810d Gerrit-Change-Number: 56036 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmap
by Werner Zeh (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Werner Zeh. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56035 to look at the new patch set (#2). Change subject: mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmap ...................................................................... mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmap There is a 16 MB flash chip on mc_ehl. Set the ROM size accordingly and provide a flashmap for partitioning. Select the used flashmap on variant level to allow different layouts for different variants. Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/Kconfig A src/mainboard/siemens/mc_ehl/mc_ehl.fmd A src/mainboard/siemens/mc_ehl/variants/mc_ehl1/Kconfig 3 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/56035/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I694729ad98f91e27308220903c49e7cb7fc436b4 Gerrit-Change-Number: 56035 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Set max Pkg C-states to Auto
by V Sowmya (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Patrick Rudolph. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55706 ) Change subject: soc/intel/alderlake: Set max Pkg C-states to Auto ...................................................................... Patch Set 7: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55706/comment/bc647a1e_20814898 PS6, Line 9: This patch configures max Pkg C-state to Auto which : limits the max C-state to deep C-state > fit upto 72col Done File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55706/comment/1ae4a2cf_2bed10ec PS6, Line 47: /* : * The Max Pkg Cstate : * Values 0 - C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, : * 254 - CPU Default , 255 - Auto. : */ : enum pkgcstate_limit { : LIMIT_C0_C1 = 0, : LIMIT_C2 = 1, : LIMIT_C3 = 2, : LIMIT_C6 = 3, : LIMIT_C7 = 4, : LIMIT_C7S = 5, : LIMIT_C8 = 6, : LIMIT_C9 = 7, : LIMIT_C10 = 8, : LIMIT_CPUDEFAULT = 254, : LIMIT_AUTO = 255, : }; > can we move this to chip. […] Done https://review.coreboot.org/c/coreboot/+/55706/comment/9692a94d_46b268e5 PS6, Line 545: /* Set the Max Pkg C-states to Auto */ > do we need this comment? UPD name and assignment is self-explanatory IMHO Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e Gerrit-Change-Number: 55706 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 04:49:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Set max Pkg C-states to Auto
by V Sowmya (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: V Sowmya, Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Vinay Kumar, Patrick Rudolph. Hello build bot (Jenkins), Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Subrata Banik, Vinay Kumar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55706 to look at the new patch set (#7). Change subject: soc/intel/alderlake: Set max Pkg C-states to Auto ...................................................................... soc/intel/alderlake: Set max Pkg C-states to Auto This patch configures max Pkg C-state to Auto which limits the max C-state to deep C-state Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/55706/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/55706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e Gerrit-Change-Number: 55706 Gerrit-PatchSet: 7 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: vagdevi.p(a)intel.com Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021