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Hello Nico Huber, Tim Wawrzynczak, Arthur Heymans, Werner Zeh, Patrick Rudolph,
I'd like you to do a code review. Please visit
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Change subject: config.emulation_qemu_x86_i440fx: Drop unneeded file
......................................................................
config.emulation_qemu_x86_i440fx: Drop unneeded file
Commit 549a33091a39de94998caa74f41d372118f5c12b (abuild: Always build
the default config) made this file unnecessary.
Change-Id: I83faef88673efc86cc813ef6035f67b4c38f1752
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
D configs/config.emulation_qemu_x86_i440fx
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/56078/1
diff --git a/configs/config.emulation_qemu_x86_i440fx b/configs/config.emulation_qemu_x86_i440fx
deleted file mode 100644
index b43736a..0000000
--- a/configs/config.emulation_qemu_x86_i440fx
+++ /dev/null
@@ -1 +0,0 @@
-# Everything is default, so the config is empty.
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Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56071
to look at the new patch set (#3).
Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
......................................................................
supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
Scan for external graphics, allows SeaBIOS to use the AST2400 without
disabling the IGD. Tested on X11SSH-LN4F.
Change-Id: I41249112c65927b61ca5f791f8eb8c3f3d204fce
Signed-off-by: Jan Tatje <jan(a)jnt.io>
---
M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md
M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
2 files changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/56071/3
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Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS4:
> Oh yes, sorry for the confusion. you are right its CB:55655. […]
@Nick, if you could pick this CL's latest patch set one more time and help to verify on volteer, if things are still fine. (I don't expect any regression though, but better to validate this)
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Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
......................................................................
Patch Set 6:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51374/comment/9969e357_2289f800
PS3, Line 24: Dump CAR MSRs in bootblock.
> Have you run stress test on different TGL SKUs with this change? +Raj and +Nick to keep in loop.
Ack
Commit Message:
https://review.coreboot.org/c/coreboot/+/51374/comment/f4e9c9a3_a62466c1
PS6, Line 9: MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL is used
> … and is used …?
Ack
https://review.coreboot.org/c/coreboot/+/51374/comment/64baa447_71aeaeeb
PS6, Line 15: Calcuate
> Calculate
Ack
File src/include/cpu/x86/msr.h:
https://review.coreboot.org/c/coreboot/+/51374/comment/c2c9ae01_5dbd54c0
PS3, Line 88: IA32_SF_WAY_CNT
> I got a confirmation that its being added into the SDM […]
Ack
File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/51374/comment/d82964e5_8ea7955c
PS5, Line 524: (1 << data_ways)
> result of two below operations would be different […]
Ack
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Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
......................................................................
soc/intel/common/../car: Calculate SF Mask#1 based on MSR 0xc87
MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is
used to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87
indicates the maximum numbers of bits that may be set in any of
the SF MASK register. Hence, this patch calculates SF way count to
program SF Mask#1 using below logic:
1. Calculate SFWayCnt = (MSR 0xC87) & 0x3f
2. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - ((1 << data_ways) - 1)
Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/include/cpu/x86/msr.h
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
2 files changed, 19 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/51374/7
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Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56033 )
Change subject: mb/siemens/mc_ehl: Provide a proper scheme for variants
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/siemens/mc_ehl: Add new mainboard based on elkhartlake_crb
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/56074/comment/20b5f7b3_9e935189
PS1, Line 62: 0x7
can we have bit wise macro to make the code more readable please ?
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/682a068b_a2005430
PS1, Line 115: /*
suggested to add a macro here, similar to https://review.coreboot.org/c/coreboot/+/56074/1/src/soc/intel/alderlake/ch… for TCSS port
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