coreboot-gerrit July 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7280: Add SHRM firmware support
by Ravi Kumar Bokka (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Ravi kumar, Shelley Chen, Paul Menzel, mturney mturney, Julius Werner. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49392 ) Change subject: sc7280: Add SHRM firmware support ...................................................................... Patch Set 54: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/49392/comment/331583cf_cc9f8089 PS50, Line 9: It use to > It is used to Done https://review.coreboot.org/c/coreboot/+/49392/comment/8fbcc3cd_e85b680c PS50, Line 9: manager, > Dot/period instead of comma. Done https://review.coreboot.org/c/coreboot/+/49392/comment/4f6c60d2_4ffb4b5d PS50, Line 10: DDRSS activities. > Please add more details, what DDRSS is. Done https://review.coreboot.org/c/coreboot/+/49392/comment/d7ee797f_1cf3cc7a PS50, Line 13: TEST=Validated on qualcomm sc7280 development board > How? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 54 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 18:43:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: IMOK: Add IMOK method support for DPTF
by Sumeet R Pawnikar (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Patrick Rudolph, Aaron Durbin, Karthik Ramasubramanian. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54688 ) Change subject: IMOK: Add IMOK method support for DPTF ...................................................................... Patch Set 3: (2 comments) File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/54688/comment/11efadae_b4f24f22 PS1, Line 262: DPTF > Sure, will add appropriate config checks as per comment. Ack https://review.coreboot.org/c/coreboot/+/54688/comment/c36e5273_0a138f21 PS1, Line 264: 0xA0 > I'll check on how to use #define in this .asl file. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/54688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8edfa3bcaa6bde0b9690fcace000cd582dcc81d2 Gerrit-Change-Number: 54688 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 05 Jul 2021 18:21:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: herobrine: Add support for USB initialization
by Ravi kumar (Code Review) 05 Jul '21

05 Jul '21

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Change in coreboot[master]: sc7180: Add support for USB common driver
by Ravi kumar (Code Review) 05 Jul '21

05 Jul '21

1 0

Change in coreboot[master]: sc7280: Add support for USB common driver
by Ravi kumar (Code Review) 05 Jul '21

05 Jul '21

1 0

Change in coreboot[master]: soc/qualcomm/common/usb: Add support for common USB driver
by Ravi kumar (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Sandeep Maheswaram. Hello Sandeep Maheswaram, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56091 to review the following change. Change subject: soc/qualcomm/common/usb: Add support for common USB driver ...................................................................... soc/qualcomm/common/usb: Add support for common USB driver Add common USB driver for qualcomm soc sc7180 and sc7280. This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy. BUG=b:182963902 TEST=Validated USB enumeration on qcom sc7180 and sc7280 development board Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 --- A src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/qusb_phy.h A src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h A src/soc/qualcomm/common/include/soc/usb/usb_common.h A src/soc/qualcomm/common/usb/qmp_usb_phy.c A src/soc/qualcomm/common/usb/qusb_phy.c A src/soc/qualcomm/common/usb/snps_usb_phy.c A src/soc/qualcomm/common/usb/usb.c 8 files changed, 1,387 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56091/1 diff --git a/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h new file mode 100644 index 0000000..a4ce80a --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/qmp_usb_phy.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <console/console.h> + +/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ +#define USB3_PCS_PHYSTATUS BIT(6) + +struct qmp_phy_init_tbl { + u32 *address; + u32 val; +}; + +struct ss_usb_phy_reg { + + /* Init sequence for QMP PHY blocks - serdes, tx, rx, pcs */ + const struct qmp_phy_init_tbl *serdes_tbl; + int serdes_tbl_num; + + const struct qmp_phy_init_tbl *tx_tbl; + int tx_tbl_num; + + const struct qmp_phy_init_tbl *rx_tbl; + int rx_tbl_num; + + const struct qmp_phy_init_tbl *pcs_tbl; + int pcs_tbl_num; + + struct usb3_phy_pcs_reg_layout *qmp_pcs_reg; +}; + +void ss_qmp_phy_init(void); + diff --git a/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h new file mode 100644 index 0000000..2784d3d --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/qusb_phy.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <console/console.h> + +#define PORT_TUNE1_MASK 0xf0 + +/* QUSB2PHY_PWR_CTRL1 register related bits */ +#define POWER_DOWN BIT(0) + +/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */ +#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4 + +/* STAT5 register bits */ +#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0) + +/* QUSB PHY register values */ +#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03 +#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c +#define QUSB2PHY_PLL_CMODE 0x80 +#define QUSB2PHY_PLL_LOCK_DELAY 0x0a +#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19 +#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40 +#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x22 +#define QUSB2PHY_PWR_CTRL2 0x21 +#define QUSB2PHY_IMP_CTRL1 0x08 +#define QUSB2PHY_IMP_CTRL2 0x58 +#define QUSB2PHY_PORT_TUNE1 0xc5 +#define QUSB2PHY_PORT_TUNE2 0x29 +#define QUSB2PHY_PORT_TUNE3 0xca +#define QUSB2PHY_PORT_TUNE4 0x04 +#define QUSB2PHY_PORT_TUNE5 0x03 +#define QUSB2PHY_CHG_CTRL2 0x30 + + +#define QFPROM_BASE 0x00780000 +#define QUSB_PRIM_PHY_BASE 0x088e3000 +#define QUSB_PRIM_PHY_DIG_BASE 0x088e3200 + +#define HS_USB_PRIM_PHY_BASE QUSB_PRIM_PHY_BASE + +/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */ +//#define USB3_PCS_PHYSTATUS BIT(6) + +struct usb_board_data { + /* Register values going to override from the boardfile */ + u32 pll_bias_control_2; + u32 imp_ctrl1; + u32 port_tune1; +}; + +struct usb_qusb_phy_dig { + u8 rsvd1[16]; + u32 pwr_ctrl1; + u32 pwr_ctrl2; + u8 rsvd2[8]; + u32 imp_ctrl1; + u32 imp_ctrl2; + u8 rsvd3[20]; + u32 chg_ctrl2; + u32 tune1; + u32 tune2; + u32 tune3; + u32 tune4; + u32 tune5; + u8 rsvd4[44]; + u32 debug_ctrl2; + u8 rsvd5[28]; + u32 debug_stat5; +}; +check_member(usb_qusb_phy_dig, tune5, 0x50); +check_member(usb_qusb_phy_dig, debug_ctrl2, 0x80); +check_member(usb_qusb_phy_dig, debug_stat5, 0xA0); + +struct usb_qusb_phy_pll { + u8 rsvd0[4]; + u32 analog_controls_two; + u8 rsvd1[36]; + u32 cmode; + u8 rsvd2[132]; + u32 dig_tim; + u8 rsvd3[204]; + u32 lock_delay; + u8 rsvd4[4]; + u32 clock_inverters; + u8 rsvd5[4]; + u32 bias_ctrl_1; + u32 bias_ctrl_2; +}; +check_member(usb_qusb_phy_pll, cmode, 0x2C); +check_member(usb_qusb_phy_pll, bias_ctrl_2, 0x198); +check_member(usb_qusb_phy_pll, dig_tim, 0xB4); + +struct hs_usb_phy_reg { + + struct usb_qusb_phy_pll *phy_pll; + + struct usb_qusb_phy_dig *phy_dig; + + struct usb_board_data *board_data; + + u32 efuse_offset; +}; + +void hs_usb_phy_init(struct usb_board_data *board_data); diff --git a/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h new file mode 100644 index 0000000..65258af --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/snps_usb_phy.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <console/console.h> + +struct hs_usb_phy_reg { + u8 rsvd1[60]; + u32 utmi_ctrl0; + u32 utmi_ctrl1; + u8 rsvd2[12]; + u32 utmi_ctrl5; + u32 hs_phy_ctrl_common0; + u32 hs_phy_ctrl_common1; + u32 hs_phy_ctrl_common2; + u32 hs_phy_ctrl1; + u32 hs_phy_ctrl2; + u8 rsvd3[44]; + u32 cfg0; + u8 rsvd4[8]; + u32 refclk_ctrl; +}; +check_member(hs_usb_phy_reg, utmi_ctrl0, 0x03c); +check_member(hs_usb_phy_reg, utmi_ctrl1, 0x040); +check_member(hs_usb_phy_reg, utmi_ctrl5, 0x050); +check_member(hs_usb_phy_reg, hs_phy_ctrl2, 0x064); +check_member(hs_usb_phy_reg, cfg0, 0x094); +check_member(hs_usb_phy_reg, refclk_ctrl, 0x0a0); + +void hs_usb_phy_init(void); + +/*SNPS USB HS PHY*/ + +#define GENMASK(h, l) (BIT(h + 1) - BIT(l)) + +#define SLEEPM BIT(0) + +#define TERMSEL BIT(5) + +#define POR BIT(1) + +#define FSEL_MASK GENMASK(7, 5) +#define FSEL_DEFAULT (0x3 << 4) + +#define VBUSVLDEXTSEL0 BIT(4) +#define PLLBTUNE BIT(5) + +#define VREGBYPASS BIT(0) + +#define VBUSVLDEXT0 BIT(0) + +#define USB2_SUSPEND_N BIT(2) +#define USB2_SUSPEND_N_SEL BIT(3) + +#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) + +#define REFCLK_SEL_MASK GENMASK(1, 0) +#define REFCLK_SEL_DEFAULT (0x2 << 0) + +/*SNPS USB HS PHY*/ diff --git a/src/soc/qualcomm/common/include/soc/usb/usb_common.h b/src/soc/qualcomm/common/include/soc/usb/usb_common.h new file mode 100644 index 0000000..37f2b37 --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/usb/usb_common.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#if CONFIG(QUSB_PHY) +#include "qusb_phy.h" +#endif +#if CONFIG(SNPS_USB_PHY) +#include "snps_usb_phy.h" +#endif + +#include "qmp_usb_phy.h" + +/* QSCRATCH_GENERAL_CFG register bit offset */ +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +/* Global USB3 Control Registers */ +#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18) +#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27) +#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) +#define DWC3_GCTL_PRTCAP_OTG 3 +#define DWC3_GCTL_PRTCAP_HOST 1 + +/* Global USB2 PHY Configuration Register */ +#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf) +#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) +#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1) +#define USBTRDTIM_UTMI_8_BIT 9 +#define UTMI_PHYIF_8_BIT 0 + +#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) +#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) +#define DWC3_GCTL_DISSCRAMBLE (1 << 3) +#define DWC3_GCTL_U2EXIT_LFPS (1 << 2) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +/* + * USB BASE ADDRESSES + */ + +#if CONFIG(QUSB_PHY) +void setup_usb_host0(struct usb_board_data *board_data); +#endif + +#if CONFIG(SNPS_USB_PHY) + +void setup_usb_host0(void); + +#endif + +/* Call reset_ before setup_ */ +void reset_usb0(void); + diff --git a/src/soc/qualcomm/common/usb/qmp_usb_phy.c b/src/soc/qualcomm/common/usb/qmp_usb_phy.c new file mode 100644 index 0000000..15e1374 --- /dev/null +++ b/src/soc/qualcomm/common/usb/qmp_usb_phy.c @@ -0,0 +1,784 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <timer.h> +#include <soc/usb/qmp_usb_phy.h> +#include <soc/addressmap.h> + +#if CONFIG(QMPV4_USB_PHY) +/* Only for QMP V4 PHY - QSERDES COM registers */ +struct usb3_phy_qserdes_com_reg_layout { + u8 _reserved1[16]; + u32 com_ssc_en_center; + u32 com_ssc_adj_per1; + u32 com_ssc_adj_per2; + u32 com_ssc_per1; + u32 com_ssc_per2; + u32 com_ssc_step_size1_mode0; + u32 com_ssc_step_size2_mode0; + u32 com_ssc_step_size3_mode0; + u32 com_ssc_step_size1_mode1; + u32 com_ssc_step_size2_mode1; + u32 com_ssc_step_size3_mode1; + u8 _reserved2[8]; + u32 com_bias_en_clkbuflr_en; + u32 com_sys_clk_enable1; + u32 com_sys_clk_ctrl; + u32 com_sysclk_buf_enable; + u32 com_pll_en; + u32 com_pll_ivco; + u8 _reserved3[4]; + u32 com_cmn_iptrim; + u8 _reserved4[16]; + u32 com_cp_ctrl_mode0; + u32 com_cp_ctrl_mode1; + u32 com_pll_rctrl_mode0; + u32 com_pll_rctrl_mode1; + u32 com_pll_cctrl_mode0; + u32 com_pll_cctrl_mode1; + u8 _reserved6[8]; + u32 com_sysclk_en_sel; + u8 _reserved7[8]; + u32 com_resetsm_ctrl2; + u32 com_lock_cmp_en; + u32 com_lock_cmp_cfg; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp1_mode1; + u32 com_lock_cmp2_mode1; + u32 com_dec_start_mode0; + u8 _reserved8[4]; + u32 com_dec_start_mode1; + u8 _reserved9[4]; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u32 com_div_frac_start1_mode1; + u32 com_div_frac_start2_mode1; + u32 com_div_frac_start3_mode1; + u8 _reserved10[8]; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u8 _reserved11[24]; + u32 com_vco_tune_map; + u32 com_vco_tune1_mode0; + u32 com_vco_tune2_mode0; + u32 com_vco_tune1_mode1; + u32 com_vco_tune2_mode1; + u8 _reserved12[52]; + u32 com_clk_select; + u32 com_hsclk_sel; + u8 _reserved13[12]; + u32 com_coreclk_div_mode0; + u32 com_coreclk_div_mode1; + u8 _reserved14[4]; + u32 com_core_clk_en; + u32 com_c_ready_status; + u32 com_cmn_config; + u32 com_cmn_rate_override; + u32 com_svs_mode_clk_sel; + u8 _reserved15[36]; + u32 com_bin_vcocal_cmp_code1_mode0; + u32 com_bin_vcocal_cmp_code2_mode0; + u32 com_bin_vcocal_cmp_code1_mode1; + u32 com_bin_vcocal_cmp_code2_mode1; + u32 com_bin_vcocal_hsclk_sel; +}; + +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); +check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x044); +check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x058); +check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x074); +check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x094); +check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x0a0); +check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0bc); +check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0cc); +check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0ec); +check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x010c); +check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x154); +check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x168); +check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x174); +check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x184); +check_member(usb3_phy_qserdes_com_reg_layout, com_bin_vcocal_hsclk_sel, 0x1bc); + +/* Only for QMP V4 PHY - TX registers */ +struct usb3_phy_qserdes_tx_reg_layout { + u8 _reserved1[52]; + u32 tx_res_code_lane_tx; + u32 tx_res_code_lane_rx; + u32 tx_res_code_lane_offset_tx; + u32 tx_res_code_lane_offset_rx; + u8 _reserved2[64]; + u32 tx_lane_mode_1; + u8 _reserved3[20]; + u32 tx_rcv_detect_lvl_2; + u8 _reserved4[100]; + u32 tx_pi_qec_ctrl; +}; +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x03c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x040); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x084); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x09c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_pi_qec_ctrl, 0x104); + +/* Only for QMP V4 PHY - RX registers */ +struct usb3_phy_qserdes_rx_reg_layout { + u8 _reserved1[20]; + u32 rx_ucdr_so_gain; + u8 _reserved2[24]; + u32 rx_ucdr_fastlock_fo_gain; + u32 rx_ucdr_so_saturation_and_enable; + u8 _reserved3[4]; + u32 rx_ucdr_fastlock_count_low; + u32 rx_ucdr_fastlock_count_high; + u32 rx_ucdr_pi_controls; + u8 _reserved4[4]; + u32 rx_ucdr_sb2_thresh1; + u32 rx_ucdr_sb2_thresh2; + u32 rx_ucdr_sb2_gain1; + u32 rx_ucdr_sb2_gain2; + u8 _reserved12[4]; + u32 rx_aux_data_tcoarse_tfine; + u8 _reserved5[112]; + u32 rx_vga_cal_cntrl1; + u32 rx_vga_cal_cntrl2; + u32 rx_gm_cal; + u8 _reserved6[12]; + u32 rx_rx_equ_adaptor_cntrl2; + u32 rx_rx_equ_adaptor_cntrl3; + u32 rx_rx_equ_adaptor_cntrl4; + u32 rx_rx_idac_tsettle_low; + u32 rx_rx_idac_tsettle_high; + u8 _reserved7[16]; + u32 rx_rx_eq_offset_adaptor_cntrl1; + u8 _reserved8[8]; + u32 rx_sigdet_cntrl; + u8 _reserved9[4]; + u32 rx_sigdet_deglitch_cntrl; + u8 _reserved10[72]; + u32 rx_rx_mode_00_low; + u32 rx_rx_mode_00_high; + u32 rx_rx_mode_00_high2; + u32 rx_rx_mode_00_high3; + u32 rx_rx_mode_00_high4; + u32 rx_rx_mode_01_low; + u32 rx_rx_mode_01_high; + u32 rx_rx_mode_01_high2; + u32 rx_rx_mode_01_high3; + u32 rx_rx_mode_01_high4; + u8 _reserved11[28]; + u32 rx_dfe_en_timer; + u32 rx_dfe_ctle_post_cal_offset; + u32 rx_dcc_ctrl1; + u8 _reserved13[4]; + u32 rx_vth_code; +}; + +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain, 0x014); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_cntrl1, 0x0d4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl2, 0x0ec); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl3, 0x0f0); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adaptor_cntrl4, 0x0f4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_cntrl, 0x11c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_dcc_ctrl1, 0x1bc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vth_code, 0x1c4); + +/* Only for QMP V4 PHY - PCS registers */ +struct usb3_phy_pcs_reg_layout { + u32 pcs_sw_reset; + u8 _reserved0[16]; + u32 pcs_ready_status; + u8 _reserved1[40]; + u32 pcs_power_down_control; + u32 pcs_start_control; + u8 _reserved2[124]; + u32 pcs_lock_detect_config1; + u32 pcs_lock_detect_config2; + u32 pcs_lock_detect_config3; + u8 _reserved3[8]; + u32 pcs_lock_detect_config6; + u32 pcs_refgen_req_config1; + u8 _reserved4[168]; + u32 pcs_rx_sigdet_lvl; + u8 _reserved5[36]; + u32 pcs_cdr_reset_time; + u8 _reserved6[12]; + u32 pcs_align_detect_config1; + u32 pcs_align_detect_config2; + u8 _reserved7[8]; + u32 pcs_pcs_tx_rx_config; + u8 _reserved8[8]; + u32 pcs_eq_config1; + u8 _reserved9[12]; + u32 pcs_eq_config5; + u8 _reserved10[296]; + u32 pcs_usb3_lfps_det_high_count_val; + u8 _reserved11[28]; + u32 pcs_usb3_rxeqtraining_dfe_time_s2; +}; + +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x0c4); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x0c8); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config6, 0x0d8); +check_member(usb3_phy_pcs_reg_layout, pcs_pcs_tx_rx_config, 0x1d0); +check_member(usb3_phy_pcs_reg_layout, pcs_eq_config5, 0x1ec); +check_member(usb3_phy_pcs_reg_layout, pcs_usb3_lfps_det_high_count_val, 0x318); +check_member(usb3_phy_pcs_reg_layout, pcs_usb3_rxeqtraining_dfe_time_s2, 0x338); + +static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = + (void *)QMP_PHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = + (void *)QMP_PHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = + (void *)QMP_PHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = + (void *)QMP_PHY_PCS_REG_BASE; +static const struct qmp_phy_init_tbl qmp_v4_usb3_serdes_tbl[] = { + {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&qserdes_com_reg_layout->com_ssc_step_size1_mode0, 0xde}, + {&qserdes_com_reg_layout->com_ssc_step_size2_mode0, 0x07}, + {&qserdes_com_reg_layout->com_ssc_step_size1_mode1, 0xde}, + {&qserdes_com_reg_layout->com_ssc_step_size2_mode1, 0x07}, + {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&qserdes_com_reg_layout->com_cmn_iptrim, 0x20}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode1, 0x06}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode1, 0x16}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode1, 0x36}, + {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x1a}, + {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x14}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode1, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode1, 0x82}, + {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&qserdes_com_reg_layout->com_dec_start_mode1, 0x82}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode1, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode1, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode1, 0x02}, + {&qserdes_com_reg_layout->com_vco_tune_map, 0x02}, + {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0x24}, + {&qserdes_com_reg_layout->com_vco_tune1_mode1, 0x24}, + {&qserdes_com_reg_layout->com_vco_tune2_mode1, 0x02}, + {&qserdes_com_reg_layout->com_hsclk_sel, 0x01}, + {&qserdes_com_reg_layout->com_coreclk_div_mode1, 0x08}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode0, 0xca}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode0, 0x1e}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code1_mode1, 0xca}, + {&qserdes_com_reg_layout->com_bin_vcocal_cmp_code2_mode1, 0x1e}, + {&qserdes_com_reg_layout->com_bin_vcocal_hsclk_sel, 0x11}, +}; + +static const struct qmp_phy_init_tbl qmp_v4_usb3_tx_tbl[] = { + {&qserdes_tx_reg_layout->tx_res_code_lane_tx, 0x60}, + {&qserdes_tx_reg_layout->tx_res_code_lane_rx, 0x60}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x11}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x02}, + {&qserdes_tx_reg_layout->tx_lane_mode_1, 0xd5}, + {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&qserdes_tx_reg_layout->tx_pi_qec_ctrl, 0x40}, +}; + +static const struct qmp_phy_init_tbl qmp_v4_usb3_rx_tbl[] = { + {&qserdes_rx_reg_layout->rx_ucdr_so_gain, 0x06}, + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x2f}, + {&qserdes_rx_reg_layout->rx_ucdr_so_saturation_and_enable, 0x7f}, + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_low, 0xff}, + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_count_high, 0x0f}, + {&qserdes_rx_reg_layout->rx_ucdr_pi_controls, 0x99}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh1, 0x04}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_thresh2, 0x08}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain1, 0x05}, + {&qserdes_rx_reg_layout->rx_ucdr_sb2_gain2, 0x05}, + {&qserdes_rx_reg_layout->rx_vga_cal_cntrl1, 0x54}, + {&qserdes_rx_reg_layout->rx_vga_cal_cntrl2, 0x0c}, + {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl2, 0x0f}, + {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl3, 0x4a}, + {&qserdes_rx_reg_layout->rx_rx_equ_adaptor_cntrl4, 0x0a}, + {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_low, 0xc0}, + {&qserdes_rx_reg_layout->rx_rx_idac_tsettle_high, 0x00}, + {&qserdes_rx_reg_layout->rx_rx_eq_offset_adaptor_cntrl1, 0x77}, + {&qserdes_rx_reg_layout->rx_sigdet_cntrl, 0x04}, + {&qserdes_rx_reg_layout->rx_sigdet_deglitch_cntrl, 0x0e}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0xff}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_low, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high, 0xff}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high2, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high3, 0x7f}, + {&qserdes_rx_reg_layout->rx_rx_mode_00_high4, 0x97}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_low, 0xdc}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high, 0xdc}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high2, 0x5c}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high3, 0x7b}, + {&qserdes_rx_reg_layout->rx_rx_mode_01_high4, 0xb4}, + {&qserdes_rx_reg_layout->rx_dfe_en_timer, 0x04}, + {&qserdes_rx_reg_layout->rx_dfe_ctle_post_cal_offset, 0x38}, + {&qserdes_rx_reg_layout->rx_aux_data_tcoarse_tfine, 0xa0}, + {&qserdes_rx_reg_layout->rx_dcc_ctrl1, 0x0c}, + {&qserdes_rx_reg_layout->rx_gm_cal, 0x1f}, + {&qserdes_rx_reg_layout->rx_vth_code, 0x10}, +}; + +static const struct qmp_phy_init_tbl qmp_v4_usb3_pcs_tbl[] = { + {&pcs_reg_layout->pcs_lock_detect_config1, 0xd0}, + {&pcs_reg_layout->pcs_lock_detect_config2, 0x07}, + {&pcs_reg_layout->pcs_lock_detect_config3, 0x20}, + {&pcs_reg_layout->pcs_lock_detect_config6, 0x13}, + {&pcs_reg_layout->pcs_refgen_req_config1, 0x21}, + {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xa9}, + {&pcs_reg_layout->pcs_cdr_reset_time, 0x0a}, + {&pcs_reg_layout->pcs_align_detect_config1, 0x88}, + {&pcs_reg_layout->pcs_align_detect_config2, 0x13}, + {&pcs_reg_layout->pcs_pcs_tx_rx_config, 0x0c}, + {&pcs_reg_layout->pcs_eq_config1, 0x4b}, + {&pcs_reg_layout->pcs_eq_config5, 0x10}, + {&pcs_reg_layout->pcs_usb3_lfps_det_high_count_val, 0xf8}, + {&pcs_reg_layout->pcs_usb3_rxeqtraining_dfe_time_s2, 0x07}, +}; + +struct ss_usb_phy_reg qmp_v4_usb_phy += { + .serdes_tbl = qmp_v4_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v4_usb3_serdes_tbl), + .tx_tbl = qmp_v4_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_tx_tbl), + .rx_tbl = qmp_v4_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v4_usb3_rx_tbl), + .pcs_tbl = qmp_v4_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v4_usb3_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, +}; + +#endif + + +#if CONFIG(QMPV3_USB_PHY) +/* Only for QMP V3 PHY - QSERDES COM registers */ +struct usb3_phy_qserdes_com_reg_layout { + u8 _reserved1[16]; + u32 com_ssc_en_center; + u32 com_ssc_adj_per1; + u32 com_ssc_adj_per2; + u32 com_ssc_per1; + u32 com_ssc_per2; + u32 com_ssc_step_size1; + u32 com_ssc_step_size2; + u8 _reserved2[8]; + u32 com_bias_en_clkbuflr_en; + u32 com_sys_clk_enable1; + u32 com_sys_clk_ctrl; + u32 com_sysclk_buf_enable; + u32 com_pll_en; + u32 com_pll_ivco; + u8 _reserved3[20]; + u32 com_cp_ctrl_mode0; + u8 _reserved4[4]; + u32 com_pll_rctrl_mode0; + u8 _reserved5[4]; + u32 com_pll_cctrl_mode0; + u8 _reserved6[12]; + u32 com_sysclk_en_sel; + u8 _reserved7[8]; + u32 com_resetsm_ctrl2; + u32 com_lock_cmp_en; + u32 com_lock_cmp_cfg; + u32 com_lock_cmp1_mode0; + u32 com_lock_cmp2_mode0; + u32 com_lock_cmp3_mode0; + u8 _reserved8[12]; + u32 com_dec_start_mode0; + u8 _reserved9[4]; + u32 com_div_frac_start1_mode0; + u32 com_div_frac_start2_mode0; + u32 com_div_frac_start3_mode0; + u8 _reserved10[20]; + u32 com_integloop_gain0_mode0; + u32 com_integloop_gain1_mode0; + u8 _reserved11[16]; + u32 com_vco_tune_map; + u32 com_vco_tune1_mode0; + u32 com_vco_tune2_mode0; + u8 _reserved12[60]; + u32 com_clk_select; + u32 com_hsclk_sel; + u8 _reserved13[8]; + u32 com_coreclk_div_mode0; + u8 _reserved14[8]; + u32 com_core_clk_en; + u32 com_c_ready_status; + u32 com_cmn_config; + u32 com_cmn_rate_override; + u32 com_svs_mode_clk_sel; +}; +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_en_center, 0x010); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per1, 0x014); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_adj_per2, 0x018); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per1, 0x01c); +check_member(usb3_phy_qserdes_com_reg_layout, com_ssc_per2, 0x020); +check_member(usb3_phy_qserdes_com_reg_layout, com_bias_en_clkbuflr_en, 0x034); +check_member(usb3_phy_qserdes_com_reg_layout, com_pll_ivco, 0x048); +check_member(usb3_phy_qserdes_com_reg_layout, com_cp_ctrl_mode0, 0x060); +check_member(usb3_phy_qserdes_com_reg_layout, com_sysclk_en_sel, 0x080); +check_member(usb3_phy_qserdes_com_reg_layout, com_resetsm_ctrl2, 0x08c); +check_member(usb3_phy_qserdes_com_reg_layout, com_dec_start_mode0, 0x0b0); +check_member(usb3_phy_qserdes_com_reg_layout, com_div_frac_start1_mode0, 0x0b8); +check_member(usb3_phy_qserdes_com_reg_layout, com_integloop_gain0_mode0, 0x0d8); +check_member(usb3_phy_qserdes_com_reg_layout, com_vco_tune_map, 0x0f0); +check_member(usb3_phy_qserdes_com_reg_layout, com_clk_select, 0x138); +check_member(usb3_phy_qserdes_com_reg_layout, com_coreclk_div_mode0, 0x148); +check_member(usb3_phy_qserdes_com_reg_layout, com_core_clk_en, 0x154); +check_member(usb3_phy_qserdes_com_reg_layout, com_svs_mode_clk_sel, 0x164); + +/* Only for QMP V3 PHY - TX registers */ +struct usb3_phy_qserdes_tx_reg_layout { + u8 _reserved1[68]; + u32 tx_res_code_lane_offset_tx; + u32 tx_res_code_lane_offset_rx; + u8 _reserved2[20]; + u32 tx_highz_drvr_en; + u8 _reserved3[40]; + u32 tx_lane_mode_1; + u8 _reserved4[20]; + u32 tx_rcv_detect_lvl_2; +}; +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_tx, 0x044); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_res_code_lane_offset_rx, 0x048); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_highz_drvr_en, 0x060); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_lane_mode_1, 0x08c); +check_member(usb3_phy_qserdes_tx_reg_layout, tx_rcv_detect_lvl_2, 0x0a4); + +/* Only for QMP V3 PHY - RX registers */ +struct usb3_phy_qserdes_rx_reg_layout { + u8 _reserved1[8]; + u32 rx_ucdr_fo_gain; + u32 rx_ucdr_so_gain_half; + u8 _reserved2[32]; + u32 rx_ucdr_fastlock_fo_gain; + u32 rx_ucdr_so_saturtn_and_en; + u8 _reserved3[12]; + u32 rx_ucdr_pi_cntrls; + u8 _reserved4[120]; + u32 rx_vga_cal_ctrl2; + u8 _reserved5[16]; + u32 rx_rx_equ_adap_ctrl2; + u32 rx_rx_equ_adap_ctrl3; + u32 rx_rx_equ_adap_ctrl4; + u8 _reserved6[24]; + u32 rx_rx_eq_offset_adap_ctrl1; + u32 rx_rx_offset_adap_ctrl2; + u32 rx_sigdet_enables; + u32 rx_sigdet_ctrl; + u8 _reserved7[4]; + u32 rx_sigdet_deglitch_ctrl; + u32 rx_rx_band; + u8 _reserved8[80]; + u32 rx_rx_mode_00; +}; +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fo_gain, 0x008); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_gain_half, 0x00c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_fastlock_fo_gain, 0x030); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_so_saturtn_and_en, 0x034); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_ucdr_pi_cntrls, 0x044); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_vga_cal_ctrl2, 0x0c0); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl2, 0x0d4); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl3, 0x0d8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_equ_adap_ctrl4, 0x0dc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_eq_offset_adap_ctrl1, 0x0f8); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_offset_adap_ctrl2, 0x0fc); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_enables, 0x100); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_ctrl, 0x104); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_sigdet_deglitch_ctrl, 0x10c); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_band, 0x110); +check_member(usb3_phy_qserdes_rx_reg_layout, rx_rx_mode_00, 0x164); + +/* Only for QMP V3 PHY - PCS registers */ +struct usb3_phy_pcs_reg_layout { + u32 pcs_sw_reset; + u32 pcs_power_down_control; + u32 pcs_start_control; + u32 pcs_txmgn_v0; + u32 pcs_txmgn_v1; + u32 pcs_txmgn_v2; + u32 pcs_txmgn_v3; + u32 pcs_txmgn_v4; + u32 pcs_txmgn_ls; + u32 pcs_txdeemph_m6db_v0; + u32 pcs_txdeemph_m3p5db_v0; + u32 pcs_txdeemph_m6db_v1; + u32 pcs_txdeemph_m3p5db_v1; + u32 pcs_txdeemph_m6db_v2; + u32 pcs_txdeemph_m3p5db_v2; + u32 pcs_txdeemph_m6db_v3; + u32 pcs_txdeemph_m3p5db_v3; + u32 pcs_txdeemph_m6db_v4; + u32 pcs_txdeemph_m3p5db_v4; + u32 pcs_txdeemph_m6db_ls; + u32 pcs_txdeemph_m3p5db_ls; + u8 _reserved1[8]; + u32 pcs_rate_slew_cntrl; + u8 _reserved2[4]; + u32 pcs_power_state_config2; + u8 _reserved3[8]; + u32 pcs_rcvr_dtct_dly_p1u2_l; + u32 pcs_rcvr_dtct_dly_p1u2_h; + u32 pcs_rcvr_dtct_dly_u3_l; + u32 pcs_rcvr_dtct_dly_u3_h; + u32 pcs_lock_detect_config1; + u32 pcs_lock_detect_config2; + u32 pcs_lock_detect_config3; + u32 pcs_tsync_rsync_time; + u8 _reserved4[16]; + u32 pcs_pwrup_reset_dly_time_auxclk; + u8 _reserved5[12]; + u32 pcs_lfps_ecstart_eqtlock; + u8 _reserved6[4]; + u32 pcs_rxeqtraining_wait_time; + u32 pcs_rxeqtraining_run_time; + u8 _reserved7[4]; + u32 pcs_fll_ctrl1; + u32 pcs_fll_ctrl2; + u32 pcs_fll_cnt_val_l; + u32 pcs_fll_cnt_val_h_tol; + u32 pcs_fll_man_code; + u32 pcs_autonomous_mode_ctrl; + u8 _reserved8[152]; + u32 pcs_ready_status; + u8 _reserved9[96]; + u32 pcs_rx_sigdet_lvl; + u8 _reserved10[48]; + u32 pcs_refgen_req_config1; + u32 pcs_refgen_req_config2; +}; +check_member(usb3_phy_pcs_reg_layout, pcs_sw_reset, 0x000); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v0, 0x00c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v1, 0x010); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v2, 0x014); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v3, 0x018); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_v4, 0x01c); +check_member(usb3_phy_pcs_reg_layout, pcs_txmgn_ls, 0x020); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v0, 0x024); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v0, 0x028); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v1, 0x02c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v1, 0x030); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v2, 0x034); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v2, 0x038); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v3, 0x03c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v3, 0x040); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_v4, 0x044); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_v4, 0x048); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m6db_ls, 0x04c); +check_member(usb3_phy_pcs_reg_layout, pcs_txdeemph_m3p5db_ls, 0x050); +check_member(usb3_phy_pcs_reg_layout, pcs_rate_slew_cntrl, 0x05c); +check_member(usb3_phy_pcs_reg_layout, pcs_power_state_config2, 0x064); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_l, 0x070); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_p1u2_h, 0x074); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_l, 0x078); +check_member(usb3_phy_pcs_reg_layout, pcs_rcvr_dtct_dly_u3_h, 0x07c); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config1, 0x080); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config2, 0x084); +check_member(usb3_phy_pcs_reg_layout, pcs_lock_detect_config3, 0x088); +check_member(usb3_phy_pcs_reg_layout, pcs_pwrup_reset_dly_time_auxclk, 0x0a0); +check_member(usb3_phy_pcs_reg_layout, pcs_rxeqtraining_wait_time, 0x0b8); +check_member(usb3_phy_pcs_reg_layout, pcs_fll_cnt_val_h_tol, 0x0d0); +check_member(usb3_phy_pcs_reg_layout, pcs_autonomous_mode_ctrl, 0x0d8); +check_member(usb3_phy_pcs_reg_layout, pcs_ready_status, 0x174); +check_member(usb3_phy_pcs_reg_layout, pcs_refgen_req_config2, 0x210); + +static struct usb3_phy_qserdes_com_reg_layout *const qserdes_com_reg_layout = + (void *)QMP_PHY_QSERDES_COM_REG_BASE; +static struct usb3_phy_qserdes_tx_reg_layout *const qserdes_tx_reg_layout = + (void *)QMP_PHY_QSERDES_TX_REG_BASE; +static struct usb3_phy_qserdes_rx_reg_layout *const qserdes_rx_reg_layout = + (void *)QMP_PHY_QSERDES_RX_REG_BASE; +static struct usb3_phy_pcs_reg_layout *const pcs_reg_layout = + (void *)QMP_PHY_PCS_REG_BASE; + + +static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { + {&qserdes_com_reg_layout->com_pll_ivco, 0x07}, + {&qserdes_com_reg_layout->com_sysclk_en_sel, 0x14}, + {&qserdes_com_reg_layout->com_bias_en_clkbuflr_en, 0x08}, + {&qserdes_com_reg_layout->com_clk_select, 0x30}, + {&qserdes_com_reg_layout->com_sys_clk_ctrl, 0x02}, + {&qserdes_com_reg_layout->com_resetsm_ctrl2, 0x08}, + {&qserdes_com_reg_layout->com_cmn_config, 0x16}, + {&qserdes_com_reg_layout->com_svs_mode_clk_sel, 0x01}, + {&qserdes_com_reg_layout->com_hsclk_sel, 0x80}, + {&qserdes_com_reg_layout->com_dec_start_mode0, 0x82}, + {&qserdes_com_reg_layout->com_div_frac_start1_mode0, 0xab}, + {&qserdes_com_reg_layout->com_div_frac_start2_mode0, 0xea}, + {&qserdes_com_reg_layout->com_div_frac_start3_mode0, 0x02}, + {&qserdes_com_reg_layout->com_cp_ctrl_mode0, 0x06}, + {&qserdes_com_reg_layout->com_pll_rctrl_mode0, 0x16}, + {&qserdes_com_reg_layout->com_pll_cctrl_mode0, 0x36}, + {&qserdes_com_reg_layout->com_integloop_gain1_mode0, 0x00}, + {&qserdes_com_reg_layout->com_integloop_gain0_mode0, 0x3f}, + {&qserdes_com_reg_layout->com_vco_tune2_mode0, 0x01}, + {&qserdes_com_reg_layout->com_vco_tune1_mode0, 0xc9}, + {&qserdes_com_reg_layout->com_coreclk_div_mode0, 0x0a}, + {&qserdes_com_reg_layout->com_lock_cmp3_mode0, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp2_mode0, 0x34}, + {&qserdes_com_reg_layout->com_lock_cmp1_mode0, 0x15}, + {&qserdes_com_reg_layout->com_lock_cmp_en, 0x04}, + {&qserdes_com_reg_layout->com_core_clk_en, 0x00}, + {&qserdes_com_reg_layout->com_lock_cmp_cfg, 0x00}, + {&qserdes_com_reg_layout->com_vco_tune_map, 0x00}, + {&qserdes_com_reg_layout->com_sysclk_buf_enable, 0x0a}, + {&qserdes_com_reg_layout->com_ssc_en_center, 0x01}, + {&qserdes_com_reg_layout->com_ssc_per1, 0x31}, + {&qserdes_com_reg_layout->com_ssc_per2, 0x01}, + {&qserdes_com_reg_layout->com_ssc_adj_per1, 0x00}, + {&qserdes_com_reg_layout->com_ssc_adj_per2, 0x00}, + {&qserdes_com_reg_layout->com_ssc_step_size1, 0x85}, + {&qserdes_com_reg_layout->com_ssc_step_size2, 0x07}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { + {&qserdes_tx_reg_layout->tx_highz_drvr_en, 0x10}, + {&qserdes_tx_reg_layout->tx_rcv_detect_lvl_2, 0x12}, + {&qserdes_tx_reg_layout->tx_lane_mode_1, 0x16}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_rx, 0x09}, + {&qserdes_tx_reg_layout->tx_res_code_lane_offset_tx, 0x06}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { + {&qserdes_rx_reg_layout->rx_ucdr_fastlock_fo_gain, 0x0b}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl2, 0x0f}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl3, 0x4e}, + {&qserdes_rx_reg_layout->rx_rx_equ_adap_ctrl4, 0x18}, + {&qserdes_rx_reg_layout->rx_rx_eq_offset_adap_ctrl1, 0x77}, + {&qserdes_rx_reg_layout->rx_rx_offset_adap_ctrl2, 0x80}, + {&qserdes_rx_reg_layout->rx_sigdet_ctrl, 0x03}, + {&qserdes_rx_reg_layout->rx_sigdet_deglitch_ctrl, 0x16}, + {&qserdes_rx_reg_layout->rx_ucdr_so_saturtn_and_en, 0x75}, + {&qserdes_rx_reg_layout->rx_ucdr_pi_cntrls, 0x80}, + {&qserdes_rx_reg_layout->rx_ucdr_fo_gain, 0x0a}, + {&qserdes_rx_reg_layout->rx_ucdr_so_gain_half, 0x06}, + {&qserdes_rx_reg_layout->rx_sigdet_enables, 0x00}, +}; + +static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { + /* FLL settings */ + {&pcs_reg_layout->pcs_fll_ctrl2, 0x83}, + {&pcs_reg_layout->pcs_fll_cnt_val_l, 0x09}, + {&pcs_reg_layout->pcs_fll_cnt_val_h_tol, 0xa2}, + {&pcs_reg_layout->pcs_fll_man_code, 0x40}, + {&pcs_reg_layout->pcs_fll_ctrl1, 0x02}, + + /* Lock Det settings */ + {&pcs_reg_layout->pcs_lock_detect_config1, 0xd1}, + {&pcs_reg_layout->pcs_lock_detect_config2, 0x1f}, + {&pcs_reg_layout->pcs_lock_detect_config3, 0x47}, + {&pcs_reg_layout->pcs_power_state_config2, 0x1b}, + + {&pcs_reg_layout->pcs_rx_sigdet_lvl, 0xba}, + {&pcs_reg_layout->pcs_txmgn_v0, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v1, 0x9f}, + {&pcs_reg_layout->pcs_txmgn_v2, 0xb7}, + {&pcs_reg_layout->pcs_txmgn_v3, 0x4e}, + {&pcs_reg_layout->pcs_txmgn_v4, 0x65}, + {&pcs_reg_layout->pcs_txmgn_ls, 0x6b}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v0, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v0, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v1, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v1, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v2, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v2, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v3, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v3, 0x1d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_v4, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_v4, 0x0d}, + {&pcs_reg_layout->pcs_txdeemph_m6db_ls, 0x15}, + {&pcs_reg_layout->pcs_txdeemph_m3p5db_ls, 0x0d}, + {&pcs_reg_layout->pcs_rate_slew_cntrl, 0x02}, + {&pcs_reg_layout->pcs_pwrup_reset_dly_time_auxclk, 0x04}, + {&pcs_reg_layout->pcs_tsync_rsync_time, 0x44}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_l, 0xe7}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_p1u2_h, 0x03}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_l, 0x40}, + {&pcs_reg_layout->pcs_rcvr_dtct_dly_u3_h, 0x00}, + {&pcs_reg_layout->pcs_rxeqtraining_wait_time, 0x75}, + {&pcs_reg_layout->pcs_lfps_ecstart_eqtlock, 0x86}, + {&pcs_reg_layout->pcs_rxeqtraining_run_time, 0x13}, +}; + + +struct ss_usb_phy_reg qmp_v3_usb_phy += { + .serdes_tbl = qmp_v3_usb3_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), + .tx_tbl = qmp_v3_usb3_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), + .rx_tbl = qmp_v3_usb3_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), + .pcs_tbl = qmp_v3_usb3_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), + .qmp_pcs_reg = (void *)QMP_PHY_PCS_REG_BASE, +}; +#endif +static void qcom_qmp_phy_configure(const struct qmp_phy_init_tbl tbl[], + int num) +{ + int i; + const struct qmp_phy_init_tbl *t = tbl; + + if (!t) + return; + + for (i = 0; i < num; i++, t++) + write32(t->address, t->val); +} + +void ss_qmp_phy_init(void) +{ + struct ss_usb_phy_reg *ss_phy_reg; + + #if CONFIG(QMPV4_USB_PHY) + ss_phy_reg = &qmp_v4_usb_phy; + #endif + + #if CONFIG(QMPV3_USB_PHY) + ss_phy_reg = &qmp_v3_usb_phy; + #endif + /* power up USB3 PHY */ + write32(&ss_phy_reg->qmp_pcs_reg->pcs_power_down_control, 0x01); + + /* Serdes configuration */ + qcom_qmp_phy_configure(ss_phy_reg->serdes_tbl, + ss_phy_reg->serdes_tbl_num); + /* Tx, Rx, and PCS configurations */ + qcom_qmp_phy_configure(ss_phy_reg->tx_tbl, ss_phy_reg->tx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->rx_tbl, ss_phy_reg->rx_tbl_num); + qcom_qmp_phy_configure(ss_phy_reg->pcs_tbl, ss_phy_reg->pcs_tbl_num); + + /* perform software reset of PCS/Serdes */ + write32(&ss_phy_reg->qmp_pcs_reg->pcs_sw_reset, 0x00); + /* start PCS/Serdes to operation mode */ + write32(&ss_phy_reg->qmp_pcs_reg->pcs_start_control, 0x03); + + /* + * Wait for PHY initialization to be done + * PCS_STATUS: wait for 1ms for PHY STATUS; + * SW can continuously check for PHYSTATUS = 1.b0. + */ + long lock_us = wait_us(10000, + !(read32(&ss_phy_reg->qmp_pcs_reg->pcs_ready_status) & + USB3_PCS_PHYSTATUS)); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QMP PHY PLL LOCK fails:\n"); + else + printk(BIOS_DEBUG, "QMP PHY initialized and locked in %ldus\n", + lock_us); +} diff --git a/src/soc/qualcomm/common/usb/qusb_phy.c b/src/soc/qualcomm/common/usb/qusb_phy.c new file mode 100644 index 0000000..1b8c114 --- /dev/null +++ b/src/soc/qualcomm/common/usb/qusb_phy.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/usb/qusb_phy.h> +#include <soc/efuse.h> +#include <timer.h> + +static struct qfprom_corr * const qfprom_corr_efuse = (void *)QFPROM_BASE; + +struct hs_usb_phy_reg qusb_phy = { + + .phy_pll = (void *)QUSB_PRIM_PHY_BASE, + + .phy_dig = (void *)QUSB_PRIM_PHY_DIG_BASE, + + .efuse_offset = 25, +}; + +static void qusb2_phy_override_phy_params(struct hs_usb_phy_reg *hs_phy_reg) +{ + /* Override preemphasis value */ + write32(&hs_phy_reg->phy_dig->tune1, + hs_phy_reg->board_data->port_tune1); + + /* Override BIAS_CTRL_2 to reduce the TX swing overshooting. */ + write32(&hs_phy_reg->phy_pll->bias_ctrl_2, + hs_phy_reg->board_data->pll_bias_control_2); + + /* Override IMP_RES_OFFSET value */ + write32(&hs_phy_reg->phy_dig->imp_ctrl1, + hs_phy_reg->board_data->imp_ctrl1); +} + +/* + * Fetches HS Tx tuning value from efuse register and sets the + * QUSB2PHY_PORT_TUNE1/2 register. + * For error case, skip setting the value and use the default value. + */ + +static void qusb2_phy_set_tune_param(struct hs_usb_phy_reg *hs_phy_reg) +{ + /* + * Efuse registers 3 bit value specifies tuning for HSTX + * output current in TUNE1 Register. Hence Extract 3 bits from + * EFUSE at correct position. + */ + + const int efuse_bits = 3; + int bit_pos = hs_phy_reg->efuse_offset; + + u32 bit_mask = (1 << efuse_bits) - 1; + u32 tune_val = + (read32(&qfprom_corr_efuse->qusb_hstx_trim_lsb) >> bit_pos) + & bit_mask; + /* + * if efuse reg is updated (i.e non-zero) then use it to program + * tune parameters. + */ + if (tune_val) + clrsetbits32(&hs_phy_reg->phy_dig->tune1, + PORT_TUNE1_MASK, tune_val << 4); +} + +static void tune_phy(struct hs_usb_phy_reg *hs_phy_reg) +{ + write32(&hs_phy_reg->phy_dig->pwr_ctrl2, QUSB2PHY_PWR_CTRL2); + /* IMP_CTRL1: Control the impedance reduction */ + write32(&hs_phy_reg->phy_dig->imp_ctrl1, QUSB2PHY_IMP_CTRL1); + /* IMP_CTRL2: Impedance offset/mapping slope */ + write32(&hs_phy_reg->phy_dig->imp_ctrl2, QUSB2PHY_IMP_CTRL1); + write32(&hs_phy_reg->phy_dig->chg_ctrl2, QUSB2PHY_IMP_CTRL2); + /* + * TUNE1: Sets HS Impedance to approx 45 ohms + * then override with efuse value. + */ + write32(&hs_phy_reg->phy_dig->tune1, QUSB2PHY_PORT_TUNE1); + /* TUNE2: Tuning for HS Disconnect Level */ + write32(&hs_phy_reg->phy_dig->tune2, QUSB2PHY_PORT_TUNE2); + /* TUNE3: Tune squelch range */ + write32(&hs_phy_reg->phy_dig->tune3, QUSB2PHY_PORT_TUNE3); + /* TUNE4: Sets EOP_DLY(Squelch rising edge to linestate falling edge) */ + write32(&hs_phy_reg->phy_dig->tune4, QUSB2PHY_PORT_TUNE4); + write32(&hs_phy_reg->phy_dig->tune5, QUSB2PHY_PORT_TUNE5); + + if (hs_phy_reg->board_data) { + /* Override board specific PHY tuning values */ + qusb2_phy_override_phy_params(hs_phy_reg); + + /* Set efuse value for tuning the PHY */ + qusb2_phy_set_tune_param(hs_phy_reg); + } +} + +void hs_usb_phy_init(struct usb_board_data *board_data) +{ + struct hs_usb_phy_reg *hs_phy_reg; + + hs_phy_reg = &qusb_phy; + + hs_phy_reg->board_data = board_data; + + /* PWR_CTRL: set the power down bit to disable the PHY */ + + setbits32(&hs_phy_reg->phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&hs_phy_reg->phy_pll->analog_controls_two, + QUSB2PHY_PLL_ANALOG_CONTROLS_TWO); + write32(&hs_phy_reg->phy_pll->clock_inverters, + QUSB2PHY_PLL_CLOCK_INVERTERS); + write32(&hs_phy_reg->phy_pll->cmode, + QUSB2PHY_PLL_CMODE); + write32(&hs_phy_reg->phy_pll->lock_delay, + QUSB2PHY_PLL_LOCK_DELAY); + write32(&hs_phy_reg->phy_pll->dig_tim, + QUSB2PHY_PLL_DIGITAL_TIMERS_TWO); + write32(&hs_phy_reg->phy_pll->bias_ctrl_1, + QUSB2PHY_PLL_BIAS_CONTROL_1); + write32(&hs_phy_reg->phy_pll->bias_ctrl_2, + QUSB2PHY_PLL_BIAS_CONTROL_2); + + tune_phy(hs_phy_reg); + + /* PWR_CTRL1: Clear the power down bit to enable the PHY */ + clrbits32(&hs_phy_reg->phy_dig->pwr_ctrl1, POWER_DOWN); + + write32(&hs_phy_reg->phy_dig->debug_ctrl2, + DEBUG_CTRL2_MUX_PLL_LOCK_STATUS); + + /* + * DEBUG_STAT5: wait for 160uS for PLL lock; + * vstatus[0] changes from 0 to 1. + */ + long lock_us = wait_us(160, read32(&hs_phy_reg->phy_dig->debug_stat5) & + VSTATUS_PLL_LOCK_STATUS_MASK); + if (!lock_us) + printk(BIOS_ERR, "ERROR: QUSB PHY PLL LOCK fails\n"); + else + printk(BIOS_DEBUG, "QUSB PHY initialized and locked in %ldus\n", + lock_us); +} diff --git a/src/soc/qualcomm/common/usb/snps_usb_phy.c b/src/soc/qualcomm/common/usb/snps_usb_phy.c new file mode 100644 index 0000000..1a901bb --- /dev/null +++ b/src/soc/qualcomm/common/usb/snps_usb_phy.c @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/usb/snps_usb_phy.h> +#include <soc/addressmap.h> + +struct hs_usb_phy_reg *hs_phy_reg = (void *)HS_USB_PRIM_PHY_BASE; + +static void qcom_snps_hsphy_write_mask(u32 *offset, u32 mask, u32 val) +{ + u32 reg; + + reg = read32(offset); + reg &= ~mask; + reg |= val & mask; + write32(offset, reg); +} + +void hs_usb_phy_init(void) +{ + qcom_snps_hsphy_write_mask(&hs_phy_reg->cfg0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN); + qcom_snps_hsphy_write_mask(&hs_phy_reg->utmi_ctrl5, + POR, POR); + qcom_snps_hsphy_write_mask(&hs_phy_reg->hs_phy_ctrl_common0, + FSEL_MASK, 0); + qcom_snps_hsphy_write_mask(&hs_phy_reg->hs_phy_ctrl_common1, + PLLBTUNE, PLLBTUNE); + qcom_snps_hsphy_write_mask(&hs_phy_reg->refclk_ctrl, + REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); + qcom_snps_hsphy_write_mask(&hs_phy_reg->hs_phy_ctrl_common1, + VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); + qcom_snps_hsphy_write_mask(&hs_phy_reg->hs_phy_ctrl1, + VBUSVLDEXT0, VBUSVLDEXT0); + + qcom_snps_hsphy_write_mask(&hs_phy_reg->hs_phy_ctrl_common2, + VREGBYPASS, VREGBYPASS); + + qcom_snps_hsphy_write_mask(&hs_phy_reg->hs_phy_ctrl2, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, + USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); + + qcom_snps_hsphy_write_mask(&hs_phy_reg->utmi_ctrl0, + SLEEPM, SLEEPM); + + qcom_snps_hsphy_write_mask(&hs_phy_reg->utmi_ctrl5, + POR, 0); + + qcom_snps_hsphy_write_mask(&hs_phy_reg->hs_phy_ctrl2, + USB2_SUSPEND_N_SEL, 0); + + qcom_snps_hsphy_write_mask(&hs_phy_reg->cfg0, + UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); + + printk(BIOS_DEBUG, "USB HS PHY initialized\n"); +} diff --git a/src/soc/qualcomm/common/usb/usb.c b/src/soc/qualcomm/common/usb/usb.c new file mode 100644 index 0000000..45ccc33 --- /dev/null +++ b/src/soc/qualcomm/common/usb/usb.c @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/usb/usb_common.h> +#include <soc/addressmap.h> +#include <soc/clock.h> + +struct usb_dwc3 { + u32 sbuscfg0; + u32 sbuscfg1; + u32 txthrcfg; + u32 rxthrcfg; + u32 ctl; + u32 pmsts; + u32 sts; + u32 uctl1; + u32 snpsid; + u32 gpio; + u32 uid; + u32 uctl; + u64 buserraddr; + u64 prtbimap; + u8 reserved1[32]; + u32 dbgfifospace; + u32 dbgltssm; + u32 dbglnmcc; + u32 dbgbmu; + u32 dbglspmux; + u32 dbglsp; + u32 dbgepinfo0; + u32 dbgepinfo1; + u64 prtbimap_hs; + u64 prtbimap_fs; + u8 reserved2[112]; + u32 usb2phycfg; + u8 reserved3[124]; + u32 usb2phyacc; + u8 reserved4[60]; + u32 usb3pipectl; + u8 reserved5[60]; +}; +check_member(usb_dwc3, usb2phycfg, 0x100); +check_member(usb_dwc3, usb3pipectl, 0x1c0); + +struct usb_dwc3_cfg { + struct usb_dwc3 *usb_host_dwc3; + u32 *usb3_bcr; + u32 *qusb2phy_bcr; + u32 *gcc_usb3phy_bcr_reg; + u32 *gcc_qmpphy_bcr_reg; +}; + +static struct usb_dwc3_cfg usb_port0 = { + .usb_host_dwc3 = (void *)USB_HOST_DWC3_BASE, + .usb3_bcr = &gcc->usb30_prim_bcr, + .qusb2phy_bcr = &gcc->qusb2phy_prim_bcr, + .gcc_usb3phy_bcr_reg = &gcc->usb3_dp_phy_prim_bcr, + .gcc_qmpphy_bcr_reg = &gcc->usb3_phy_prim_bcr, +}; + +static void reset_usb(struct usb_dwc3_cfg *dwc3) +{ + /* Assert Core reset */ + clock_reset_bcr(dwc3->usb3_bcr, 1); + + /* Assert HS PHY reset */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 1); + + /* Assert QMP PHY reset */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 1); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 1); +} + +void reset_usb0(void) +{ + /* Before Resetting PHY, put Core in Reset */ + printk(BIOS_INFO, "Starting DWC3 and PHY resets for USB(0)\n"); + + reset_usb(&usb_port0); +} + +static void setup_dwc3(struct usb_dwc3 *dwc3) +{ + /* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */ + clrsetbits32(&dwc3->usb3pipectl, + DWC3_GUSB3PIPECTL_DELAYP1TRANS, + DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX); + + /* + * Configure USB phy interface of DWC3 core. + * 1. Select UTMI+ PHY with 16-bit interface. + * 2. Set USBTRDTIM to the corresponding value + * according to the UTMI+ PHY interface. + */ + clrsetbits32(&dwc3->usb2phycfg, + (DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK | + DWC3_GUSB2PHYCFG_PHYIF_MASK), + (DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) | + DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT))); + + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK | + DWC3_GCTL_DISSCRAMBLE), + DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG); + + /* configure controller in Host mode */ + clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)), + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST)); + printk(BIOS_SPEW, "Configure USB in Host mode\n"); +} + +/* Initialization of DWC3 Core and PHY */ + +#if CONFIG(QUSB_PHY) +static void setup_usb_host(struct usb_dwc3_cfg *dwc3, + struct usb_board_data *board_data) +#elif CONFIG(SNPS_USB_PHY) +static void setup_usb_host(struct usb_dwc3_cfg *dwc3) +#endif +{ + /* Clear core reset. */ + clock_reset_bcr(dwc3->usb3_bcr, 0); + + /* Clear QUSB PHY reset. */ + clock_reset_bcr(dwc3->qusb2phy_bcr, 0); + + /* Initialize HS PHY */ + #if CONFIG(QUSB_PHY) + hs_usb_phy_init(board_data); + #elif CONFIG(SNPS_USB_PHY) + hs_usb_phy_init(); + #endif + + /* Clear QMP PHY resets. */ + clock_reset_bcr(dwc3->gcc_usb3phy_bcr_reg, 0); + clock_reset_bcr(dwc3->gcc_qmpphy_bcr_reg, 0); + + /* Initialize QMP PHY */ + ss_qmp_phy_init(); + + setup_dwc3(dwc3->usb_host_dwc3); + + printk(BIOS_INFO, "DWC3 and PHY setup finished\n"); +} +#if CONFIG(QUSB_PHY) +void setup_usb_host0(struct usb_board_data *board_data) +#elif CONFIG(SNPS_USB_PHY) +void setup_usb_host0(void) +#endif +{ + printk(BIOS_INFO, "Setting up USB HOST0 controller.\n"); + #if CONFIG(QUSB_PHY) + setup_usb_host(&usb_port0, board_data); + #elif CONFIG(SNPS_USB_PHY) + setup_usb_host(&usb_port0); + #endif +} -- To view, visit https://review.coreboot.org/c/coreboot/+/56091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013ded22855286220cfa747cb25418070fe85a7 Gerrit-Change-Number: 56091 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: Add CPUCP firmware support
by Ravi kumar (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49768 to look at the new patch set (#53). Change subject: sc7280: Add CPUCP firmware support ...................................................................... sc7280: Add CPUCP firmware support CPUCP is CPUSS Control Processor. It refers to the firmware for control CPUSS active power management. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/cpucp_load_reset.c A src/soc/qualcomm/sc7280/include/soc/cpucp.h M src/soc/qualcomm/sc7280/soc.c 5 files changed, 71 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49768/53 -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 53 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: Add SHRM firmware support
by Ravi kumar (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49392 to look at the new patch set (#54). Change subject: sc7280: Add SHRM firmware support ...................................................................... sc7280: Add SHRM firmware support SHRM is a system hardware resource manager. It is used to manage run time DDRSS activities. DDRSS stands for DDR subsystem. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board by trying DDR clocks which through SHRM RSI command. Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/mainboard/google/herobrine/romstage.c M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/include/soc/shrm.h M src/soc/qualcomm/sc7280/memlayout.ld A src/soc/qualcomm/sc7280/shrm_load_reset.c 6 files changed, 36 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/49392/54 -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 54 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: Initialize SPI FW for EC and TPM
by Ravi kumar (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50581 to look at the new patch set (#52). Change subject: sc7280: Initialize SPI FW for EC and TPM ...................................................................... sc7280: Initialize SPI FW for EC and TPM Initialize SPI firmware for EC and H1/TPM instances. Load QUP FW in respective Serial Engines. BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/mainboard/google/herobrine/bootblock.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/50581/52 -- To view, visit https://review.coreboot.org/c/coreboot/+/50581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cbdd1d59a0166688d52d61646db1b6764879a7c Gerrit-Change-Number: 50581 Gerrit-PatchSet: 52 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: herobrine: sc7280: Load GSI FW in ramstage
by Ravi kumar (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55964 to look at the new patch set (#4). Change subject: herobrine: sc7280: Load GSI FW in ramstage ...................................................................... herobrine: sc7280: Load GSI FW in ramstage Load GSI FW in ramstage and make it part of RW As part of the code clean up, update the header files of the QUP drivers with the correct path. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board. Signed-off-by: Rajesh Patil <rajpat(a)codeaurora.org> Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30 --- M src/mainboard/google/herobrine/bootblock.c M src/mainboard/google/herobrine/mainboard.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/55964/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30 Gerrit-Change-Number: 55964 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit July 2021