coreboot-gerrit July 2021

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Change in coreboot[master]: mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Sean Rhodes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56088 ) Change subject: mainboard: Add Star Labs labtop series ...................................................................... Patch Set 6: (2 comments) File src/mainboard/starlabs/labtop/variants/cml/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123463): https://review.coreboot.org/c/coreboot/+/56088/comment/27338918_74b1e8b2 PS6, Line 106: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); line over 96 characters File src/mainboard/starlabs/labtop/variants/tgl/devtree.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123463): https://review.coreboot.org/c/coreboot/+/56088/comment/fb4f4e41_7db4ac9b PS6, Line 13: // TODO: TGL needs power_limits_config[POWER_LIMITS_U_2_CORE] and power_limits_config[POWER_LIMITS_U_4_CORE] line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/56088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 Gerrit-Change-Number: 56088 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Mon, 05 Jul 2021 19:46:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK
by build bot (Jenkins) (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode for SKU1 and SKU2 HACK ...................................................................... Patch Set 54: (2 comments) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123454): https://review.coreboot.org/c/coreboot/+/50586/comment/ce457c55_e767a4fa PS54, Line 508: while (1) suspect code indent for conditional statements (24, 24) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123454): https://review.coreboot.org/c/coreboot/+/50586/comment/603a834d_1a69d0ed PS54, Line 529: while (1) suspect code indent for conditional statements (24, 24) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 54 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 19:44:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard: Add Star Labs labtop series
by Sean Rhodes (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Sean Rhodes. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56088 ) Change subject: mainboard: Add Star Labs labtop series ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/56088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 Gerrit-Change-Number: 56088 Gerrit-PatchSet: 6 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Mon, 05 Jul 2021 19:43:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add PCIe RC driver in Coreboot
by build bot (Jenkins) (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, Julius Werner, Prasad Malisetty, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe RC driver in Coreboot ...................................................................... Patch Set 21: (1 comment) File src/soc/qualcomm/sc7280/include/soc/pcie.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123447): https://review.coreboot.org/c/coreboot/+/53902/comment/b098b428_e396ce1a PS21, Line 168: #define PCIE_DEV_FUNC (dev, func) {(PCI_SLOT(devfn)) | (PCI_FUNC(devfn))} Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 21 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 19:42:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: herobrine: sc7280: Load GSI FW in ramstage
by build bot (Jenkins) (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55964 ) Change subject: herobrine: sc7280: Load GSI FW in ramstage ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/herobrine/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123444): https://review.coreboot.org/c/coreboot/+/55964/comment/925cb04d_ed1e55c3 PS4, Line 16: trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/55964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d9caa0921fcf9ad67f1071cdf769a99fb6d1a30 Gerrit-Change-Number: 55964 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Rajesh Patil <rajpat(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Roja Rani Yarubandi <c_rojay(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 19:41:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]cpu/x86/64bit: Turn jumping to long mode into a macro
by Arthur Heymans (Code Review) 05 Jul '21

05 Jul '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56095 ) Change subject: [RFC]cpu/x86/64bit: Turn jumping to long mode into a macro ...................................................................... [RFC]cpu/x86/64bit: Turn jumping to long mode into a macro This makes it easier to reuse, e.g. if you want to do it twice in one assembly file. Also having the .code64 explicit instead of inside the included file provides more clarity. Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/64bit/mode_switch.S M src/cpu/x86/lapic/secondary.S M src/cpu/x86/sipi_vector.S M src/cpu/x86/smm/smm_stub.S M src/cpu/x86/smm/smmhandler.S M src/soc/intel/common/block/cpu/car/cache_as_ram.S 10 files changed, 40 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/56095/1 diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 0451bb4..c5e39c7 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -3,6 +3,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/64bit/entry64.inc> #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e @@ -211,9 +212,9 @@ andl $0xfffffff0, %esp #if ENV_X86_64 - - #include <cpu/x86/64bit/entry64.inc> - + setup_longmode 1f +.code64 +1: movd %mm2, %rdi shlq $32, %rdi movd %mm1, %rsi diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 9ac9e22..9e1478e 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -12,6 +12,7 @@ .global bootblock_pre_c_entry #include <cpu/intel/car/cache_as_ram_symbols.inc> +#include <cpu/x86/64bit/entry64.inc> .code32 _cache_as_ram_setup: @@ -360,8 +361,9 @@ subl $4, %esp #if ENV_X86_64 - #include <cpu/x86/64bit/entry64.inc> - + setup_longmode 1f +.code64 +1: movd %mm2, %rdi shlq $32, %rdi /* BIST */ movd %mm1, %rsi diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 07f848a..6fa6b28 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cpu/x86/post_code.h> +#include <cpu/x86/64bit/entry64.inc> #define CBFS_FILE_MAGIC 0 #define CBFS_FILE_LEN (CBFS_FILE_MAGIC + 8) @@ -79,11 +80,11 @@ /* Align the stack and keep aligned for call to bootblock_c_entry() */ and $0xfffffff0, %esp - /* entry64.inc preserves ebx. */ -#include <cpu/x86/64bit/entry64.inc> - /* Restore the BIST result and timestamps. */ #if defined(__x86_64__) + setup_longmode 1f +.code64 +1: movd %mm2, %rdi shlq $32, %rdi movd %mm1, %rsi diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 7025517..d1e133c 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -22,8 +22,7 @@ #include <arch/rom_segs.h> #endif - -setup_longmode: +.macro setup_longmode jmp_addr /* Get page table address */ movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax @@ -48,12 +47,11 @@ /* use long jump to switch to 64-bit code segment */ #if defined(__RAMSTAGE__) - ljmp $RAM_CODE_SEG64, $__longmode_start + ljmp $RAM_CODE_SEG64, $\jmp_addr #else - ljmp $ROM_CODE_SEG64, $__longmode_start + ljmp $ROM_CODE_SEG64, $\jmp_addr #endif -.code64 -__longmode_start: +.endm #endif diff --git a/src/cpu/x86/64bit/mode_switch.S b/src/cpu/x86/64bit/mode_switch.S index eea104b..d217817 100644 --- a/src/cpu/x86/64bit/mode_switch.S +++ b/src/cpu/x86/64bit/mode_switch.S @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cpu/x86/64bit/entry64.inc> .text .code64 @@ -51,7 +52,9 @@ movl %eax, %ebx /* Preserves ebx */ - #include <cpu/x86/64bit/entry64.inc> + setup_longmode continue +.code64 +continue: /* Place return value in rax */ movl %ebx, %eax diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S index d36bc9a..b12d078 100644 --- a/src/cpu/x86/lapic/secondary.S +++ b/src/cpu/x86/lapic/secondary.S @@ -2,6 +2,7 @@ #include <cpu/x86/lapic_def.h> #include <arch/ram_segs.h> +#include <cpu/x86/64bit/entry64.inc> .text .globl _secondary_start, _secondary_start_end, _secondary_gdt_addr @@ -60,7 +61,9 @@ #if ENV_X86_64 /* entry64.inc preserves ebx. */ - #include <cpu/x86/64bit/entry64.inc> + setup_longmode 1f +.code64 +1: movabs secondary_stack, %rax mov %rax, %rsp andl $0xfffffff0, %esp diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index d8156b8..ca7dcb4 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -6,6 +6,7 @@ #include <arch/ram_segs.h> #define __RAMSTAGE__ +#include <cpu/x86/64bit/entry64.inc> /* The SIPI vector is responsible for initializing the APs in the system. It * loads microcode, sets up MSRs, and enables caching before calling into @@ -216,8 +217,9 @@ #ifdef __x86_64__ /* entry64.inc preserves ebx. */ -#include <cpu/x86/64bit/entry64.inc> - + setup_longmode 1f +.code64 +1: mov %rsi, %rdi /* cpu_num */ movabs c_handler, %eax diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 07be047..a4ac47a 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -12,6 +12,7 @@ #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic_def.h> +#include <cpu/x86/64bit/entry64.inc> .code32 .section ".module_parameters", "aw", @progbits @@ -194,7 +195,9 @@ movl %edx, -0xc(%ebp) /* entry64.inc preserves ebx, esi, edi */ -#include <cpu/x86/64bit/entry64.inc> + setup_longmode 1f +.code64 +1: mov %edi, %ecx #endif diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 3750e52..9328f79 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -9,6 +9,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> +#include <cpu/x86/64bit/entry64.inc> /* * +--------------------------------+ 0xaffff @@ -174,8 +175,9 @@ movl %edx, ia32efer_backup_edx /* Enable long mode. Preserves ebx. */ -#include <cpu/x86/64bit/entry64.inc> - + setup_longmode 1f +.code64 +1: #endif /* Call C handler */ call smi_handler diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 74957ab..3344d38 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -9,6 +9,7 @@ #include <cpu/x86/post_code.h> #include <rules.h> #include <intelblocks/msr.h> +#include <cpu/x86/64bit/entry64.inc> .section .init, "ax", @progbits @@ -278,7 +279,9 @@ andl $0xfffffff0, %esp #if ENV_X86_64 - #include <cpu/x86/64bit/entry64.inc> + setup_longmode 1f +.code64 +1: movd %mm2, %rdi shlq $32, %rdi movd %mm1, %rsi -- To view, visit https://review.coreboot.org/c/coreboot/+/56095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida861338004187e4e714be41e17c8447fa4cf935 Gerrit-Change-Number: 56095 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/car/p4: Add x86_64 support
by Arthur Heymans (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Nico Huber, Paul Menzel, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56021 ) Change subject: cpu/intel/car/p4: Add x86_64 support ...................................................................... Patch Set 5: (2 comments) File src/cpu/intel/car/p4-netburst/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/56021/comment/5645b62c_ee568bb2 PS4, Line 363: > Remove the blank line as below? The indentation should help enough for readability. Done https://review.coreboot.org/c/coreboot/+/56021/comment/ca4929b5_463a7425 PS4, Line 365: > Please add a similar comment as below. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Gerrit-Change-Number: 56021 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 19:36:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/intel/car/p4: Add x86_64 support
by Arthur Heymans (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Hello build bot (Jenkins), Nico Huber, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56021 to look at the new patch set (#5). Change subject: cpu/intel/car/p4: Add x86_64 support ...................................................................... cpu/intel/car/p4: Add x86_64 support Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/56021/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Gerrit-Change-Number: 56021 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS
by Sean Rhodes (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Sean Rhodes, SRIDHAR SIRICILLA, Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Angel Pons, Sridhar Siricilla, Patrick Rudolph. Hello build bot (Jenkins), SRIDHAR SIRICILLA, Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52800 to look at the new patch set (#50). Change subject: soc/intel: Allow enable/disable ME via CMOS ...................................................................... soc/intel: Allow enable/disable ME via CMOS Added .enable method that will set the CSME state. State is based on me_state, with values of 0 and 1. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 119 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/52800/50 -- To view, visit https://review.coreboot.org/c/coreboot/+/52800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20 Gerrit-Change-Number: 52800 Gerrit-PatchSet: 50 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: SRIDHAR SIRICILLA Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Attention: SRIDHAR SIRICILLA Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: herobrine: get boardid from GPIO configuration
by Ravi Kumar Bokka (Code Review) 05 Jul '21

05 Jul '21

Attention is currently required from: Ravi kumar, Paul Menzel. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55950 ) Change subject: herobrine: get boardid from GPIO configuration ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55950/comment/bdd9eeea_25b02312 PS2, Line 7: sc7280 > Please use the board name in the prefix. Done https://review.coreboot.org/c/coreboot/+/55950/comment/6aaae4b3_30cc845b PS2, Line 9: boarid > board Done https://review.coreboot.org/c/coreboot/+/55950/comment/03a899f8_ed1c956e PS2, Line 9: varients > variants Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b7625f9b98563438d1ac20e6f29411ef1058cf4 Gerrit-Change-Number: 55950 Gerrit-PatchSet: 3 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 05 Jul 2021 18:43:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit July 2021