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Change subject: cpu/intel/car/p4: Add x86_64 support
......................................................................
Patch Set 5:
(2 comments)
File src/cpu/intel/car/p4-netburst/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/56021/comment/5645b62c_ee568bb2
PS4, Line 363:
> Remove the blank line as below? The indentation should help enough for readability.
Done
https://review.coreboot.org/c/coreboot/+/56021/comment/ca4929b5_463a7425
PS4, Line 365:
> Please add a similar comment as below.
Done
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Change subject: cpu/intel/car/p4: Add x86_64 support
......................................................................
cpu/intel/car/p4: Add x86_64 support
Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
1 file changed, 11 insertions(+), 0 deletions(-)
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Change subject: soc/intel: Allow enable/disable ME via CMOS
......................................................................
soc/intel: Allow enable/disable ME via CMOS
Added .enable method that will set the CSME state.
State is based on me_state, with values of 0 and 1.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
---
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Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55950 )
Change subject: herobrine: get boardid from GPIO configuration
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55950/comment/bdd9eeea_25b02312
PS2, Line 7: sc7280
> Please use the board name in the prefix.
Done
https://review.coreboot.org/c/coreboot/+/55950/comment/6aaae4b3_30cc845b
PS2, Line 9: boarid
> board
Done
https://review.coreboot.org/c/coreboot/+/55950/comment/03a899f8_ed1c956e
PS2, Line 9: varients
> variants
Done
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Change subject: sc7280: Add SHRM firmware support
......................................................................
Patch Set 54:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49392/comment/331583cf_cc9f8089
PS50, Line 9: It use to
> It is used to
Done
https://review.coreboot.org/c/coreboot/+/49392/comment/8fbcc3cd_e85b680c
PS50, Line 9: manager,
> Dot/period instead of comma.
Done
https://review.coreboot.org/c/coreboot/+/49392/comment/4f6c60d2_4ffb4b5d
PS50, Line 10: DDRSS activities.
> Please add more details, what DDRSS is.
Done
https://review.coreboot.org/c/coreboot/+/49392/comment/d7ee797f_1cf3cc7a
PS50, Line 13: TEST=Validated on qualcomm sc7280 development board
> How?
Done
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Change subject: IMOK: Add IMOK method support for DPTF
......................................................................
Patch Set 3:
(2 comments)
File src/ec/google/chromeec/acpi/ec.asl:
https://review.coreboot.org/c/coreboot/+/54688/comment/11efadae_b4f24f22
PS1, Line 262: DPTF
> Sure, will add appropriate config checks as per comment.
Ack
https://review.coreboot.org/c/coreboot/+/54688/comment/c36e5273_0a138f21
PS1, Line 264: 0xA0
> I'll check on how to use #define in this .asl file.
Ack
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