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Change in coreboot[master]: vc/mediatek/mt8195: Improve DRAM driver
by Rex-BC Chen (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Ryan Chuang. Hello Ryan Chuang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56099 to review the following change. Change subject: vc/mediatek/mt8195: Improve DRAM driver ...................................................................... vc/mediatek/mt8195: Improve DRAM driver 1. Improve settings of duty calibration. 2. Enable VREF calibration at DDR3200 for enter/exit S0 stability. 3. Enable DRAM Vcore DVFS settings. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: I8ae81bf26e3665e595721577794836ef39b55ef7 --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c M src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h 4 files changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/56099/1 diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index cea83a0..286e9a0 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -14804,9 +14804,15 @@ #endif #endif { + U8 u1ChannelIdx; + U8 u1backup_channel = vGetPHY2ChannelMapping(p); + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if(p->femmc_Ready==1) { + for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++){ + vSetPHY2ChannelMapping(p, u1ChannelIdx); + DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]); DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]); #if __LP5_COMBO__ @@ -14816,6 +14822,8 @@ DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM); DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ); #endif + } + vSetPHY2ChannelMapping(p, u1backup_channel); vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K); return; diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c index 71415d2..632a176 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c @@ -33,7 +33,7 @@ u8 ett_fix_freq = 0xff; // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733 DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = { - {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. + {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. {LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first. #if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION {LP4_DDR400 /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF, OPEN_LOOP_MODE}, @@ -272,7 +272,7 @@ #ifndef DDR_INIT_TIME_PROFILING print("Read voltage for %d, %d\n", p->frequency, vGet_Current_SRAMIdx(p)); - print("Vio18 = %d\n", dramc_get_vio18_voltage()); + //print("Vio18 = %d\n", dramc_get_vio18_voltage()); print("Vcore = %d\n", dramc_get_vcore_voltage()); print("Vdram = %d\n", dramc_get_vmdd_voltage(p->dram_type)); print("Vddq = %d\n", dramc_get_vmddq_voltage(p->dram_type)); diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c index 1595073..87a6040 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_top.c @@ -352,6 +352,9 @@ { #ifdef MTK_PMIC_MT6359 return mtk_regulator_set_voltage(&reg_vcore, vcore, MAX_VCORE); +#elif CONFIG(CHROMEOS) + dramc_debug("%s set vcore to %d\n", __func__, vcore); + mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore); #endif return 0; } diff --git a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h index a40f290..d27d7ea 100644 --- a/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h +++ b/src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h @@ -123,7 +123,7 @@ #else #define ENABLE_EYESCAN_GRAPH 1 #endif -#define EYESCAN_GRAPH_CATX_VREF_STEP 1 // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868 +#define EYESCAN_GRAPH_CATX_VREF_STEP 0x1U // 1 (origin), 2 (div 2)(save 9K size), 5 for A60868 #define EYESCAN_GRAPH_RX_VREF_STEP 2 #define EYESCAN_RX_VREF_RANGE_END 128 //field is 6 bit, but can only use 0~63,7bit ->127 #define EYESCAN_SKIP_UNTERM_CBT_EYESCAN_VREF 10 -- To view, visit https://review.coreboot.org/c/coreboot/+/56099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ae81bf26e3665e595721577794836ef39b55ef7 Gerrit-Change-Number: 56099 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Add dramc_param.h
by Rex-BC Chen (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Xi Chen, Hung-Te Lin, Ryan Chuang. Hello Ryan Chuang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/56098 to review the following change. Change subject: soc/mediatek/mt8195: Add dramc_param.h ...................................................................... soc/mediatek/mt8195: Add dramc_param.h The dramc_param.h defines the header version, structure and APIs for the DRAM calibration parameters stored on the flash, and should be platform independent. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e --- R src/soc/mediatek/mt8192/include/soc/dramc_param.h C src/soc/mediatek/mt8195/include/soc/dramc_param.h 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/56098/1 diff --git a/src/soc/mediatek/common/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h similarity index 96% rename from src/soc/mediatek/common/include/soc/dramc_param.h rename to src/soc/mediatek/mt8192/include/soc/dramc_param.h index 7794a73..7d6efda 100644 --- a/src/soc/mediatek/common/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_MEDIATEK_DRAMC_PARAM_H__ -#define __SOC_MEDIATEK_DRAMC_PARAM_H__ +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ /* * NOTE: This file is shared between coreboot and dram blob. Any change in this @@ -149,4 +149,4 @@ int validate_dramc_param(const void *blob); int is_valid_dramc_param(const void *blob); int initialize_dramc_param(void *blob); -#endif /* __SOC_MEDIATEK_DRAMC_PARAM_H__ */ +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/common/include/soc/dramc_param.h b/src/soc/mediatek/mt8195/include/soc/dramc_param.h similarity index 95% copy from src/soc/mediatek/common/include/soc/dramc_param.h copy to src/soc/mediatek/mt8195/include/soc/dramc_param.h index 7794a73..0e1b62c 100644 --- a/src/soc/mediatek/common/include/soc/dramc_param.h +++ b/src/soc/mediatek/mt8195/include/soc/dramc_param.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SOC_MEDIATEK_DRAMC_PARAM_H__ -#define __SOC_MEDIATEK_DRAMC_PARAM_H__ +#ifndef __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__ /* * NOTE: This file is shared between coreboot and dram blob. Any change in this @@ -12,7 +12,7 @@ #include <sys/types.h> #include <soc/dramc_soc.h> -#define DRAMC_PARAM_HEADER_VERSION 6 +#define DRAMC_PARAM_HEADER_VERSION 7 enum DRAMC_PARAM_STATUS_CODES { DRAMC_SUCCESS = 0, @@ -149,4 +149,4 @@ int validate_dramc_param(const void *blob); int is_valid_dramc_param(const void *blob); int initialize_dramc_param(void *blob); -#endif /* __SOC_MEDIATEK_DRAMC_PARAM_H__ */ +#endif /* __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/56098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e Gerrit-Change-Number: 56098 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Enable DCM
by Rex-BC Chen (Code Review) 06 Jul '21

06 Jul '21

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56097 ) Change subject: soc/mediatek/mt8195: Enable DCM ...................................................................... soc/mediatek/mt8195: Enable DCM Enable DCM settings on the MT8195 platform. DCM means dynamic clock management, and it can dynamically slow down or gate clocks during CPU or bus idle. Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce Signed-off-by: Garmin Chang <garmin.chang(a)mediatek.com> --- M src/soc/mediatek/mt8195/include/soc/pll.h M src/soc/mediatek/mt8195/pll.c 2 files changed, 62 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/56097/1 diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h index cc133c8..9b6f314f6 100644 --- a/src/soc/mediatek/mt8195/include/soc/pll.h +++ b/src/soc/mediatek/mt8195/include/soc/pll.h @@ -580,4 +580,45 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +enum { + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18), + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18), + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1 << 20) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 3) | + (0x0 << 4) | + (0x10 << 5) | + (0x1 << 20) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = (0xf << 0), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = (0x0 << 0), + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21), + INFRACFG_AO_PERI_BUS_DCM_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 3) | + (0x0 << 4) | + (0x1f << 5) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21), + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = (0x1 << 29) | (0x1 << 31), + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = (0x1 << 29) | (0x1 << 31), +}; + #endif /* SOC_MEDIATEK_MT8195_PLL_H */ diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index fc16535..ebdc37f 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -713,6 +713,27 @@ setbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, 0x3 << 21); setbits32(&mt8195_infracfg_ao_bcrm->vdnr_dcm_top_infra_ctrl0, 0x2); + /* dcm_infracfg_ao_aximem_bus_dcm */ + clrsetbits32(&mt8195_infracfg_ao->infra_aximem_idle_bit_en_0, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON); + /* dcm_infracfg_ao_infra_bus_dcm */ + clrsetbits32(&mt8195_infracfg_ao->infra_bus_dcm_ctrl, + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON); + /* dcm_infracfg_ao_infra_rx_p2p_dcm */ + clrsetbits32(&mt8195_infracfg_ao->p2p_rx_clk_on, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON); + /* dcm_infracfg_ao_peri_bus_dcm */ + clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, + INFRACFG_AO_PERI_BUS_DCM_REG0_ON); + /* dcm_infracfg_ao_peri_module_dcm */ + clrsetbits32(&mt8195_infracfg_ao->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON); + /* initialize SPM request */ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); -- To view, visit https://review.coreboot.org/c/coreboot/+/56097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce Gerrit-Change-Number: 56097 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by EricR Lai (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56074 to look at the new patch set (#5). Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... mb/google/brya: Add UsbTcPortEn in devicetree CB:2976591 add new parameter in FSP. Brya uses TCSS port 0/1/2, we need to enable it in devicetree. BUG=b:188481987 TEST=check typeC 3.0 works. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/tcss.h 4 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/56074/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 5 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by EricR Lai (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 ) Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: @Furquan, do you have comment? -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Jul 2021 04:56:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by EricR Lai (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 ) Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/include/intelblocks/tcss.h: https://review.coreboot.org/c/coreboot/+/56074/comment/d97bcd05_e83d6059 PS4, Line 101: > having this enum inside soc/alderlake/chip. […] I would like to use this #define TCSS_PORT(x) BIT((x)), like I did in PCI_RP and put in common code. SG? -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Jul 2021 04:56:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by Subrata Banik (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 ) Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/include/intelblocks/tcss.h: https://review.coreboot.org/c/coreboot/+/56074/comment/fe263785_9fdf957e PS4, Line 101: having this enum inside soc/alderlake/chip.h would help to understand the purpose of these macros as this are for FSP-UPD filling purpose. Assume we have more number of USB-C ports in next generation then, having such code in common place like this would tough to grow without any meaningful usage for previously generation platform. enum usbc_port_flags { TCSS_PORT0 = BIT(0), TCSS_PORT1 = BIT(1), TCSS_PORT2 = BIT(2), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Jul 2021 04:35:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by EricR Lai (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 ) Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/include/intelblocks/tcss.h: https://review.coreboot.org/c/coreboot/+/56074/comment/3d9153ad_6c451d0f PS3, Line 97: : #define TCSS_PORT_0 1 > my only concern is common code is not to fill in with FSP UPD related macros. […] #define TCSS_PORT(x) BIT(x)??? You mean this way or? why enum? -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 06 Jul 2021 04:25:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/voema: Remove stop delay time for ELAN TS
by YH Lin (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: David Wu, Nick Vaccaro. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56087 ) Change subject: mb/google/volteer/var/voema: Remove stop delay time for ELAN TS ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/56087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3 Gerrit-Change-Number: 56087 Gerrit-PatchSet: 2 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 06 Jul 2021 04:23:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add UsbTcPortEn in devicetree
by Subrata Banik (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 ) Change subject: mb/google/brya: Add UsbTcPortEn in devicetree ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/include/intelblocks/tcss.h: https://review.coreboot.org/c/coreboot/+/56074/comment/5eea2809_04297848 PS3, Line 97: : #define TCSS_PORT_0 1 > I saw TGL has the same define, shouldn't this a common define? This logic apply in all FSP, BIT0/1/2 […] my only concern is common code is not to fill in with FSP UPD related macros. i will let others also to comment on this, if chip.h itself is good enough. Also, may be an enum ? -- To view, visit https://review.coreboot.org/c/coreboot/+/56074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b Gerrit-Change-Number: 56074 Gerrit-PatchSet: 4 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Jul 2021 04:20:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit July 2021