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Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/tcss.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/3d9153ad_6c451d0f
PS3, Line 97:
: #define TCSS_PORT_0 1
> my only concern is common code is not to fill in with FSP UPD related macros. […]
#define TCSS_PORT(x) BIT(x)??? You mean this way or? why enum?
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Change subject: mb/google/volteer/var/voema: Remove stop delay time for ELAN TS
......................................................................
Patch Set 2: Code-Review+1
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Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/tcss.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/5eea2809_04297848
PS3, Line 97:
: #define TCSS_PORT_0 1
> I saw TGL has the same define, shouldn't this a common define? This logic apply in all FSP, BIT0/1/2 […]
my only concern is common code is not to fill in with FSP UPD related macros. i will let others also to comment on this, if chip.h itself is good enough. Also, may be an enum ?
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Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
mb/google/brya: Add UsbTcPortEn in devicetree
CB:2976591 add new parameter in FSP. Brya uses TCSS port 0/1/2,
we need to enable it in devicetree.
BUG=b:188481987
TEST=check typeC 3.0 works.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/tcss.h
4 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/56074/4
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Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/tcss.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/ccc2b485_80394329
PS3, Line 97:
: #define TCSS_PORT_0 1
> suggestion: […]
I saw TGL has the same define, shouldn't this a common define? This logic apply in all FSP, BIT0/1/2 etc for all devices like PCIE/USB etc..
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Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
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Patch Set 3:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/tcss.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/4fd91e98_b84b1547
PS3, Line 97:
: #define TCSS_PORT_0 1
suggestion:
#define TCSS_PORT0 BIT(0) ?
Also you can keep those as part of an enum inside chip.h because its not a register so better it stays inside FSP UPD related files rater in common code ?
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Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/56074/comment/3e275bef_86a53894
PS1, Line 62: 0x7
> can we have bit wise macro to make the code more readable please ?
Done
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Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
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Patch Set 3:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/13905fb7_5c60706d
PS1, Line 115: /*
> okay, I can clean up this tomorrow. […]
Done
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Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
mb/google/brya: Add UsbTcPortEn in devicetree
CB:2976591 add new parameter in FSP. Brya uses TCSS port 0/1/2,
we need to enable it in devicetree.
BUG=b:188481987
TEST=check typeC 3.0 works.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/tcss.h
4 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/56074/3
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Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/common/block/include/intelblocks/tcss.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123471):
https://review.coreboot.org/c/coreboot/+/56074/comment/c9e92265_e6d22dd7
PS2, Line 99: #define TCSS_PORT_1 1 << 1
Macros with complex values should be enclosed in parentheses
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123471):
https://review.coreboot.org/c/coreboot/+/56074/comment/0a9a26f3_69f9c882
PS2, Line 100: #define TCSS_PORT_2 1 << 2
Macros with complex values should be enclosed in parentheses
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