Attention is currently required from: Xi Chen, Hung-Te Lin, Ryan Chuang.
Hello Ryan Chuang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/56098
to review the following change.
Change subject: soc/mediatek/mt8195: Add dramc_param.h
......................................................................
soc/mediatek/mt8195: Add dramc_param.h
The dramc_param.h defines the header version,
structure and APIs for the DRAM calibration parameters
stored on the flash, and should be platform independent.
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e
---
R src/soc/mediatek/mt8192/include/soc/dramc_param.h
C src/soc/mediatek/mt8195/include/soc/dramc_param.h
2 files changed, 7 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/56098/1
diff --git a/src/soc/mediatek/common/include/soc/dramc_param.h b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
similarity index 96%
rename from src/soc/mediatek/common/include/soc/dramc_param.h
rename to src/soc/mediatek/mt8192/include/soc/dramc_param.h
index 7794a73..7d6efda 100644
--- a/src/soc/mediatek/common/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8192/include/soc/dramc_param.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SOC_MEDIATEK_DRAMC_PARAM_H__
-#define __SOC_MEDIATEK_DRAMC_PARAM_H__
+#ifndef __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__
+#define __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__
/*
* NOTE: This file is shared between coreboot and dram blob. Any change in this
@@ -149,4 +149,4 @@
int validate_dramc_param(const void *blob);
int is_valid_dramc_param(const void *blob);
int initialize_dramc_param(void *blob);
-#endif /* __SOC_MEDIATEK_DRAMC_PARAM_H__ */
+#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ */
diff --git a/src/soc/mediatek/common/include/soc/dramc_param.h b/src/soc/mediatek/mt8195/include/soc/dramc_param.h
similarity index 95%
copy from src/soc/mediatek/common/include/soc/dramc_param.h
copy to src/soc/mediatek/mt8195/include/soc/dramc_param.h
index 7794a73..0e1b62c 100644
--- a/src/soc/mediatek/common/include/soc/dramc_param.h
+++ b/src/soc/mediatek/mt8195/include/soc/dramc_param.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SOC_MEDIATEK_DRAMC_PARAM_H__
-#define __SOC_MEDIATEK_DRAMC_PARAM_H__
+#ifndef __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__
+#define __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__
/*
* NOTE: This file is shared between coreboot and dram blob. Any change in this
@@ -12,7 +12,7 @@
#include <sys/types.h>
#include <soc/dramc_soc.h>
-#define DRAMC_PARAM_HEADER_VERSION 6
+#define DRAMC_PARAM_HEADER_VERSION 7
enum DRAMC_PARAM_STATUS_CODES {
DRAMC_SUCCESS = 0,
@@ -149,4 +149,4 @@
int validate_dramc_param(const void *blob);
int is_valid_dramc_param(const void *blob);
int initialize_dramc_param(void *blob);
-#endif /* __SOC_MEDIATEK_DRAMC_PARAM_H__ */
+#endif /* __SOC_MEDIATEK_MT8195_DRAMC_PARAM_H__ */
--
To view, visit https://review.coreboot.org/c/coreboot/+/56098
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e
Gerrit-Change-Number: 56098
Gerrit-PatchSet: 1
Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com>
Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com>
Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org>
Gerrit-Attention: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Gerrit-MessageType: newchange
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56074
to look at the new patch set (#5).
Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
mb/google/brya: Add UsbTcPortEn in devicetree
CB:2976591 add new parameter in FSP. Brya uses TCSS port 0/1/2,
we need to enable it in devicetree.
BUG=b:188481987
TEST=check typeC 3.0 works.
Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com>
Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/tcss.h
4 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/56074/5
--
To view, visit https://review.coreboot.org/c/coreboot/+/56074
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
Gerrit-Change-Number: 56074
Gerrit-PatchSet: 5
Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Furquan Shaikh <furquan(a)google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newpatchset
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 )
Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
@Furquan, do you have comment?
--
To view, visit https://review.coreboot.org/c/coreboot/+/56074
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
Gerrit-Change-Number: 56074
Gerrit-PatchSet: 4
Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Furquan Shaikh <furquan(a)google.com>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Comment-Date: Tue, 06 Jul 2021 04:56:36 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Patrick Rudolph.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 )
Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/tcss.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/d97bcd05_e83d6059
PS4, Line 101:
> having this enum inside soc/alderlake/chip. […]
I would like to use this #define TCSS_PORT(x) BIT((x)), like I did in PCI_RP and put in common code. SG?
--
To view, visit https://review.coreboot.org/c/coreboot/+/56074
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
Gerrit-Change-Number: 56074
Gerrit-PatchSet: 4
Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Comment-Date: Tue, 06 Jul 2021 04:56:18 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-MessageType: comment
Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 )
Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/tcss.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/fe263785_9fdf957e
PS4, Line 101:
having this enum inside soc/alderlake/chip.h would help to understand the purpose of these macros as this are for FSP-UPD filling purpose.
Assume we have more number of USB-C ports in next generation then, having such code in common place like this would tough to grow without any meaningful usage for previously generation platform.
enum usbc_port_flags {
TCSS_PORT0 = BIT(0),
TCSS_PORT1 = BIT(1),
TCSS_PORT2 = BIT(2),
};
--
To view, visit https://review.coreboot.org/c/coreboot/+/56074
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
Gerrit-Change-Number: 56074
Gerrit-PatchSet: 4
Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Comment-Date: Tue, 06 Jul 2021 04:35:24 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Patrick Rudolph.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 )
Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/tcss.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/3d9153ad_6c451d0f
PS3, Line 97:
: #define TCSS_PORT_0 1
> my only concern is common code is not to fill in with FSP UPD related macros. […]
#define TCSS_PORT(x) BIT(x)??? You mean this way or? why enum?
--
To view, visit https://review.coreboot.org/c/coreboot/+/56074
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
Gerrit-Change-Number: 56074
Gerrit-PatchSet: 4
Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Comment-Date: Tue, 06 Jul 2021 04:25:02 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com>
Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-MessageType: comment
Attention is currently required from: David Wu, Nick Vaccaro.
YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56087 )
Change subject: mb/google/volteer/var/voema: Remove stop delay time for ELAN TS
......................................................................
Patch Set 2: Code-Review+1
--
To view, visit https://review.coreboot.org/c/coreboot/+/56087
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id326fd4d9d71eef171580b1c6001505e698b40a3
Gerrit-Change-Number: 56087
Gerrit-PatchSet: 2
Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: YH Lin <yueherngl(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com>
Gerrit-Comment-Date: Tue, 06 Jul 2021 04:23:05 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56074 )
Change subject: mb/google/brya: Add UsbTcPortEn in devicetree
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/tcss.h:
https://review.coreboot.org/c/coreboot/+/56074/comment/5eea2809_04297848
PS3, Line 97:
: #define TCSS_PORT_0 1
> I saw TGL has the same define, shouldn't this a common define? This logic apply in all FSP, BIT0/1/2 […]
my only concern is common code is not to fill in with FSP UPD related macros. i will let others also to comment on this, if chip.h itself is good enough. Also, may be an enum ?
--
To view, visit https://review.coreboot.org/c/coreboot/+/56074
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ibe9d3a6d1d73cb37daae4a1ae49ee26abc43635b
Gerrit-Change-Number: 56074
Gerrit-PatchSet: 4
Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-Comment-Date: Tue, 06 Jul 2021 04:20:24 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com>
Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com>
Gerrit-MessageType: comment