coreboot-gerrit July 2021

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Change in coreboot[master]: Kconfig: Simplify x86_64 Kconfig handling
by Patrick Rudolph (Code Review) 06 Jul '21

06 Jul '21

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55471 ) Change subject: Kconfig: Simplify x86_64 Kconfig handling ...................................................................... Abandoned Superseeded by CB:55759 -- To view, visit https://review.coreboot.org/c/coreboot/+/55471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I024226c88ef929c746254b8c2a71e0bdb9338b0e Gerrit-Change-Number: 55471 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Sean Rhodes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56088 ) Change subject: mainboard: Add Star Labs labtop series ...................................................................... Patch Set 8: (2 comments) File src/mainboard/starlabs/labtop/variants/cml/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123481): https://review.coreboot.org/c/coreboot/+/56088/comment/4805e1a9_2b4e535c PS8, Line 106: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); line over 96 characters File src/mainboard/starlabs/labtop/variants/tgl/devtree.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123481): https://review.coreboot.org/c/coreboot/+/56088/comment/71b51e66_35ba1a40 PS8, Line 13: // TODO: TGL needs power_limits_config[POWER_LIMITS_U_2_CORE] and power_limits_config[POWER_LIMITS_U_4_CORE] line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/56088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 Gerrit-Change-Number: 56088 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Tue, 06 Jul 2021 07:33:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by Kevin Chang (Code Review) 06 Jul '21

06 Jul '21

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56100 ) Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... grunt/treeya: add Realtek ALC5682 codec support ALC5682 i2c address: 0x1A BUG=b:185972050 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa --- M src/mainboard/google/kahlee/variants/treeya/Makefile.inc A src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/kahlee/variants/treeya/devicetree.cb A src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h 4 files changed, 98 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/56100/1 diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc index 21b0276..525e76c 100644 --- a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ./spd + +ramstage-y += audio.c diff --git a/src/mainboard/google/kahlee/variants/treeya/audio.c b/src/mainboard/google/kahlee/variants/treeya/audio.c new file mode 100644 index 0000000..e40ad57 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/audio.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> +#include <baseboard/variants.h> +#include <variant/sku.h> +#include <string.h> +#include <drivers/i2c/hid/chip.h> + +extern struct chip_operations drivers_i2c_generic_ops; +extern struct chip_operations drivers_i2c_da7219_ops; + +void variant_devtree_update(void) +{ + uint32_t sku = google_chromeec_get_sku_id(); + struct device *mmio_dev = NULL, *child = NULL; + struct device *alc_dev = NULL, *da7219_dev = NULL; + + while (1) { + mmio_dev = dev_find_path(mmio_dev, DEVICE_PATH_MMIO); + if (mmio_dev == NULL) + break; + if (mmio_dev->path.mmio.addr == 0xfedc2000) + break; + } + + if (mmio_dev == NULL) + return; + + while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { + if (child->path.type != DEVICE_PATH_I2C) + continue; + if (child->path.i2c.device != 0x1a) + continue; + if (child->chip_ops == &drivers_i2c_generic_ops) { + struct drivers_i2c_generic_config *config = child->chip_info; + if (!strcmp(config->hid, "10EC5682")) + alc_dev = child; + } else if (child->chip_ops == &drivers_i2c_da7219_ops) { + da7219_dev = child; + } + } + + switch (sku) { + default: + /* da7219 only */ + if (da7219_dev) + da7219_dev->enabled = 1; + if (alc_dev) + alc_dev->enabled = 0; + break; + case SKU_TREEYA_ALC5682_AE: + case SKU_TREEYA_ALC5682_AF: + /* alc5682 only */ + if (da7219_dev) + da7219_dev->enabled = 0; + if (alc_dev) + alc_dev->enabled = 1; + break; + } +} diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index 183e3dd..0050d80 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -110,6 +110,21 @@ register "mclk_name" = ""oscout1"" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_14)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h new file mode 100644 index 0000000..fd4fe34 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* SKU ID enumeration */ +enum treeya_sku { + SKU_UNKNOWN = -1, + SKU_TREEYA_ALC5682_AE = 174, + SKU_TREEYA_ALC5682_AF = 175, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: configs/config.foxconn_g41m: Build test with X86_64
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56042 ) Change subject: configs/config.foxconn_g41m: Build test with X86_64 ...................................................................... configs/config.foxconn_g41m: Build test with X86_64 Change-Id: I755f2037bc9368e610eb97a2633aa66da7f626b0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56042 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A configs/config.foxconn_g41m 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/configs/config.foxconn_g41m b/configs/config.foxconn_g41m new file mode 100644 index 0000000..f5deea5 --- /dev/null +++ b/configs/config.foxconn_g41m @@ -0,0 +1,3 @@ +CONFIG_VENDOR_FOXCONN=y +CONFIG_BOARD_FOXCONN_G41M=y +CONFIG_USE_EXP_X86_64_SUPPORT=y -- To view, visit https://review.coreboot.org/c/coreboot/+/56042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I755f2037bc9368e610eb97a2633aa66da7f626b0 Gerrit-Change-Number: 56042 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: configs/config.foxconn_g41m: Build test with X86_64
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Paul Menzel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56042 ) Change subject: configs/config.foxconn_g41m: Build test with X86_64 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/56042/comment/e559d25d_cf706425 PS1, Line 7: Buildtest > Nit: Build test Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I755f2037bc9368e610eb97a2633aa66da7f626b0 Gerrit-Change-Number: 56042 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 06 Jul 2021 06:11:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: configs/config.foxconn_g41m: Build test with X86_64
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56042 to look at the new patch set (#3). Change subject: configs/config.foxconn_g41m: Build test with X86_64 ...................................................................... configs/config.foxconn_g41m: Build test with X86_64 Change-Id: I755f2037bc9368e610eb97a2633aa66da7f626b0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A configs/config.foxconn_g41m 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/56042/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/56042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I755f2037bc9368e610eb97a2633aa66da7f626b0 Gerrit-Change-Number: 56042 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/x4x: Expose x86_64 support
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56022 ) Change subject: nb/intel/x4x: Expose x86_64 support ...................................................................... nb/intel/x4x: Expose x86_64 support TESTED on foxconn g41m. Change-Id: I2d5d5dfbd76a84aa400e44b4bc2ac4f3b5b6f739 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56022 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/x4x/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 3ebb4fa..476caf5 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -12,6 +12,7 @@ select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + select HAVE_EXP_X86_64_SUPPORT config CBFS_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/56022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d5d5dfbd76a84aa400e44b4bc2ac4f3b5b6f739 Gerrit-Change-Number: 56022 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/intel/car/p4: Add x86_64 support
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/56021 ) Change subject: cpu/intel/car/p4: Add x86_64 support ...................................................................... cpu/intel/car/p4: Add x86_64 support Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56021 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/intel/car/p4-netburst/cache_as_ram.S 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 71ec9e3..9ac9e22 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -359,6 +359,16 @@ andl $0xfffffff0, %esp subl $4, %esp +#if ENV_X86_64 + #include <cpu/x86/64bit/entry64.inc> + + movd %mm2, %rdi + shlq $32, %rdi /* BIST */ + movd %mm1, %rsi + or %rsi, %rdi /* tsc[63:32] */ + movd %mm0, %rsi /* tsc[31:0] */ + +#else /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -366,6 +376,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_c_entry: post_code(0x2f) -- To view, visit https://review.coreboot.org/c/coreboot/+/56021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77516e3cd5f0d3b7442be660c005a65b00454343 Gerrit-Change-Number: 56021 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86: Use ENV_X86_64 instead of _x86_64_
by Patrick Rudolph (Code Review) 06 Jul '21

06 Jul '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44867 ) Change subject: arch/x86: Use ENV_X86_64 instead of _x86_64_ ...................................................................... arch/x86: Use ENV_X86_64 instead of _x86_64_ Untested. Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/assembly_entry.S M src/arch/x86/boot.c M src/arch/x86/c_exit.S M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/cpu_common.c M src/arch/x86/exception.c M src/arch/x86/exit_car.S M src/arch/x86/gdt_init.S M src/arch/x86/idt.S M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/registers.h M src/arch/x86/memcpy.c M src/arch/x86/wakeup.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/smm/smm_stub.S M src/cpu/x86/smm/smmhandler.S M src/include/assert.h M src/include/cpu/x86/cr.h M src/soc/intel/denverton_ns/soc_util.c 22 files changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/44867/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 31670c2..6e73027 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -15,7 +15,7 @@ #define _STACK_TOP _ecar_stack #endif -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -26,7 +26,7 @@ _start: /* Migrate GDT to this text segment */ -#ifdef __x86_64__ +#if ENV_X86_64 call gdt_init64 #else call gdt_init diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index 777a0b7..31e7cee 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -21,14 +21,14 @@ void arch_prog_run(struct prog *prog) { -#if ENV_RAMSTAGE && defined(__x86_64__) +#if ENV_RAMSTAGE && ENV_X86_64 const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog)); const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog)); /* On x86 coreboot payloads expect to be called in protected mode */ protected_mode_jump(entry, arg); #else -#ifdef __x86_64__ +#if ENV_X86_64 void (*doit)(void *arg); #else /* Ensure the argument is pushed on the stack. */ diff --git a/src/arch/x86/c_exit.S b/src/arch/x86/c_exit.S index e5b9bf8..bb1df28 100644 --- a/src/arch/x86/c_exit.S +++ b/src/arch/x86/c_exit.S @@ -5,7 +5,7 @@ #include <cpu/x86/cr.h> -#ifdef __x86_64__ +#if ENV_X86_64 /* * Functions to handle mode switches from long mode to protected diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index c46a45c..47d6597 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -22,7 +22,7 @@ #endif .section ".text._start", "ax", @progbits -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -31,7 +31,7 @@ _start: cli lgdt %cs:gdtaddr -#ifndef __x86_64__ +#if ENV_X86_32 ljmp $RAM_CODE_SEG, $1f #endif 1: movl $RAM_DATA_SEG, %eax @@ -40,7 +40,7 @@ movl %eax, %ss movl %eax, %fs movl %eax, %gs -#ifdef __x86_64__ +#if ENV_X86_64 mov $RAM_CODE_SEG64, %ecx call SetCodeSelector #endif @@ -49,7 +49,7 @@ cld -#ifdef __x86_64__ +#if ENV_X86_64 mov %rdi, _cbmem_top_ptr #else /* The return argument is at 0(%esp), the calling argument at 4(%esp) */ @@ -110,7 +110,7 @@ .globl gdb_stub_breakpoint gdb_stub_breakpoint: -#ifdef __x86_64__ +#if ENV_X86_64 pop %rax /* Return address */ pushfl push %cs @@ -132,7 +132,7 @@ gdtaddr: .word gdt_end - gdt - 1 -#ifdef __x86_64__ +#if ENV_X86_64 .quad gdt #else .long gdt /* we know the offset */ @@ -169,7 +169,7 @@ /* selgdt 0x18, flat data segment */ .word 0xffff, 0x0000 -#ifdef __x86_64__ +#if ENV_X86_64 .byte 0x00, 0x92, 0xcf, 0x00 #else .byte 0x00, 0x93, 0xcf, 0x00 @@ -203,7 +203,7 @@ * limit */ -#ifdef __x86_64__ +#if ENV_X86_64 /* selgdt 0x48, flat x64 code segment */ .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0xaf, 0x00 @@ -211,7 +211,7 @@ gdt_end: .section ".text._start", "ax", @progbits -#ifdef __x86_64__ +#if ENV_X86_64 SetCodeSelector: # save rsp because iret will align it to a 16 byte boundary mov %rsp, %rdx diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index d054cfe..d44bd2f 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -14,7 +14,7 @@ #include <device/device.h> #include <smp/spinlock.h> -#ifndef __x86_64__ +#if ENV_X86_32 /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -137,7 +137,7 @@ vendor_name[0] = '\0'; /* Unset */ -#ifndef __x86_64__ +#if ENV_X86_32 /* Find the id and vendor_name */ if (!cpu_have_cpuid()) { /* Its a 486 if we can modify the AC flag */ diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 07de155..77d08c41 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -2,7 +2,7 @@ #include <cpu/cpu.h> -#ifndef __x86_64__ +#if ENV_X86_32 /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index f10c7bf..6c519c3 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -491,7 +491,7 @@ logical_processor = cpu_index(); #endif u8 *code; -#ifdef __x86_64__ +#if ENV_X86_64 #define MDUMP_SIZE 0x100 printk(BIOS_EMERG, "CPU Index %d - APIC %d Unexpected Exception:\n" diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index dc356b2..db36821 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -11,7 +11,7 @@ .long 0 .long 0 -#if defined(__x86_64__) +#if ENV_X86_64 .code64 .macro pop_eax_edx pop %rax @@ -42,13 +42,13 @@ is expected to be implemented in assembly. */ /* Migrate GDT to this text segment */ -#if defined(__x86_64__) +#if ENV_X86_64 call gdt_init64 #else call gdt_init #endif -#ifdef __x86_64__ +#if ENV_X86_64 mov %rdi, _cbmem_top_ptr #else /* The return argument is at 0(%esp), the calling argument at 4(%esp) */ @@ -67,7 +67,7 @@ call chipset_teardown_car /* Enable caching if not already enabled. */ -#ifdef __x86_64__ +#if ENV_X86_64 mov %cr0, %rax and $(~(CR0_CD | CR0_NW)), %eax mov %rax, %cr0 @@ -102,7 +102,7 @@ /* Need to align stack to 16 bytes at the call instruction. Therefore account for the 1 push. */ andl $0xfffffff0, %esp -#if defined(__x86_64__) +#if ENV_X86_64 mov %rbp, %rdi #else sub $12, %esp diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index 1558ac6..287f17b 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -15,7 +15,7 @@ .word gdt_end - gdt -1 /* compute the table limit */ .long gdt /* we know the offset */ -#ifdef __x86_64__ +#if ENV_X86_64 .code64 .section ".text._gdt64_", "ax", @progbits .globl gdt_init64 diff --git a/src/arch/x86/idt.S b/src/arch/x86/idt.S index 6807056..d763b9e 100644 --- a/src/arch/x86/idt.S +++ b/src/arch/x86/idt.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ .section ".text._idt", "ax", @progbits -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -109,7 +109,7 @@ .global int_hand int_hand: -#ifdef __x86_64__ +#if ENV_X86_64 /* At this point, on x86-64, on the stack there is: * 0(%rsp) vector * 8(%rsp) error code diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index b622465..e523fc0 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -236,7 +236,7 @@ { struct cpu_info *ci; __asm__( -#ifdef __x86_64__ +#if ENV_X86_64 "and %%rsp,%0; " "or %2, %0 " #else diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 5f8f9be..7043cd1 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -42,7 +42,7 @@ uint64_t r##A; \ } __packed -#ifdef __ARCH_x86_64__ +#if ENV_X86_64 struct eregs { QUAD_DOWNTO8(a); QUAD_DOWNTO8(c); diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 1cfdf89..93002cd 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -15,7 +15,7 @@ #endif asm volatile( -#ifdef __x86_64__ +#if ENV_X86_64 "rep ; movsd\n\t" "mov %4,%%rcx\n\t" #else diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index ae2efe0..dc9510b 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -6,7 +6,7 @@ /* CR0 bits */ #define PE (1 << 0) -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -14,7 +14,7 @@ .globl __wakeup __wakeup: -#ifdef __x86_64__ +#if ENV_X86_64 xor %rax,%rax mov %ss, %ax push %rax diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 415ed24..4489d2c 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -28,7 +28,7 @@ and $0xfffffff0, %esp /* Restore the BIST result and timestamps. */ -#if defined(__x86_64__) +#if ENV_X86_64 movd %mm2, %rdi shld %rdi, 32 movd %mm1, %rsi diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc..5049169 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -9,7 +9,7 @@ * Clobbers: eax, ecx, edx */ -#if defined(__x86_64__) +#if ENV_X86_64 .code32 #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 #error pagetables must be 4KiB aligned! diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index f89d9e3..342c86d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -39,7 +39,7 @@ static inline void setup_secondary_gdt(void) { u16 *gdt_limit; -#ifdef __x86_64__ +#if ENV_X86_64 u64 *gdt_base; #else u32 *gdt_base; diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 11ea9a7..dd902d7 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -178,7 +178,7 @@ /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp -#ifdef __x86_64__ +#if ENV_X86_64 mov %ecx, %edi /* Backup IA32_EFER. Preserves ebx. */ movl $(IA32_EFER), %ecx @@ -197,7 +197,7 @@ * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; * c_handler(&arg) */ -#ifdef __x86_64__ +#if ENV_X86_64 push %rbx /* uintptr_t *canary */ push $(smm_runtime) push %rcx /* size_t cpu */ diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 340840f..bb91cb1 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -43,7 +43,7 @@ #define SMM_HANDLER_OFFSET 0x0000 -#if defined(__x86_64__) +#if ENV_X86_64 .bss ia32efer_backup_eax: .long @@ -169,7 +169,7 @@ movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ subl %ebp, %ebx /* subtract core X offset */ -#if defined(__x86_64__) +#if ENV_X86_64 /* Backup IA32_EFER. Preserves ebx. */ movl $(IA32_EFER), %ecx rdmsr @@ -189,7 +189,7 @@ /* Call C handler */ call smi_handler -#if defined(__x86_64__) +#if ENV_X86_64 /* * The only reason to go back to protected mode is that RSM doesn't restore * MSR registers and MSR IA32_EFER was modified by entering long mode. diff --git a/src/include/assert.h b/src/include/assert.h index 944c677..27d7309 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -80,7 +80,7 @@ *(type *)(uintptr_t)0; \ }) -#ifdef __x86_64__ +#if ENV_X86_64 #define pointer_to_uint32_safe(x) ({ \ if ((uintptr_t)(x) > 0xffffffffUL) \ die("Cast from pointer to uint32_t overflows"); \ diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 3508505a..c70f35c 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -9,7 +9,7 @@ #define COMPILER_BARRIER "memory" -#ifdef __x86_64__ +#if ENV_X86_64 #define CRx_TYPE uint64_t #define CRx_IN "q" #define CRx_RET "=q" diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index d5b9b34..b4c707d 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -274,7 +274,7 @@ unsigned long d0, d1, d2; asm volatile( -#ifdef __x86_64__ +#if ENV_X86_64 "rep ; movsd\n\t" "mov %4,%%rcx\n\t" #else -- To view, visit https://review.coreboot.org/c/coreboot/+/44867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Gerrit-Change-Number: 44867 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 7

Change in coreboot[master]: Kconfig: Simplify x86_64 Kconfig handling
by Patrick Georgi (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Patrick Rudolph, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Andrey Petrov, Jason Glenesk, Anjaneya "Reddy" Chagam, Marshall Dawson, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Morgan Jang, Felix Held. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55471 ) Change subject: Kconfig: Simplify x86_64 Kconfig handling ...................................................................... Patch Set 7: (1 comment) File src/cpu/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/55471/comment/7e3e2767_d63dafe3 PS7, Line 199: config EXP_SUPPORT_ARCH_X86_64 EXP_ as in experimental, so you'll need a tree-wide pass to rename it once it's not experimental anymore? -- To view, visit https://review.coreboot.org/c/coreboot/+/55471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I024226c88ef929c746254b8c2a71e0bdb9338b0e Gerrit-Change-Number: 55471 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 06 Jul 2021 06:09:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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