coreboot-gerrit July 2021

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Change in coreboot[master]: vc/mediatek/mt8195: Improve DRAM driver
by Rex-BC Chen (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Ryan Chuang. Hello Hung-Te Lin, build bot (Jenkins), Ryan Chuang, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56099 to look at the new patch set (#2). Change subject: vc/mediatek/mt8195: Improve DRAM driver ...................................................................... vc/mediatek/mt8195: Improve DRAM driver 1. Improve settings of duty calibration. 2. Enable VREF calibration at DDR3200 for enter/exit S0 stability. 3. Enable DRAM Vcore DVFS settings. Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Change-Id: I8ae81bf26e3665e595721577794836ef39b55ef7 --- M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c M src/vendorcode/mediatek/mt8195/dramc/dramc_top.c M src/vendorcode/mediatek/mt8195/include/dramc_pi_api.h 4 files changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/56099/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ae81bf26e3665e595721577794836ef39b55ef7 Gerrit-Change-Number: 56099 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/mediatek/mt8195: Improve DRAM driver
by Yu-Ping Wu (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Ryan Chuang. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56099 ) Change subject: vc/mediatek/mt8195: Improve DRAM driver ...................................................................... Patch Set 1: (1 comment) File src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c: https://review.coreboot.org/c/coreboot/+/56099/comment/ae0bd97d_75774556 PS1, Line 275: //print("Vio18 = %d\n", dramc_get_vio18_voltage()); If we want to comment this out, please remove it. -- To view, visit https://review.coreboot.org/c/coreboot/+/56099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ae81bf26e3665e595721577794836ef39b55ef7 Gerrit-Change-Number: 56099 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 06 Jul 2021 08:22:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Add dramc_param.h
by Yu-Ping Wu (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56098 ) Change subject: soc/mediatek/mt8195: Add dramc_param.h ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e Gerrit-Change-Number: 56098 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Jul 2021 08:20:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Enable DCM
by Yu-Ping Wu (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Hung-Te Lin. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56097 ) Change subject: soc/mediatek/mt8195: Enable DCM ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/56097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib431a0334c157d440d6e89dcb154241d980d97ce Gerrit-Change-Number: 56097 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Jul 2021 08:19:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTONLY]do we use cbfs-relative base addresses as input??
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56044 to look at the new patch set (#5). Change subject: [TESTONLY]do we use cbfs-relative base addresses as input?? ...................................................................... [TESTONLY]do we use cbfs-relative base addresses as input?? If no-one is using this, we might as well get rid of it? Change-Id: I87349e98d6aeac5d3f79c8a067982cd136a0b863 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/cbfstool.c 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/56044/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/56044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87349e98d6aeac5d3f79c8a067982cd136a0b863 Gerrit-Change-Number: 56044 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: TESTONLY: Link pagetables into programs instead of using a cbfs file
by Arthur Heymans (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56096 ) Change subject: TESTONLY: Link pagetables into programs instead of using a cbfs file ...................................................................... Patch Set 1: (1 comment) File src/cpu/x86/64bit/pt.S: https://review.coreboot.org/c/coreboot/+/56096/comment/1138c642_9ec526a8 PS1, Line 14: .align 32 > This is the alignment relative to _program. Shouldn't all CBFS files using this assembly code then be aligned to 4096 as well? > > Does it work for bootblock where _eprogram is aligned to 4GiB instead of _program? So bootblock is a special program. It is linked at the address it gets executed, which means this just works. Other programs should be aligned to 4096, which would be cbfstool's job. Relocatable stages already have 4K runtime alignment afaict: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr…. So the only thing left to do is 4K alignment for early programs, especially those that are XIP. Anyway RO/part of program PT are not always needed. We might need to differentiate: - Some platforms have enough CAR that you could generate it in place - On Intel GLK, PT are copied from cbfs into CAR -> this could be probably be improved too - RAM stages could have the PT in DRAM: care needs to be taken in postcar, e.g. if PT are in CAR. I think with stages in DRAM you want the PT in .bss or .data an just put an identity table in there, either generated or static. - SMM is weird. You can't link a PT inside the stub, but the stub needs to know where it is: preferably inside the permanent handler or inside ramstage during relocation. That means a stub relocatable param pointing to it. - Sipi Vector in ramstage: you probably also want a pointer to the ramstage PT inside the relocatable params. -- To view, visit https://review.coreboot.org/c/coreboot/+/56096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice4fd15d131b8c91bc98afad7f459ce3485b786d Gerrit-Change-Number: 56096 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 06 Jul 2021 08:12:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: TESTONLY: Link pagetables into programs instead of using a cbfs file
by Patrick Rudolph (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56096 ) Change subject: TESTONLY: Link pagetables into programs instead of using a cbfs file ...................................................................... Patch Set 1: (1 comment) File src/cpu/x86/64bit/pt.S: https://review.coreboot.org/c/coreboot/+/56096/comment/1f697318_f3e876de PS1, Line 14: .align 32 This is the alignment relative to _program. Shouldn't all CBFS files using this assembly code then be aligned to 4096 as well? Does it work for bootblock where _eprogram is aligned to 4GiB instead of _program? -- To view, visit https://review.coreboot.org/c/coreboot/+/56096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice4fd15d131b8c91bc98afad7f459ce3485b786d Gerrit-Change-Number: 56096 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 06 Jul 2021 07:48:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Kconfig: Simplify x86_64 Kconfig handling
by Patrick Rudolph (Code Review) 06 Jul '21

06 Jul '21

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/55471 ) Change subject: Kconfig: Simplify x86_64 Kconfig handling ...................................................................... Abandoned Superseeded by CB:55759 -- To view, visit https://review.coreboot.org/c/coreboot/+/55471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I024226c88ef929c746254b8c2a71e0bdb9338b0e Gerrit-Change-Number: 55471 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mainboard: Add Star Labs labtop series
by build bot (Jenkins) (Code Review) 06 Jul '21

06 Jul '21

Attention is currently required from: Sean Rhodes. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56088 ) Change subject: mainboard: Add Star Labs labtop series ...................................................................... Patch Set 8: (2 comments) File src/mainboard/starlabs/labtop/variants/cml/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123481): https://review.coreboot.org/c/coreboot/+/56088/comment/4805e1a9_2b4e535c PS8, Line 106: const uint8_t ht = get_uint_option("hyper_threading", memupd->FspmConfig.HyperThreading); line over 96 characters File src/mainboard/starlabs/labtop/variants/tgl/devtree.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-123481): https://review.coreboot.org/c/coreboot/+/56088/comment/71b51e66_35ba1a40 PS8, Line 13: // TODO: TGL needs power_limits_config[POWER_LIMITS_U_2_CORE] and power_limits_config[POWER_LIMITS_U_4_CORE] line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/56088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I090971a9e8d2be5b08be886d00d304607304b645 Gerrit-Change-Number: 56088 Gerrit-PatchSet: 8 Gerrit-Owner: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <admin(a)starlabs.systems> Gerrit-Comment-Date: Tue, 06 Jul 2021 07:33:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: grunt/treeya: add Realtek ALC5682 codec support
by Kevin Chang (Code Review) 06 Jul '21

06 Jul '21

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56100 ) Change subject: grunt/treeya: add Realtek ALC5682 codec support ...................................................................... grunt/treeya: add Realtek ALC5682 codec support ALC5682 i2c address: 0x1A BUG=b:185972050 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa --- M src/mainboard/google/kahlee/variants/treeya/Makefile.inc A src/mainboard/google/kahlee/variants/treeya/audio.c M src/mainboard/google/kahlee/variants/treeya/devicetree.cb A src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h 4 files changed, 98 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/56100/1 diff --git a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc index 21b0276..525e76c 100644 --- a/src/mainboard/google/kahlee/variants/treeya/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/treeya/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only subdirs-y += ./spd + +ramstage-y += audio.c diff --git a/src/mainboard/google/kahlee/variants/treeya/audio.c b/src/mainboard/google/kahlee/variants/treeya/audio.c new file mode 100644 index 0000000..e40ad57 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/audio.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/google/chromeec/ec.h> +#include <baseboard/variants.h> +#include <variant/sku.h> +#include <string.h> +#include <drivers/i2c/hid/chip.h> + +extern struct chip_operations drivers_i2c_generic_ops; +extern struct chip_operations drivers_i2c_da7219_ops; + +void variant_devtree_update(void) +{ + uint32_t sku = google_chromeec_get_sku_id(); + struct device *mmio_dev = NULL, *child = NULL; + struct device *alc_dev = NULL, *da7219_dev = NULL; + + while (1) { + mmio_dev = dev_find_path(mmio_dev, DEVICE_PATH_MMIO); + if (mmio_dev == NULL) + break; + if (mmio_dev->path.mmio.addr == 0xfedc2000) + break; + } + + if (mmio_dev == NULL) + return; + + while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { + if (child->path.type != DEVICE_PATH_I2C) + continue; + if (child->path.i2c.device != 0x1a) + continue; + if (child->chip_ops == &drivers_i2c_generic_ops) { + struct drivers_i2c_generic_config *config = child->chip_info; + if (!strcmp(config->hid, "10EC5682")) + alc_dev = child; + } else if (child->chip_ops == &drivers_i2c_da7219_ops) { + da7219_dev = child; + } + } + + switch (sku) { + default: + /* da7219 only */ + if (da7219_dev) + da7219_dev->enabled = 1; + if (alc_dev) + alc_dev->enabled = 0; + break; + case SKU_TREEYA_ALC5682_AE: + case SKU_TREEYA_ALC5682_AF: + /* alc5682 only */ + if (da7219_dev) + da7219_dev->enabled = 0; + if (alc_dev) + alc_dev->enabled = 1; + break; + } +} diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index 183e3dd..0050d80 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -110,6 +110,21 @@ register "mclk_name" = ""oscout1"" device i2c 1a on end end + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "uid" = "1" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_14)" + register "property_count" = "2" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + register "property_list[1].type" = "ACPI_DP_TYPE_STRING" + register "property_list[1].name" = ""realtek,mclk-name"" + register "property_list[1].string" = ""oscout1"" + device i2c 1a on end + end chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h new file mode 100644 index 0000000..fd4fe34 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/sku.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* SKU ID enumeration */ +enum treeya_sku { + SKU_UNKNOWN = -1, + SKU_TREEYA_ALC5682_AE = 174, + SKU_TREEYA_ALC5682_AF = 175, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/56100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49c673fd944b2c2a79c4283eee941a16596ba7fa Gerrit-Change-Number: 56100 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2021