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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56104 )
Change subject: vc/mediatek/mt8195: Improve DRAM driver
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56104/comment/e601de6f_a7d60223
PS1, Line 7: Improve DRAM driver
Improve settings of duty calibration
And remove line #9. Same for the other 2 patches.
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Jan Tatje has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56071 )
Change subject: supermicro/x11-lga1151-series: Remove SkipExtGfxScan = 1
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Can you try again with CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y, please?
Also works just fine.
ASpeed AST2050: initializing video device
ast_detect_chip: VGA not enabled on entry, requesting chip POST
ast_detect_config_mode: P2A bridge disabled, using default configuration
ast_detect_chip: AST 2400 detected
ast_detect_chip: Analog VGA only
ast_driver_load: dram MCLK=396 Mhz type=1 bus_width=16 size=01000000
AST: Display has 1920px x 1080px
Using framebuffer 1920px x 1080px pitch 7680 @ 32 BPP
framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000
ASpeed high resolution framebuffer initialized
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56099 )
Change subject: vc/mediatek/mt8195: Improve DRAM driver
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56099/comment/77a1673d_5229e82c
PS2, Line 11: 3. Enable DRAM Vcore DVFS settings.
> I’d be nice to have one commit per item.
split into 3 patches.
CB:56104
CB:56105
CB:56106
I will abandon this patch.
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Hello Ryan Chuang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/56105
to review the following change.
Change subject: vc/mediatek/mt8195: Improve DRAM driver
......................................................................
vc/mediatek/mt8195: Improve DRAM driver
Enable VREF calibration at DDR3200 for enter/exit S0 stability.
Signed-off-by: Ryan Chuang <ryan.chuang(a)mediatek.corp-partner.google.com>
Change-Id: I9df776b393f6b6166d1d6f02d5e96bd7ebc4a707
---
M src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/56105/1
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
index 71415d2..b761473 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_main.c
@@ -33,7 +33,7 @@
u8 ett_fix_freq = 0xff; // 0xFF=all freq by gFreqTbl. The 0x"X" != 0xFF for single freq by gFreqTbl index, ex: 0x3 for DDR3733
DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SRAM_MAX] = {
- {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_OFF, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first.
+ {LP4_DDR3200 /*0*/, DIV8_MODE, SRAM_SHU1, DUTY_LAST_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first.
{LP4_DDR4266 /*1*/, DIV8_MODE, SRAM_SHU0, DUTY_NEED_K, VREF_CALI_ON, CLOSE_LOOP_MODE}, // highest freq of term group (3733) must k first.
#if ENABLE_DDR400_OPEN_LOOP_MODE_OPTION
{LP4_DDR400 /*2*/, DIV4_MODE, SRAM_SHU7, DUTY_DEFAULT, VREF_CALI_OFF, OPEN_LOOP_MODE},
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