coreboot-gerrit June 2021

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Change in coreboot[master]: acpi: drop unused parameter from acpi_soc_fill_bert
by Felix Held (Code Review) 01 Jun '21

01 Jun '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55052 ) Change subject: acpi: drop unused parameter from acpi_soc_fill_bert ...................................................................... acpi: drop unused parameter from acpi_soc_fill_bert Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55052 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Lance Zhao --- M src/acpi/acpi.c M src/include/acpi/acpi.h M src/soc/intel/common/block/acpi/acpi_bert.c 3 files changed, 4 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Lance Zhao: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 0874e6e..185825b 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1565,7 +1565,7 @@ return false; } -__weak void acpi_soc_fill_bert(acpi_bert_t *bert, void **region, size_t *length) {} +__weak void acpi_soc_fill_bert(void **region, size_t *length) {} unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { @@ -1815,7 +1815,7 @@ size_t size; printk(BIOS_DEBUG, "ACPI: * BERT\n"); bert = (acpi_bert_t *) current; - acpi_soc_fill_bert(bert, &region, &size); + acpi_soc_fill_bert(&region, &size); acpi_write_bert(bert, (uintptr_t)region, size); if (bert->header.length >= sizeof(acpi_bert_t)) { current += bert->header.length; diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index d5e933b..dd00c40 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1342,7 +1342,7 @@ /* For crashlog. */ bool acpi_is_boot_error_src_present(void); -void acpi_soc_fill_bert(acpi_bert_t *bert, void **region, size_t *length); +void acpi_soc_fill_bert(void **region, size_t *length); /* For ACPI S3 support. */ void __noreturn acpi_resume(void *wake_vec); diff --git a/src/soc/intel/common/block/acpi/acpi_bert.c b/src/soc/intel/common/block/acpi/acpi_bert.c index d090dfd..f94026d 100644 --- a/src/soc/intel/common/block/acpi/acpi_bert.c +++ b/src/soc/intel/common/block/acpi/acpi_bert.c @@ -8,9 +8,7 @@ #include <intelblocks/crashlog.h> -void acpi_soc_fill_bert(acpi_bert_t *bert, - void **region, - size_t *length) +void acpi_soc_fill_bert(void **region, size_t *length) { acpi_generic_error_status_t *status = NULL; size_t cpu_record_size, pmc_record_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/55052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic354824468f016a7857c6990024ae87db6fd00bf Gerrit-Change-Number: 55052 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS
by Johnny Lin (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Jonathan Zhang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55005 ) Change subject: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS ...................................................................... Patch Set 2: (1 comment) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/55005/comment/c78476fc_07ab7484 PS2, Line 7: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS > Another approach is to do this in build process: […] The first approach can work w/o chicken and egg problem as long as the data for checksum calculation doesn't include VPD region. At build time cbfstool can extract and calculate several cbfs files' checksum from the coreboot image and set to VPD, and which later got populated into SMBIOS. On the machine we can use flashrom to read out the ifd bios region and does the same thing. For example flashrom read the bios into /tmp/bios.bin, then cbfstool /tmp/bios.bin extract -r COREBOOT -m x86 -n bootblock -f bootblock.bin cbfstool /tmp/bios.bin extract -r COREBOOT -m x86 -n fallback/romstage -f romstage.bin cbfstool /tmp/bios.bin extract -r COREBOOT -m x86 -n fallback/ramstage -f ramstage.bin cbfstool /tmp/bios.bin extract -r COREBOOT -m x86 -n fallback/payload -f payload.bin cat bootblock.bin romstage.bin ramstage.bin payload.bin > bios.bin md5sum bios.bin I just tested this works but somehow cbfstool needs to use the same version otherwise the read cbfs file can be different. The only drawback is that the VPD data can be tampered if we don't have lock protection, but which I guess is not a concern. -- To view, visit https://review.coreboot.org/c/coreboot/+/55005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d41c73ffe8377c6014abe77a8921497a41bcb9 Gerrit-Change-Number: 55005 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Name of user not set #1003548 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 12:33:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]src/soc/intel/common/block/pmc: Don't link get_int_option in SMM
by Angel Pons (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Patrick Rudolph, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Michael Niewöhner, Morgan Jang, Andrey Petrov. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55114 ) Change subject: [RFC]src/soc/intel/common/block/pmc: Don't link get_int_option in SMM ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55114/comment/e89ed308_46fcd425 PS1, Line 7: int *u*int since CB:52672 happened https://review.coreboot.org/c/coreboot/+/55114/comment/b5378184_a52e63e0 PS1, Line 7: src/ nit: drop `src/` https://review.coreboot.org/c/coreboot/+/55114/comment/f66da843_c815542e PS1, Line 14: SMM handler over 72 characters https://review.coreboot.org/c/coreboot/+/55114/comment/b7b74f2d_7cd48ed4 PS1, Line 16: including over 72 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60986979d7f7905b312b7d03abd46ac0465ae4cf Gerrit-Change-Number: 55114 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 12:32:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]src/soc/intel/common/block/pmc: Don't link get_int_option in SMM
by Angel Pons (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Patrick Rudolph, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Morgan Jang, Andrey Petrov. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55114 ) Change subject: [RFC]src/soc/intel/common/block/pmc: Don't link get_int_option in SMM ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File src/soc/intel/common/block/include/intelblocks/pmclib.h: https://review.coreboot.org/c/coreboot/+/55114/comment/1b69aa24_328ebb0e PS1, Line 223: const enum pmc_after_g3_power_state power_on_after_fail); To avoid having to change each and every , I wouldn't change the signature of the `pmc_set_power_failure_state` function. Instead, add another function that takes the `state` parameter: void pmc_set_power_failure_state(bool target_on) { const unsigned int state = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); pmc_set_power_failure_state_val(target_on, state); } void pmc_set_power_failure_state_val(bool target_on, const enum pmc_after_g3_power_state state) { bool on; switch (state) { case MAINBOARD_POWER_STATE_OFF: printk(BIOS_INFO, "Set power off after power failure.\n"); on = false; break; case MAINBOARD_POWER_STATE_ON: printk(BIOS_INFO, "Set power on after power failure.\n"); on = true; break; case MAINBOARD_POWER_STATE_PREVIOUS: printk(BIOS_INFO, "Keep power state after power failure.\n"); on = target_on; break; default: printk(BIOS_WARNING, "WARNING: Unknown power-failure state: %d\n", state); on = false; break; } pmc_soc_set_afterg3_en(on); } To prevent using `pmc_set_power_failure_state()` from within SMM, I can think of three options (sorted, as per my personal preferences, from best to worst): 1. If this works, simply force a linker error: void pmc_set_power_failure_state(bool target_on) { /* Option API can't be safely used from within SMM */ if (ENV_SMM) dead_code(); const unsigned int state = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); pmc_set_power_failure_state_val(target_on, state); } 2. Guard the function definition with some preprocessor: /* Option API can't be safely used from within SMM */ #if !ENV_SMM void pmc_set_power_failure_state(bool target_on) { const unsigned int state = get_uint_option("power_on_after_fail", CONFIG_MAINBOARD_POWER_FAILURE_STATE); pmc_set_power_failure_state_val(target_on, state); } #endif 3. Put the function definition in another compilation unit. Where, though? This also breaks locality of reference. I don't like this idea. File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/55114/comment/39a0c080_e21ac331 PS1, Line 582: power_on_after_fail How about `state` for the sake of brevity? -- To view, visit https://review.coreboot.org/c/coreboot/+/55114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60986979d7f7905b312b7d03abd46ac0465ae4cf Gerrit-Change-Number: 55114 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 12:27:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: docs/flashmap: state the endianness of FMAP
by Krystian Hebel (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Krystian Hebel. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55041 to look at the new patch set (#2). Change subject: docs/flashmap: state the endianness of FMAP ...................................................................... docs/flashmap: state the endianness of FMAP Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Idf6d46ed262b18c176d69352e333c56f4fdff66a --- M Documentation/lib/flashmap.md 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/55041/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf6d46ed262b18c176d69352e333c56f4fdff66a Gerrit-Change-Number: 55041 Gerrit-PatchSet: 2 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE
by Krystian Hebel (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Krystian Hebel. Hello build bot (Jenkins), Idwer Vollering, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55039 to look at the new patch set (#3). Change subject: util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE ...................................................................... util/cbfstool/flashmap/fmap.c: fix fmaptool endianness bugs on BE This patch makes all accesses to the FMAP fields explicitly little endian. It fixes issue where build on BE host produced different binary image than on LE. Signed-off-by: Marek Kasiewicz <marek.kasiewicz(a)3mdeb.com> Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Ia88c0625cefa1e594ac1849271a71c3aacc8ce78 --- M util/cbfstool/flashmap/fmap.c 1 file changed, 33 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/55039/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia88c0625cefa1e594ac1849271a71c3aacc8ce78 Gerrit-Change-Number: 55039 Gerrit-PatchSet: 3 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/Linuxboot/u-root: Explicitly set GO111MODULE=off
by Angel Pons (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Martin Roth, Paul Menzel, Stefan Reinauer, Christian Walter, Arthur Heymans, Ron Minnich. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55095 ) Change subject: payloads/Linuxboot/u-root: Explicitly set GO111MODULE=off ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: I have no idea about Go -- To view, visit https://review.coreboot.org/c/coreboot/+/55095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie90b400418ccd06426a0e00ec7f7932066f57d7e Gerrit-Change-Number: 55095 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 11:55:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]src/soc/intel/common/block/pmc: Don't link get_int_option in SMM
by Patrick Rudolph (Code Review) 01 Jun '21

01 Jun '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55114 ) Change subject: [RFC]src/soc/intel/common/block/pmc: Don't link get_int_option in SMM ...................................................................... [RFC]src/soc/intel/common/block/pmc: Don't link get_int_option in SMM The option backend used in SMM has several disadvantages: - Restoring the initial state when entering SMM is difficult - Accessing hardware is slow and steals time from ring 0 - When using PCI hardware additional checks on decoded memory regions would be necessary - It links in a lot of code, which defeats the aim to have a minimal SMM handler Pass the power_on_after_fail option to SMM by using GNVS instead of including the option backend into SMM. With this change the option can no longer be updated at runtime. Change-Id: I60986979d7f7905b312b7d03abd46ac0465ae4cf Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/alderlake/pmc.c M src/soc/intel/apollolake/pmc.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/elkhartlake/pmc.c M src/soc/intel/icelake/pmc.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/jasperlake/pmc.c M src/soc/intel/skylake/pmc.c M src/soc/intel/tigerlake/pmc.c M src/soc/intel/xeon_sp/pmc.c 14 files changed, 51 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/55114/1 diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index 03399c3..154d1c5b 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -14,6 +14,7 @@ #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <option.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> @@ -76,7 +77,9 @@ rtc_init(); - pmc_set_power_failure_state(true); + const unsigned int state = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_power_failure_state(true, state); pmc_gpe_init(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 4cc7670..d2ba86c 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> +#include <option.h> #include <soc/iomap.h> #include <soc/pm.h> #include <timer.h> @@ -94,5 +95,7 @@ /* Now that things have been logged clear out the PMC state. */ pmc_clear_prsts(); - pmc_set_power_failure_state(true); + const unsigned int state = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_power_failure_state(true, state); } diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index d6c30a8..778b86c 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -7,6 +7,7 @@ #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <option.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -74,7 +75,9 @@ rtc_init(); - pmc_set_power_failure_state(true); + const unsigned int state = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_power_failure_state(true, state); pmc_gpe_init(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index c98fa01..bd41ea9 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -13,7 +13,7 @@ u8 ppcm; /* 0x04 - Max PPC State */ u8 tlvl; /* 0x05 - Throttle Level Limit */ u8 lids; /* 0x06 - LID State */ - u8 unused_was_pwrs; /* 0x07 - AC Power State */ + u8 pag3; /* 0x07 - Power State After G3 */ u32 cbmc; /* 0x08 - 0xb coreboot Memory Console */ u64 pm1i; /* 0x0c - 0x13 PM1 wake status bit */ u64 gpei; /* 0x14 - 0x1b GPE wake status bit */ diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index ecc8166..3d2451c 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -198,7 +198,7 @@ * 2 == Keep Previous State * Keep in sync with `config MAINBOARD_POWER_FAILURE_STATE`. */ -enum { +enum pmc_after_g3_power_state { MAINBOARD_POWER_STATE_OFF, MAINBOARD_POWER_STATE_ON, MAINBOARD_POWER_STATE_PREVIOUS, @@ -209,6 +209,7 @@ * system should go into after power is reapplied. */ void pmc_soc_set_afterg3_en(bool on); + /* * Configure power state to go into when power is reapplied. * @@ -218,7 +219,8 @@ * `target_on` signifies that we are currently powering on, so that * MAINBOARD_POWER_STATE_PREVIOUS can be handled accordingly. */ -void pmc_set_power_failure_state(bool target_on); +void pmc_set_power_failure_state(bool target_on, + const enum pmc_after_g3_power_state power_on_after_fail); /* * This function ensures that the duration programmed in the PchPmPwrCycDur will never be diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index aa5b362..a04a3ff 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -11,7 +11,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/gpio.h> #include <intelblocks/tco.h> -#include <option.h> #include <security/vboot/vboot_common.h> #include <soc/pm.h> #include <stdint.h> @@ -579,14 +578,12 @@ gpio_route_gpe(dw0, dw1, dw2); } -void pmc_set_power_failure_state(const bool target_on) +void pmc_set_power_failure_state(const bool target_on, + const enum pmc_after_g3_power_state power_on_after_fail) { bool on; - const unsigned int state = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); - - switch (state) { + switch (power_on_after_fail) { case MAINBOARD_POWER_STATE_OFF: printk(BIOS_INFO, "Set power off after power failure.\n"); on = false; @@ -600,7 +597,8 @@ on = target_on; break; default: - printk(BIOS_WARNING, "WARNING: Unknown power-failure state: %d\n", state); + printk(BIOS_WARNING, "WARNING: Unknown power-failure state: %d\n", + power_on_after_fail); on = false; break; } diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index ff87d71..5d33043 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -215,7 +215,7 @@ /* Disable all GPE */ pmc_disable_all_gpe(); /* Set which state system will be after power reapplied */ - pmc_set_power_failure_state(false); + pmc_set_power_failure_state(false, gnvs->pag3); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); diff --git a/src/soc/intel/elkhartlake/pmc.c b/src/soc/intel/elkhartlake/pmc.c index 45a368c..bc6b99d 100644 --- a/src/soc/intel/elkhartlake/pmc.c +++ b/src/soc/intel/elkhartlake/pmc.c @@ -7,6 +7,7 @@ #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <option.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> @@ -58,7 +59,9 @@ rtc_init(); - pmc_set_power_failure_state(true); + const unsigned int state = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_power_failure_state(true, state); pmc_gpe_init(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index ee40fee..b331a9f 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -7,6 +7,7 @@ #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <option.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> @@ -58,7 +59,9 @@ rtc_init(); - pmc_set_power_failure_state(true); + const unsigned int state = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_power_failure_state(true, state); pmc_gpe_init(); pmc_set_acpi_mode(); diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index f73766a..1f77128 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -259,6 +259,10 @@ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + /* Set Power State after G3 */ + gnvs->pag3 = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + /* Fill in Above 4GB MMIO resource */ sa_fill_gnvs(gnvs); } diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index dce791c..3b0b51d 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -7,6 +7,7 @@ #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <option.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> @@ -58,7 +59,9 @@ rtc_init(); - pmc_set_power_failure_state(true); + const unsigned int state = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_power_failure_state(true, state); pmc_gpe_init(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index e797b8f..1ed3cad 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -8,6 +8,7 @@ #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <option.h> #include <reg_script.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -94,7 +95,9 @@ rtc_init(); - pmc_set_power_failure_state(true); + const unsigned int state = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_power_failure_state(true, state); pmc_gpe_init(); /* Note that certain bits may be cleared from running script as diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 190f3ff..38a56c1 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -15,6 +15,7 @@ #include <intelblocks/pmclib.h> #include <intelblocks/pmc_ipc.h> #include <intelblocks/rtc.h> +#include <option.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/soc_chip.h> @@ -76,7 +77,9 @@ rtc_init(); - pmc_set_power_failure_state(true); + const unsigned int state = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_power_failure_state(true, state); pmc_gpe_init(); config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c index b0c067b..07de002 100644 --- a/src/soc/intel/xeon_sp/pmc.c +++ b/src/soc/intel/xeon_sp/pmc.c @@ -6,6 +6,7 @@ #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> +#include <option.h> #include <reg_script.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -42,7 +43,9 @@ void pmc_soc_init(struct device *dev) { - pmc_set_power_failure_state(true); + const unsigned int state = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + pmc_set_power_failure_state(true, state); pmc_gpe_init(); /* Note that certain bits may be cleared from running script as -- To view, visit https://review.coreboot.org/c/coreboot/+/55114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60986979d7f7905b312b7d03abd46ac0465ae4cf Gerrit-Change-Number: 55114 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/community: Add Discord to forums
by Felix Held (Code Review) 01 Jun '21

01 Jun '21

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55018 ) Change subject: Documentation/community: Add Discord to forums ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > I agree with Felix that some of the tools we might utilize are not ideal when it comes to how open t […] sure, building the best chat software is way out of scope of coreboot and i also strongly doubt that there's a chat solution that will be the best for everyone. fragmentation might be an issue, but unless this becomes a real problem, i also wouldn't worry too much about that -- To view, visit https://review.coreboot.org/c/coreboot/+/55018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2 Gerrit-Change-Number: 55018 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 11:47:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/var/volet: Update gpio and devicetree settings
by Sheng-Liang Pan (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, YH Lin. Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55113 ) Change subject: mb/google/volteer/var/volet: Update gpio and devicetree settings ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55113 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e9557e01ce1e7a49a3dddf6da3e4a29587a8b7 Gerrit-Change-Number: 55113 Gerrit-PatchSet: 2 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: YH Lin <yueherngl(a)chromium.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 11:45:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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