coreboot-gerrit June 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/dedede/var/sasukette: Modify the touch pad slave address
by Karthik Ramasubramanian (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Henry Sun, Paul Menzel, Tao Xia. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55035 ) Change subject: mb/google/dedede/var/sasukette: Modify the touch pad slave address ...................................................................... Patch Set 3: Code-Review+2 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55035/comment/961da5a3_1f38cf7a PS3, Line 7: slave Nit: slave -> I2C just as an effort to use inclusive language. https://review.coreboot.org/c/coreboot/+/55035/comment/5a97c672_4470b78c PS3, Line 9: slave Same comment as above. https://review.coreboot.org/c/coreboot/+/55035/comment/eb08b0c5_a5dc2407 PS3, Line 10: Nit: remove extra space at the end of the line. -- To view, visit https://review.coreboot.org/c/coreboot/+/55035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0bd80baa27dfeb7bcb43f0ca4b02e1228e372a6 Gerrit-Change-Number: 55035 Gerrit-PatchSet: 3 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-CC: Jessie Xu <xuyanan(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 16:24:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: introduce and use chipset device tree
by Raul Rangel (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50626 ) Change subject: soc/amd/picasso: introduce and use chipset device tree ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/picasso/chipset.cb: https://review.coreboot.org/c/coreboot/+/50626/comment/6f3e952f_c597278f PS6, Line 18: on > i strongly disagree on this, since this device needs to be enabled in order for internal_bridge_a an […] Ah, I misread the later CLs, I thought internal_bridge_a was refering to 8.0. You are right. -- To view, visit https://review.coreboot.org/c/coreboot/+/50626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Gerrit-Change-Number: 50626 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Jun 2021 16:21:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: introduce and use chipset device tree
by Felix Held (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50626 ) Change subject: soc/amd/picasso: introduce and use chipset device tree ...................................................................... Patch Set 6: (1 comment) File src/soc/amd/picasso/chipset.cb: https://review.coreboot.org/c/coreboot/+/50626/comment/00e4499f_229cd556 PS6, Line 18: on > I think I would leave these off by default. i strongly disagree on this, since this device needs to be enabled in order for internal_bridge_a and internal_bridge_b to work. when function 0 of a pcie device is disabled, all other functions are assumed to be disabled too. same argument for device pci 01.0 above. checked with the cezanne chipset devicetree and device pci 08.0 is also enabled there -- To view, visit https://review.coreboot.org/c/coreboot/+/50626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Gerrit-Change-Number: 50626 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 16:13:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/cbmem_stage_cache-test test case
by Patrick Georgi (Code Review) 01 Jun '21

01 Jun '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54916 ) Change subject: tests: Add lib/cbmem_stage_cache-test test case ...................................................................... tests: Add lib/cbmem_stage_cache-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ie6851b9473b225beb5ba51e26f44e21ea5919a64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54916 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M tests/lib/Makefile.inc A tests/lib/cbmem_stage_cache-test.c 2 files changed, 204 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 0792776..6750353 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -30,6 +30,7 @@ tests-y += rtc-test tests-y += spd_cache-ddr3-test tests-y += spd_cache-ddr4-test +tests-y += cbmem_stage_cache-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -167,3 +168,12 @@ CONFIG_DIMM_MAX=4 CONFIG_DIMM_SPD_SIZE=512 \ CONFIG_BOOT_DEVICE_MEMORY_MAPPED=1 spd_cache-ddr4-test-cflags += -D__TEST_SPD_CACHE_DDR=4 + +cbmem_stage_cache-test-srcs += tests/lib/cbmem_stage_cache-test.c +cbmem_stage_cache-test-srcs += tests/stubs/console.c +cbmem_stage_cache-test-srcs += src/lib/cbmem_stage_cache.c +cbmem_stage_cache-test-srcs += src/lib/imd_cbmem.c +cbmem_stage_cache-test-srcs += src/lib/imd.c +cbmem_stage_cache-test-cflags += -I 3rdparty/vboot/firmware/include +cbmem_stage_cache-test-cflags += -I $(src)/commonlib/include +cbmem_stage_cache-test-config += CONFIG_CBMEM_STAGE_CACHE=1 diff --git a/tests/lib/cbmem_stage_cache-test.c b/tests/lib/cbmem_stage_cache-test.c new file mode 100644 index 0000000..24ba095 --- /dev/null +++ b/tests/lib/cbmem_stage_cache-test.c @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <tests/test.h> +#include <cbmem.h> +#include <commonlib/cbmem_id.h> +#include <stage_cache.h> + +#define CBMEM_SIZE (32 * KiB) + +/* CBMEM top pointer used by implementation. */ +extern uintptr_t _cbmem_top_ptr; + +void cbmem_run_init_hooks(int is_recovery) +{ +} + +static void *get_cbmem_ptr(void) +{ + void *cbmem_top_ptr = (void *)_cbmem_top_ptr; + if (cbmem_top_ptr) + return cbmem_top_ptr - CBMEM_SIZE; + else + return NULL; +} + +static void clear_cbmem(void) +{ + void *ptr = get_cbmem_ptr(); + if (ptr) + memset(ptr, 0, CBMEM_SIZE); +} + +int setup_test(void **state) +{ + void *cbmem_top_ptr = malloc(CBMEM_SIZE); + + if (!cbmem_top_ptr) + return -1; + + _cbmem_top_ptr = (uintptr_t)cbmem_top_ptr + CBMEM_SIZE; + clear_cbmem(); + cbmem_initialize_empty(); + return 0; +} + +int teardown_test(void **state) +{ + if (_cbmem_top_ptr && (_cbmem_top_ptr - CBMEM_SIZE)) + free((void *)(_cbmem_top_ptr - CBMEM_SIZE)); + + _cbmem_top_ptr = 0; + return 0; +} + +/* This function is used as prog_entry of struct prog to prevent potential calls to unaccessible + or incorrect addresses. */ +void prog_entry_mock(void *arg) +{ +} + +/* This test checks if stage_cache_add() correctly adds CBMEM_ID_STAGE_x_META + and CBMEM_ID_STAGEx_CACHE entries to cbmem. stage_cache_add() must create meta + entry containing load address, entry address and argument for it. It also must + copy buffer pointer pointed by start pointer of prog struct to cache entry. */ +void test_stage_cache_add(void **state) +{ + const int id = 12; + int arg = 0xC14; + struct stage_cache *meta = NULL; + uint8_t *prog_data_buf = NULL; + const size_t data_sz = 4 * KiB; + uint8_t *data = malloc(data_sz); + struct prog prog_data = {0}; + + assert_non_null(data); + memset(data, 0xDB, data_sz); + prog_data = (struct prog)PROG_INIT(PROG_ROMSTAGE, "test_prog"); + prog_set_area(&prog_data, data, data_sz); + prog_set_entry(&prog_data, prog_entry_mock, &arg); + + stage_cache_add(id, &prog_data); + + meta = cbmem_find(CBMEM_ID_STAGEx_META + id); + assert_non_null(meta); + assert_int_equal(meta->load_addr, (uintptr_t)prog_start(&prog_data)); + assert_int_equal(meta->entry_addr, (uintptr_t)prog_entry(&prog_data)); + assert_int_equal(meta->arg, (uintptr_t)prog_entry_arg(&prog_data)); + + prog_data_buf = cbmem_find(CBMEM_ID_STAGEx_CACHE + id); + assert_non_null(prog_data_buf); + assert_memory_equal(data, prog_data_buf, data_sz); + + free(data); +} + +/* This test checks if stage_cache_add_raw() correctly creates entry with data from + provided buffer. Data should be accessible using cbmem_find() with + (CBMEM_ID_STAGEx_RAW + id) parameter. */ +void test_stage_cache_add_raw(void **state) +{ + const int id = 55; + const size_t data_sz = 8 * KiB; + uint8_t *data = malloc(data_sz); + uint8_t *data_raw = NULL; + + assert_non_null(data); + memset(data, 0x91, data_sz); + + stage_cache_add_raw(id, data, data_sz); + + data_raw = cbmem_find(CBMEM_ID_STAGEx_RAW + id); + assert_non_null(data_raw); + assert_memory_equal(data_raw, data, data_sz); + + free(data); +} + + +/* This test checks if stage_cache_get_raw() correctly extracts base and size of previously + added entry. */ +void test_stage_cache_get_raw(void **state) +{ + const int id = 23; + const size_t data_sz = 3 * KiB; + uint8_t *data = malloc(data_sz); + size_t data_out_sz = 0; + uint8_t *data_out = NULL; + + assert_non_null(data); + memset(data, 0x3c, data_sz); + stage_cache_add_raw(id, data, data_sz); + + stage_cache_get_raw(id, (void **)&data_out, &data_out_sz); + + assert_int_equal(data_sz, data_out_sz); + assert_memory_equal(data, data_out, data_sz); + + free(data); +} + +/* This test checks if stage_cache_load_stage() correctly loads previously added stage data + and its metadata. */ +void test_stage_cache_load_stage(void **state) +{ + int id = 0xCC; + struct prog prog_out = {0}; + const size_t data_sz = 7 * KiB; + uint8_t *data = malloc(data_sz); + uint8_t *data_bak = malloc(data_sz); + struct prog prog_data = {0}; + int arg = 0x33224455; + + assert_non_null(data); + assert_non_null(data_bak); + memset(data, 0x45, data_sz); + + prog_data = (struct prog)PROG_INIT(PROG_RAMSTAGE, "test_prog"); + prog_set_area(&prog_data, data, data_sz); + prog_set_entry(&prog_data, prog_entry_mock, &arg); + stage_cache_add(id, &prog_data); + + /* Copy current data to backup buffer and clear current buffer */ + memcpy(data_bak, data, data_sz); + memset(data, 0, data_sz); + + /* Load stage data. Data should be returned to the same buffer. */ + stage_cache_load_stage(id, &prog_out); + + /* Data should be same as it was before */ + assert_memory_equal(data, data_bak, data_sz); + assert_int_equal(prog_start(&prog_data), prog_start(&prog_out)); + assert_int_equal(prog_size(&prog_data), prog_size(&prog_out)); + assert_ptr_equal(prog_entry(&prog_data), prog_entry(&prog_out)); + assert_ptr_equal(prog_entry_arg(&prog_data), prog_entry_arg(&prog_out)); + + free(data_bak); + free(data); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup_teardown(test_stage_cache_add, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_stage_cache_add_raw, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_stage_cache_get_raw, + setup_test, teardown_test), + cmocka_unit_test_setup_teardown(test_stage_cache_load_stage, + setup_test, teardown_test), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/54916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6851b9473b225beb5ba51e26f44e21ea5919a64 Gerrit-Change-Number: 54916 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/volet: add volet memory configuration.
by Paul Fagerburg (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Nick Vaccaro, Sheng-Liang Pan. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55096 ) Change subject: mb/google/volteer/var/volet: add volet memory configuration. ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: Structurally, looks OK, but I will defer to YH and Nick for final approval -- To view, visit https://review.coreboot.org/c/coreboot/+/55096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 Gerrit-Change-Number: 55096 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 16:06:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/cbmem_stage_cache-test test case
by Paul Fagerburg (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Jakub Czapiga, Julius Werner, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54916 ) Change subject: tests: Add lib/cbmem_stage_cache-test test case ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54916 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6851b9473b225beb5ba51e26f44e21ea5919a64 Gerrit-Change-Number: 54916 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 16:02:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS
by Jonathan Zhang (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Johnny Lin. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55005 ) Change subject: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS ...................................................................... Patch Set 2: (1 comment) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/55005/comment/cd167050_c08b6c9b PS2, Line 7: mb/ocp/deltalake: Add BIOS checksum value to SMBIOS > The first approach can work w/o chicken and egg problem as long as the data for checksum calculation […] This is a fine idea. Thanks for the experiment. I will discuss with FB team. In the mean time, Let's defer this work to CraterLake. -- To view, visit https://review.coreboot.org/c/coreboot/+/55005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22d41c73ffe8377c6014abe77a8921497a41bcb9 Gerrit-Change-Number: 55005 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Name of user not set #1003548 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 15:58:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Reserve wlan & wpss dram memory regions
by Ravi Kumar Bokka (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Ravi kumar. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50587 ) Change subject: sc7280: Reserve wlan & wpss dram memory regions ...................................................................... Patch Set 38: (1 comment) File src/soc/qualcomm/sc7280/soc.c: https://review.coreboot.org/c/coreboot/+/50587/comment/d9ce9a5b_f298f9e9 PS38, Line 15: 4 > Why 4 and 5? I mean I think it doesn't hurt, but generally this index is intended to be sequential. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/50587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Gerrit-Change-Number: 50587 Gerrit-PatchSet: 38 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Tue, 01 Jun 2021 15:57:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/cret: Add new Goodix touchscreen
by Karthik Ramasubramanian (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Dtrain Hsu, Henry Sun. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54872 ) Change subject: mb/google/dedede/var/cret: Add new Goodix touchscreen ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a6f7c1e9900492937202c0bc6595674f1e79e5b Gerrit-Change-Number: 54872 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Comment-Date: Tue, 01 Jun 2021 15:53:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/pcie/rtd3/device: Add PCIe RTD3 driver
by Raul Rangel (Code Review) 01 Jun '21

01 Jun '21

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54966 ) Change subject: drivers/pcie/rtd3/device: Add PCIe RTD3 driver ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54966/comment/05ecccba_0085b8cb PS1, Line 9: I decided : to copy and modify it because the Intel driver has a lot of Intel : specific code. > > 2. So this is where I grew uncomfortable. […] I filed b/189834892 to track the `GL9755` issue. File src/soc/amd/common/block/rtd3/rtd3.c: https://review.coreboot.org/c/coreboot/+/54966/comment/e98c7b77_12d76367 PS1, Line 210: pci_dev_read_resources > > I wasn't a fan of the fake device because it made it difficult to understand. […] It sounds like we need some type of composition. How about something like this? struct drivers_pcie_rtd3_device_config { DEVTREE_CONST struct device *target; } --- device ref gpp_bridge_3 on device pci 00.0 alias nvme on end # Required so the NVMe gets placed into D3 when entering S0i3. chip drivers/pcie/rtd3/device use nvme as target device generic 0 on end end end # NVMe --- acpigen_write_device(acpi_device_path(config->target)); --- I think this makes it clear that the rtd3 driver is writing an ACPI node for the PCI device. It allows us to remove the hard coded `acpigen_write_ADR(0);` as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/54966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2adfc925183ff7a19ab97e89212bc87c40d552d0 Gerrit-Change-Number: 54966 Gerrit-PatchSet: 4 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Duncan Laurie <dlaurie(a)gmail.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Mario Limonciello <mario.limonciello(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Jun 2021 15:53:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit June 2021