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Change subject: mb/google/brya: Add firmware configuration probing for audio
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/brya/variants/brya0/fw_config.c:
https://review.coreboot.org/c/coreboot/+/54716/comment/6d374dcb_afcd3433
PS7, Line 82: BS_PRE_DEVICE
> Hi Tim, […]
I have changed it to BS_DEV_ENABLE for now, PRE_DEVICE changes can be discussed on the corresponding patch.
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Change subject: mb/google/dedede/var/cret: Add new Elan touchscreen
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/brya: Add firmware configuration probing for audio
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/brya0/fw_config.c:
https://review.coreboot.org/c/coreboot/+/54716/comment/641f3387_70f672cb
PS7, Line 82: BS_PRE_DEVICE
> Is there a reason you moved this to PRE_DEVICE ? Volteer used BS_DEV_ENABLE, and I don't see why tha […]
Hi Tim,
we are working on the BT offload changes on top of current patch, which is under verification.
I can revert this to BS_DEV_ENABLE, if it is better to make change in the corresponding patch.
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Change subject: mb/google/brya: Add firmware configuration probing for audio
......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/google/brya/variants/brya0/fw_config.c:
https://review.coreboot.org/c/coreboot/+/54716/comment/2fc188c6_92b54f85
PS7, Line 82: BS_PRE_DEVICE
Is there a reason you moved this to PRE_DEVICE ? Volteer used BS_DEV_ENABLE, and I don't see why that needs to change?
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Change subject: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/xeon_sp/cpx/cpu.c:
https://review.coreboot.org/c/coreboot/+/55098/comment/12ead1e0_975f0688
PS2, Line 26: #include <soc/pci_devs.h>
Please add this in alphabetical order, for an example after line 21.
https://review.coreboot.org/c/coreboot/+/55098/comment/03e5daee_ae6f4349
PS2, Line 109: /*
: * The MSRs and CSRS have the same register layout. Use the CSRS bit definitions
: * Lock Turbo. Did FSP-S set this up???
: */
You might want to use the concise style as below:
/* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions
Lock Turbo. Did FSP-S set this up??? */
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Hello build bot (Jenkins), Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52190
to look at the new patch set (#6).
Change subject: mb/google/dedede/var/drawcia: Add low_power_probe config for camera devices
......................................................................
mb/google/dedede/var/drawcia: Add low_power_probe config for camera devices
Add low_power_probe config to camera devices so that driver skips initial
probe during kernel boot and hence prevents privacy LED blink.
BUG=b:178060668
TEST=Build and boot to OS on Drawcia. Ensure no blink on privacy LED.
Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com>
Change-Id: I00dfe2ce0b57ff3eaa258204f49e79a280754dcf
---
M src/mainboard/google/dedede/variants/drawcia/overridetree.cb
1 file changed, 21 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/52190/6
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Change subject: mainboards using soc/amd/picasso: use aliases for remaining PCIe devices
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/picasso: introduce and use chipset device tree
......................................................................
Patch Set 6:
(1 comment)
File src/soc/amd/picasso/chipset.cb:
https://review.coreboot.org/c/coreboot/+/50626/comment/6a589e34_2fb8b1d7
PS6, Line 18: on
I think I would leave these off by default.
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Change subject: mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/picasso: introduce and use chipset device tree
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