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Change subject: acpi/device: Add ability to generate proper _STA for PowerResource
......................................................................
Patch Set 2:
(1 comment)
File src/include/acpi/acpi_device.h:
https://review.coreboot.org/c/coreboot/+/55027/comment/c21a8f56_7b7de97f
PS2, Line 459:
: /* Write a _STA method that checks the state of the GPIOs. Otherwise
: * the _STA method will always return _ON.
: */
: bool enable_status;
> It looks the comment and name of bool need to explain a litter bit better for next person whom will […]
How about use_gpio_for_status?
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Change subject: mb/google/dedede/var/drawcia: Add low_power_probe config for camera devices
......................................................................
Patch Set 5:
This change is ready for review.
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Change subject: soc/amd/cezanne/include/iomap: properly align defines
......................................................................
Patch Set 1: Code-Review+2
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Change subject: arch/x86: Add a common romstage entry
......................................................................
Patch Set 3:
(1 comment)
File src/include/romstage_common.h:
https://review.coreboot.org/c/coreboot/+/55067/comment/a320d3db_d5699c87
PS3, Line 6: romstage_main
Since this is only for x86 for now, can you add this prottype to arch/romstage.h?
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Change subject: mb/google/guybrush: Move variant_has_fpmcu() after eSPI init
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/bootblock.c:
https://review.coreboot.org/c/coreboot/+/54740/comment/727f300b_b4cf089c
PS3, Line 40: void bootblock_mainboard_init(void){
> open brace '{' following function definitions go on the next line
Please fix.
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Change subject: use initial_lapicid() instead of opencoding it
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/picasso/mca.c:
https://review.coreboot.org/c/coreboot/+/55063/comment/174c41e5_de8fc04a
PS2, Line 167: int
unsigned?
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Hello build bot (Jenkins), Jonathan Zhang, Angel Pons, Arthur Heymans, Michael Niewöhner, Kyösti Mälkki, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Morgan Jang, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55114
to look at the new patch set (#2).
Change subject: [RFC]soc/intel/common/block/pmc: Don't link get_uint_option in SMM
......................................................................
[RFC]soc/intel/common/block/pmc: Don't link get_uint_option in SMM
The option backend used in SMM has several disadvantages:
- Restoring the initial state when entering SMM is difficult
- Accessing hardware is slow and steals time from ring 0
- When using PCI hardware additional checks on decoded memory regions
would be necessary
- It links in a lot of code, which defeats the aim to have a minimal
SMM handler
Pass the power_on_after_fail option to SMM by using GNVS instead of
including the option backend into SMM.
With this change the option can no longer be updated at runtime.
Change-Id: I60986979d7f7905b312b7d03abd46ac0465ae4cf
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/apollolake/acpi/globalnvs.asl
M src/soc/intel/apollolake/include/soc/nvs.h
M src/soc/intel/common/block/acpi/acpi/globalnvs.asl
M src/soc/intel/common/block/include/intelblocks/nvs.h
M src/soc/intel/common/block/include/intelblocks/pmclib.h
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/skylake/acpi/globalnvs.asl
M src/soc/intel/skylake/include/soc/nvs.h
10 files changed, 41 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/55114/2
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55114 )
Change subject: [RFC]src/soc/intel/common/block/pmc: Don't link get_int_option in SMM
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/nvs.h:
https://review.coreboot.org/c/coreboot/+/55114/comment/5b1549ca_97ff470f
PS1, Line 16: u8 pag3; /* 0x07 - Power State After G3 */
A more flexible approach would be to create an Option NVS, which would work like Device NVS or ChromeOS NVS after https://review.coreboot.org/q/topic:%22acpi-gnvs-framework-2%22 got rid of the per-platform dependency. Specifically, CB:49476 and CB:49477 did the actual decoupling.
Still, this is a very good starting point. Introducing Option NVS is significant enough of a change to deserve a patch series of its own.
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