coreboot-gerrit June 2021

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Change in coreboot[master]: soc/amd/picasso: Move Type 17 DMI generation to common
by Nikolai Vyssotski (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nikolai Vyssotski, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52746 to look at the new patch set (#3). Change subject: soc/amd/picasso: Move Type 17 DMI generation to common ...................................................................... soc/amd/picasso: Move Type 17 DMI generation to common Move dmi.c code to common/fsp to be shared among different SOCs. BUG=b:184124605 Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/common/Kconfig.common M src/soc/amd/common/fsp/Makefile.inc R src/soc/amd/common/fsp/dmi.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 5 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/52746/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Gerrit-Change-Number: 52746 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB
by Nikolai Vyssotski (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Matt Papageorge, Felix Held. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55237 ) Change subject: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55237/comment/a021d6a5_9fd176a4 PS3, Line 18: Change > Add a Cq-depend: chrome-internal:3889619 I did not realize it was working now. Last time when making GOP changes I could not get Cq-depend in CB to work with FSP. Good to know. File src/soc/amd/common/block/include/amdblocks/amd_pci_util.h: https://review.coreboot.org/c/coreboot/+/55237/comment/f278efc6_3651e649 PS3, Line 55: struct pci_routing_info_hob { : uint32_t num_of_entries; : struct pci_routing_info routing_table[]; : } __packed; : > Can you move this struct into pci_routing_info.c. It's an implementation detail of FSP. Done File src/soc/amd/common/fsp/pci/pci_routing_info.c: https://review.coreboot.org/c/coreboot/+/55237/comment/4920e5c8_9fc8e7bc PS3, Line 33: d > u? This is not really needed. Was there mostly to aid in debug of the issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/55237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Gerrit-Change-Number: 55237 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 22:31:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB
by build bot (Jenkins) (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt Papageorge, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55237 ) Change subject: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/common/fsp/pci/pci_routing_info.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120818): https://review.coreboot.org/c/coreboot/+/55237/comment/49de8349_bd27b009 PS5, Line 18: } __packed *routing_hob; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/55237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Gerrit-Change-Number: 55237 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 22:29:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB
by Nikolai Vyssotski (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt Papageorge, Felix Held. Hello Jason Glenesk, build bot (Jenkins), Raul Rangel, Marshall Dawson, Matt Papageorge, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55237 to look at the new patch set (#5). Change subject: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB ...................................................................... soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB EDK2 mandates HOB to be in increments of qword (8). This HOB has 13 elements which causes it be padded with 4 bytes of garbage. This results in coreboot failing intermittently with invalid data. Add "number of entries" field to specify the number of valid entries in the table. BUG=b:190153208 Cq-depend: chrome-internal:3889619 TEST=verify HOB is present and correct size (13) is reported Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/common/fsp/pci/pci_routing_info.c M src/vendorcode/amd/fsp/cezanne/FspGuids.h 2 files changed, 11 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/55237/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/55237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Gerrit-Change-Number: 55237 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
by Subrata Banik (Code Review) 04 Jun '21

04 Jun '21

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44014 ) Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE ...................................................................... src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE This patch ensures that the TSEG region is only mapped as cacheable so that one can perform SMRAM relocation faster. Ideally don't need to mark the entire TOP_OF_RAM till BGSM range (used for ME stolen memory, PTT, DPR, PRMRR, TSEG etc) as cacheable as no executable code exist there except TSEG region. Hence only mark TSEG range as cacheable (+ reserved) and other ranges as reserve alone. TEST=Able to build and boot ICL, TGL RVP. Without this CL: PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a With this CL: PCI: 00:00.0 resource base 77000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base 7b000000 size 800000 align 0 gran 0 limit 0 flags f0004200 index a PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index b Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44014/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e12e07c..b15ca01 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -173,8 +173,13 @@ sa_get_mem_map(dev, &sa_map_values[0]); - /* top_of_ram -> BGSM */ + /* top_of_ram -> TSEG */ base_k = top_of_ram; + size_k = sa_map_values[SA_TSEG_REG] - base_k; + mmio_resource(dev, index++, base_k / KiB, size_k / KiB); + + /* TSEG -> BGSM */ + base_k = sa_map_values[SA_TSEG_REG]; size_k = sa_map_values[SA_BGSM_REG] - base_k; reserved_ram_resource(dev, index++, base_k / KiB, size_k / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/44014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Gerrit-Change-Number: 44014 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in ...
by Anil Kumar K (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Patrick Rudolph. Anil Kumar K has uploaded a new patch set (#2) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/55240 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in FSP v2127_00 onwards ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in FSP v2127_00 onwards With XMP3.0 support added for DDR5 in ADL, the MEMORY_INFO_DATA_HOB structure changed and these changes need to be aligned in vendorcode. To align the structres we update the MemInfoHob header file in vendorcode Bug=None Branch=None Test=build coreboot and boot on ADLRVP . Confirm the mosys command displays memory info correctly $mosys memory spd print all Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I86bc11c845d836f39ef5c3d748c5fbb1d098cac0 --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h 1 file changed, 31 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/55240/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86bc11c845d836f39ef5c3d748c5fbb1d098cac0 Gerrit-Change-Number: 55240 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB
by Nikolai Vyssotski (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Marshall Dawson, Nikolai Vyssotski, Matt Papageorge, Felix Held. Hello build bot (Jenkins), Raul Rangel, Marshall Dawson, Matt Papageorge, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55237 to look at the new patch set (#4). Change subject: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB ...................................................................... soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB EDK2 mandates HOB to be in increments of qword (8). This HOB has 13 elements which causes it be padded with 4 bytes of garbage. This results in coreboot failing intermittently with invalid data. Add "number of entries" field to specify the number of valid entries in the table. BUG=b:190153208 Cq-depend: chrome-internal:3889619 TEST=verify HOB is present and correct size (13) is reported Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/common/block/include/amdblocks/amd_pci_util.h M src/soc/amd/common/fsp/pci/pci_routing_info.c M src/vendorcode/amd/fsp/cezanne/FspGuids.h 3 files changed, 14 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/55237/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Gerrit-Change-Number: 55237 Gerrit-PatchSet: 4 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in ...
by Anil Kumar K (Code Review) 04 Jun '21

04 Jun '21

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55240 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in FSP v2127_00 onwards ...................................................................... vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h as per changes in FSP v2127_00 onwards With XMP3.0 support added for DDR5 in ADL, the MEMORY_INFO_DATA_HOB structure changed and these changes need to be aligned in vendorcode. To align the structres we update the MemInfoHob header file in vendorcode Bug=None Branch=None Test=build coreboot and boot on ADLRVP . Confirm the mosys command displays memory info correctly $mosys memory spd print all Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: I86bc11c845d836f39ef5c3d748c5fbb1d098cac0 --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h 1 file changed, 31 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/55240/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h index 31047af..4898bc8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h @@ -27,6 +27,9 @@ #define MAX_NODE 2 #define MAX_CH 4 #define MAX_DIMM 2 +// Must match definitions in +// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h +#define HOB_MAX_SAGV_POINTS 4 /// /// Host reset states from MRC. @@ -129,23 +132,17 @@ // // Matches MrcDdrType enum in MRC // -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 #endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 #endif #ifndef MRC_DDR_TYPE_LPDDR4 #define MRC_DDR_TYPE_LPDDR4 3 #endif -#ifndef MRC_DDR_TYPE_WIO2 -#define MRC_DDR_TYPE_WIO2 4 -#endif #ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 5 +#define MRC_DDR_TYPE_UNKNOWN 4 #endif #define MAX_PROFILE_NUM 4 // number of memory profiles supported @@ -182,6 +179,10 @@ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. } MRC_CH_TIMING; +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + /// /// Memory SMBIOS & OC Memory Data Hob /// @@ -224,6 +225,20 @@ UINT8 Rsvd[2]; } PSMI_MEM_INFO; +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + typedef struct { UINT8 Revision; UINT16 DataWidth; ///< Data width, in bits, of this memory device @@ -244,11 +259,16 @@ UINT32 TotalPhysicalMemorySize; UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 UINT8 RefClk; UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; CONTROLLER_INFO Controller[MAX_NODE]; UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. } MEMORY_INFO_DATA_HOB; /** -- To view, visit https://review.coreboot.org/c/coreboot/+/55240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86bc11c845d836f39ef5c3d748c5fbb1d098cac0 Gerrit-Change-Number: 55240 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: FSP2.0 platforms: Use bootloader reserved memory for BERT
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Andrey Petrov, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55142 ) Change subject: FSP2.0 platforms: Use bootloader reserved memory for BERT ...................................................................... Patch Set 4: (2 comments) File src/soc/intel/common/block/systemagent/memmap.c: https://review.coreboot.org/c/coreboot/+/55142/comment/71ef9b28_1af3efaa PS3, Line 61: *start = cbmem_top(); : *size = CONFIG_ACPI_BERT_SIZE; > Yeah that makes sense to me, the extra MTRR is not necessary […] There was some discussion here https://review.coreboot.org/c/coreboot/+/44014 w.r.t. top_of_ram -> TOLUD caching attributes. File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/55142/comment/c77714fa_79e38bef PS4, Line 196: Make sure to account for the fact that the FSP saves some of the : * reserved RAM for ACPI BERT One thing that I fear about is this getting out of sync with rest of the changes for BERT space allocation in the next refactor. There is nothing that will catch that the assumption is broken. -- To view, visit https://review.coreboot.org/c/coreboot/+/55142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd99fc4a89d559be32be69f8fc73c30782e6ae97 Gerrit-Change-Number: 55142 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 22:00:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP,RFC] sb,soc/intel: Remove option power on after fail from SMI
by Kyösti Mälkki (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Angel Pons, Arthur Heymans, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55238 ) Change subject: [WIP,RFC] sb,soc/intel: Remove option power_on_after_fail from SMI ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55238/comment/9d4aa0db_91f7ffcb PS1, Line 9: The mechanism was flawed. In the case that nvram contents were > This write is done to emulate the "keep" setting, as the hardware only knows "on" and "off". I know. To have an NVS bit is a less bad choice than CMOS or SMBUS+EEPROM. But NVS store is outside TSEG. If I remember correctly, we link (static) devicetree into SMM now for chip_info access and that is something that should be fixed too. There is a general need for passing some configuration bits to SMI handlers, something to put into SMM module loader probably. -- To view, visit https://review.coreboot.org/c/coreboot/+/55238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ae6aa08177d4915a7acd5a53e0aae1e968e60a2 Gerrit-Change-Number: 55238 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 21:57:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2021