coreboot-gerrit June 2021

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Change in coreboot[master]: security/vboot: Add support for ZTE spaces
by build bot (Jenkins) (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Aaron Durbin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55242 ) Change subject: security/vboot: Add support for ZTE spaces ...................................................................... Patch Set 1: (3 comments) File src/security/vboot/secdata_tpm.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120823): https://review.coreboot.org/c/coreboot/+/55242/comment/b0bfed24_d884eb8f PS1, Line 126: .TPMA_NV_PPWRITE =1, spaces required around that '=' (ctx:WxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120823): https://review.coreboot.org/c/coreboot/+/55242/comment/c15446bf_f4325f54 PS1, Line 137: .TPMA_NV_PPWRITE =1, spaces required around that '=' (ctx:WxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120823): https://review.coreboot.org/c/coreboot/+/55242/comment/ac391ab0_9d68bc00 PS1, Line 274: /* Initialize defaults: Board ID and RMA+SN Bits must be intialized to 'intialized' may be misspelled - perhaps 'initialized'? -- To view, visit https://review.coreboot.org/c/coreboot/+/55242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb Gerrit-Change-Number: 55242 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Sat, 05 Jun 2021 00:01:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add support for ZTE spaces
by Aseda Aboagye (Code Review) 05 Jun '21

05 Jun '21

Attention is currently required from: Aaron Durbin. Aseda Aboagye has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55242 ) Change subject: security/vboot: Add support for ZTE spaces ...................................................................... security/vboot: Add support for ZTE spaces This commit adds support for the Chrome OS Zero-Touch Enrollment related spaces. For TPM 2.0 devices which don't use Cr50, coreboot will define the Attested Device ID, Board ID, and RMA counter spaces. BUG=b:184676425 BRANCH=None TEST=Build and flash lalala, verify that the ZTE spaces are created successfully. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb --- M src/security/vboot/antirollback.h M src/security/vboot/secdata_tpm.c 2 files changed, 124 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/55242/1 diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index fcfa7a2..a208c04 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -28,6 +28,10 @@ /* 0x100d: Hash of MRC_CACHE training data for non-recovery boot */ #define MRC_RW_HASH_NV_INDEX 0x100d #define HASH_NV_SIZE VB2_SHA256_DIGEST_SIZE +/* Zero-Touch Enrollment related spaces */ +#define ZTE_BOARD_ID_NV_INDEX 0x3fff00 +#define ZTE_RMA_SN_BITS_INDEX 0x3fff01 +#define ZTE_RMA_BYTES_COUNTER_INDEX 0x3fff04 /* Structure definitions for TPM spaces */ diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index dd36796..1cc1888 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -117,6 +117,29 @@ .TPMA_NV_PPWRITE = 1, }; +/* Attributes for spaces that enable zero-touch enrollment (ZTE) */ +static const TPMA_NV zte_attr = { + .TPMA_NV_PLATFORMCREATE = 1, + .TPMA_NV_WRITEDEFINE = 1, + .TPMA_NV_AUTHWRITE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_PPWRITE =1, + .TPMA_NV_PPREAD = 1, + .TPMA_NV_NO_DA = 1, + .TPMA_NV_POLICY_DELETE = 1, +}; + +static const TPMA_NV zte_rma_bytes_attr = { + .TPMA_NV_PLATFORMCREATE = 1, + .TPMA_NV_BITS = 1, + .TPMA_NV_AUTHWRITE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_PPWRITE =1, + .TPMA_NV_PPREAD = 1, + .TPMA_NV_NO_DA = 1, + .TPMA_NV_POLICY_DELETE = 1, +}; + /* * This policy digest was obtained using TPM2_PolicyOR on 3 digests * corresponding to a sequence of @@ -154,6 +177,30 @@ 0x50, 0xEF, 0x96, 0x98, 0x0A, 0x2B, 0x96, 0x6E, 0xA9, 0x09, 0x04, 0x4A, 0x01, 0xB8, 0x5F, 0xA5, 0x4A, 0x96, 0xFC, 0x59, 0x84}; +static uint32_t define_space(const char *name, uint32_t index, uint32_t length, + const TPMA_NV nv_attributes, + const uint8_t *nv_policy, size_t nv_policy_size) +{ + uint32_t rv; + + rv = tlcl_define_space(index, length, nv_attributes, nv_policy, + nv_policy_size); + if (rv == TPM_E_NV_DEFINED) { + /* + * Continue with writing: it may be defined, but not written + * to. In that case a subsequent tlcl_read() would still return + * TPM_E_BADINDEX on TPM 2.0. The cases when some non-firmware + * space is defined while the firmware space is not there + * should be rare (interru pted initialization), so no big harm + * in writing once again even if it was written already. + */ + VBDEBUG("%s: %s space already exists\n", __func__, name); + rv = TPM_SUCCESS; + } + + return rv; +} + /* Nothing special in the TPM2 path yet. */ static uint32_t safe_write(uint32_t index, const void *data, uint32_t length) { @@ -166,21 +213,8 @@ { uint32_t rv; - rv = tlcl_define_space(index, length, nv_attributes, nv_policy, - nv_policy_size); - if (rv == TPM_E_NV_DEFINED) { - /* - * Continue with writing: it may be defined, but not written - * to. In that case a subsequent tlcl_read() would still return - * TPM_E_BADINDEX on TPM 2.0. The cases when some non-firmware - * space is defined while the firmware space is not there - * should be rare (interrupted initialization), so no big harm - * in writing once again even if it was written already. - */ - VBDEBUG("%s: %s space already exists\n", __func__, name); - rv = TPM_SUCCESS; - } - + rv = define_space(name, index, length, nv_attributes, nv_policy, + nv_policy_size); if (rv != TPM_SUCCESS) return rv; @@ -225,6 +259,69 @@ } } +/** + * Setup the Zero-Touch Enrollment(ZTE) related spaces. + * + * These spaces are not used by firmware, but we do need to initialize them. + */ +static uint32_t setup_zte_spaces(void) +{ + uint32_t rv; + uint64_t rma_bytes_counter_default = 0; + uint8_t rma_sn_bits_default[16]; + uint8_t board_id_default[12]; + + /* Initialize defaults: Board ID and RMA+SN Bits must be intialized to + all 0xFFs. */ + for (int i = 0; i < ARRAY_SIZE(rma_sn_bits_default); i++) + rma_sn_bits_default[i] = 0xFF; + + for (int i = 0; i < ARRAY_SIZE(board_id_default); i++) + board_id_default[i] = 0xFF; + + /* Setup RMA + SN Bits */ + rv = setup_space("RMA + SN Bits", ZTE_RMA_SN_BITS_INDEX, + rma_sn_bits_default, sizeof(rma_sn_bits_default), + zte_attr, + pcr0_allowed_policy, sizeof(pcr0_allowed_policy)); + if (rv != TPM_SUCCESS) { + VBDEBUG("%s: Failed to setup RMA + SN Bits space\n", __func__); + return rv; + } + + /* Setup Board ID */ + rv = setup_space("Board ID", ZTE_BOARD_ID_NV_INDEX, + board_id_default, sizeof(board_id_default), + zte_attr, + pcr0_allowed_policy, sizeof(pcr0_allowed_policy)); + if (rv != TPM_SUCCESS) { + VBDEBUG("%s: Failed to setup Board ID space\n", __func__); + return rv; + } + + /* Setup RMA Bytes counter */ + rv = define_space("RMA Bytes Counter", ZTE_RMA_BYTES_COUNTER_INDEX, + sizeof(rma_bytes_counter_default), + zte_rma_bytes_attr, + pcr0_allowed_policy, sizeof(pcr0_allowed_policy)); + if (rv != TPM_SUCCESS) { + VBDEBUG("%s: Failed to define RMA Bytes space\n", __func__); + return rv; + } + + /* + * Since the RMA counter has the BITS attribute, we need to call + * TPM2_NV_SetBits() in order to initialize it. + */ + rv = tlcl_set_bits(ZTE_RMA_BYTES_COUNTER_INDEX, 0); + if (rv != TPM_SUCCESS) { + VBDEBUG("%s: Failed to init RMA Bytes space\n", __func__); + return rv; + } + + return rv; +} + static uint32_t _factory_initialize_tpm(struct vb2_context *ctx) { RETURN_ON_FAILURE(tlcl_force_clear()); @@ -250,6 +347,14 @@ /* Define and write firmware management parameters space. */ RETURN_ON_FAILURE(setup_fwmp_space(ctx)); + /* + * Define and write zero-touch enrollment (ZTE) spaces. For Cr50 devices, + * these are setup elsewhere via TPM vendor commands. + */ + if (!(CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) || + CONFIG(MAINBOARD_HAS_I2C_TPM_CR50))) + RETURN_ON_FAILURE(setup_zte_spaces()); + RETURN_ON_FAILURE(setup_firmware_space(ctx)); return TPM_SUCCESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/55242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97e3ae7e18fc9ee9a02afadbbafeb226b41af0eb Gerrit-Change-Number: 55242 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()`
by Aseda Aboagye (Code Review) 05 Jun '21

05 Jun '21

Aseda Aboagye has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55241 ) Change subject: security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()` ...................................................................... security/tpm/tss/tcg-2.0: Add `tlcl_set_bits()` This commit adds support for the TPM2_NV_SetBits command to the TLCL. This command is used to set bits in an NV index that was created as a bit field. Any number of bits from 0 to 64 may be set. The contents of bits are ORed with the current contents of the NV index. BUG=b:184676425 BRANCH=None TEST=With other changes, create a NVMEM space in a TPM 2.0 TPM with the bits attribute. Issue the command and verify that the TPM command succeeds. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653 --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/55241/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 4a8206d0..f68e1f4 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -68,6 +68,9 @@ uint32_t property_count, TPMS_CAPABILITY_DATA *capability_data); +/* Issue TPM2_NV_SetBits command */ +uint32_t tlcl_set_bits(uint32_t index, uint64_t bits); + /* * Makes tpm_process_command available for on top implementations of * custom tpm standards like cr50 diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 79d8eb9..f464fe1 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -317,6 +317,29 @@ return TPM_SUCCESS; } +uint32_t tlcl_set_bits(uint32_t index, uint64_t bits) +{ + struct tpm2_nv_setbits_cmd nvsb_cmd; + struct tpm2_response *response; + + /* Prepare the command structure */ + memset(&nvsb_cmd, 0, sizeof(nvsb_cmd)); + + nvsb_cmd.nvIndex = HR_NV_INDEX + index; + nvsb_cmd.bits = bits; + + response = tpm_process_command(TPM2_NV_SetBits, &nvsb_cmd); + + printk(BIOS_INFO, "%s: response is %x\n", + __func__, response ? response->hdr.tpm_code : -1); + + /* Need to map tpm error codes into internal values. */ + if (!response || response->hdr.tpm_code) + return TPM_E_WRITE_FAILURE; + + return TPM_SUCCESS; +} + uint32_t tlcl_define_space(uint32_t space_index, size_t space_size, const TPMA_NV nv_attributes, const uint8_t *nv_policy, size_t nv_policy_size) diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index f21fe3d..83fff5f 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -197,6 +197,18 @@ return rc; } +static int marshal_nv_setbits(struct obuf *ob, + const struct tpm2_nv_setbits_cmd *command_body) +{ + int rc = 0; + const uint32_t handles[] = { TPM_RH_PLATFORM, command_body->nvIndex }; + + rc |= marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); + rc |= obuf_write_be64(ob, command_body->bits); + + return rc; +} + static int marshal_nv_write(struct obuf *ob, const struct tpm2_nv_write_cmd *command_body) { @@ -386,6 +398,10 @@ rc |= marshal_nv_define_space(ob, tpm_command_body); break; + case TPM2_NV_SetBits: + rc |= marshal_nv_setbits(ob, tpm_command_body); + break; + case TPM2_NV_Write: rc |= marshal_nv_write(ob, tpm_command_body); break; @@ -618,6 +634,7 @@ case TPM2_Clear: case TPM2_ClearControl: case TPM2_NV_DefineSpace: + case TPM2_NV_SetBits: case TPM2_NV_Write: case TPM2_NV_WriteLock: case TPM2_PCR_Extend: diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 1c7aa4b..cb8b4f9 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -81,6 +81,7 @@ #define TPM2_Clear ((TPM_CC)0x00000126) #define TPM2_ClearControl ((TPM_CC)0x00000127) #define TPM2_NV_DefineSpace ((TPM_CC)0x0000012A) +#define TPM2_NV_SetBits ((TPM_CC)0x00000135) #define TPM2_NV_Write ((TPM_CC)0x00000137) #define TPM2_NV_WriteLock ((TPM_CC)0x00000138) #define TPM2_SelfTest ((TPM_CC)0x00000143) @@ -395,6 +396,11 @@ uint16_t offset; }; +struct tpm2_nv_setbits_cmd { + TPMI_RH_NV_INDEX nvIndex; + uint64_t bits; +}; + struct tpm2_self_test { TPMI_YES_NO yes_no; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/55241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca6376bb9f7ed8fd1167c2c80f1e8d3c3f46653 Gerrit-Change-Number: 55241 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: FSP2.0 platforms: Use bootloader reserved memory for BERT
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Arthur Heymans, Andrey Petrov, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55142 ) Change subject: FSP2.0 platforms: Use bootloader reserved memory for BERT ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/systemagent/systemagent.c: https://review.coreboot.org/c/coreboot/+/55142/comment/5880b338_82d302c6 PS4, Line 196: Make sure to account for the fact that the FSP saves some of the : * reserved RAM for ACPI BERT > One thing that I fear about is this getting out of sync with rest of the changes for BERT space allo […] How about a Kconfig, e.g. ``` config FSP_RESERVE_BERT_REGION bool depends on ACPI_BERT ``` where the memory_init.c code guards adding the space: ``` if (CONFIG(FSP_RESERVE_BERT_REGION)) march_upd->BootloaderTolumSize += CONFIG_ACPI_BERT_SIZE; ``` and then here ``` if (CONFIG(FSP_RESERVE_BERT_REGION)) top_of_ram += CONFIG_ACPI_BERT_SIZE; ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/55142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd99fc4a89d559be32be69f8fc73c30782e6ae97 Gerrit-Change-Number: 55142 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 23:10:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Drop unused lpss functions
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55226 ) Change subject: soc/intel: Drop unused lpss functions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Gerrit-Change-Number: 55226 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 23:06:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Move Type 17 DMI generation to common
by Nikolai Vyssotski (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Nikolai Vyssotski, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52746 to look at the new patch set (#4). Change subject: soc/amd/picasso: Move Type 17 DMI generation to common ...................................................................... soc/amd/picasso: Move Type 17 DMI generation to common Move dmi.c code to common/fsp to be shared among different SOCs. BUG=b:184124605 Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> --- M src/soc/amd/common/Kconfig.common M src/soc/amd/common/fsp/Makefile.inc R src/soc/amd/common/fsp/dmi.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 5 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/52746/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Gerrit-Change-Number: 52746 Gerrit-PatchSet: 4 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Drop unused lpss functions
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55226 ) Change subject: soc/intel: Drop unused lpss functions ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > looks like cannonlake does […] Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/55226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Gerrit-Change-Number: 55226 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 22:45:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Drop unused lpss functions
by Furquan Shaikh (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Furquan Shaikh, Patrick Rudolph. Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55226 to look at the new patch set (#2). Change subject: soc/intel: Drop unused lpss functions ...................................................................... soc/intel: Drop unused lpss functions This change drops the following unused lpss functions and related code: * soc_lpss_controllers_list * is_dev_lpss These functions were added to determine if a controller is LPSS for performing IRQ configuration. But, these never got used and hence are being dropped. Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/lpss.h M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 8 files changed, 0 insertions(+), 148 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/55226/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Gerrit-Change-Number: 55226 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB
by Raul Rangel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nikolai Vyssotski, Matt Papageorge, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55237 ) Change subject: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20 Gerrit-Change-Number: 55237 Gerrit-PatchSet: 5 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 22:42:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Move Type 17 DMI generation to common
by Nikolai Vyssotski (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Nikolai Vyssotski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52746 ) Change subject: soc/amd/picasso: Move Type 17 DMI generation to common ...................................................................... Patch Set 3: (2 comments) File src/soc/amd/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/52746/comment/f2f1a16a_ac5cf071 PS2, Line 11: _ > Add a _COMMON Done File src/soc/amd/common/fsp/Makefile.inc: https://review.coreboot.org/c/coreboot/+/52746/comment/dbaf3d2a_4b758fe2 PS2, Line 7: ramstage-y > How about `ramstage-$(CONFIG_SOC_AMD_FSP_DMI_TABLES)` += Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Gerrit-Change-Number: 52746 Gerrit-PatchSet: 3 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 22:39:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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