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Change subject: FSP2.0 platforms: Use bootloader reserved memory for BERT
......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/common/block/systemagent/memmap.c:
https://review.coreboot.org/c/coreboot/+/55142/comment/39e9af16_c4befe4e
PS3, Line 40: * +---------------------------+ TOLUM / top_of_ram / cbmem_top
> update comment
Done
https://review.coreboot.org/c/coreboot/+/55142/comment/cc575205_cfb08c8e
PS3, Line 61: *start = cbmem_top();
: *size = CONFIG_ACPI_BERT_SIZE;
> Just wondering: this ends up being UC instead of WB: see systemagent.c 'top_of_ram -> TOLUD'. […]
Yeah that makes sense to me, the extra MTRR is not necessary
`MTRR: 1 base 0x0000000076ff0000 mask 0x00003fffffff0000 type 0`
is what I got on my machine for that region, next patch will account for that
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I'd like you to reexamine a change. Please visit
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Change subject: FSP2.0 platforms: Use bootloader reserved memory for BERT
......................................................................
FSP2.0 platforms: Use bootloader reserved memory for BERT
Currently, a cbmem entry is used to store the BERT data, but when
ACPI_BERT is defined, the FSP will save some memory in its reserved area
above TOLUM to store the ACPI BERT. This patch moves the area
BERT data is stored from cbmem to this reserved region.
TEST=1) Trigger an event which will create a BERT
2) Verify BERT contents look valid
3) Ensure reserved region is covered by an e820 entry marked RESERVED
4) Ensure cbmem contents are still valid
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Ibd99fc4a89d559be32be69f8fc73c30782e6ae97
---
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/systemagent/memmap.c
M src/soc/intel/common/block/systemagent/systemagent.c
3 files changed, 21 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/55142/4
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Change subject: payloads/tianocore: Fix orphaned reference to 'bootloader' variable
......................................................................
Patch Set 2: Code-Review+2
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Change subject: [WIP,RFC] sb,soc/intel: Remove option power_on_after_fail from SMI
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55238/comment/ddc47d48_d7d325cd
PS1, Line 9: The mechanism was flawed. In the case that nvram contents were
This write is done to emulate the "keep" setting, as the hardware only knows "on" and "off".
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Change subject: payloads/tianocore: Fix orphaned reference to 'bootloader' variable
......................................................................
payloads/tianocore: Fix orphaned reference to 'bootloader' variable
commit d3b49b4
[payloads/Tianocore: Update default build target, simplify build options]
simplified the build string and removed the bootloader Makefile variable,
but one reference was missed. Luckily the variable being empty didn't
break things, but correct it regardless.
Change-Id: If37b291dda59c20bfe4c6e5b9100fac52d11a2f4
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M payloads/external/tianocore/Makefile
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/55239/2
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Change subject: mb/google/poppy: Do not let FSP-S init UART 0
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Change subject: skylake boards: Auto-config SerialIO UPDs (all disabled)
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