coreboot-gerrit June 2021

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Change in coreboot[master]: [WIP] mb/dell: Add OptiPlex 7020 SFF port
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Máté Kukri, Martin Roth, Paul Menzel, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55232 ) Change subject: [WIP] mb/dell: Add OptiPlex 7020 SFF port ...................................................................... Patch Set 1: (1 comment) File src/mainboard/dell/optiplex_7020/smscprog.c: PS1: > Please run this through clang-format or indent, so Jenkins does not add so many comments. […] This file is obviously WIP. There's a *lot* to clean up here, not just formatting. -- To view, visit https://review.coreboot.org/c/coreboot/+/55232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 20:22:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset
by Tim Wawrzynczak (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Subrata Banik, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55230 ) Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55230/comment/bc95b28a_280db63a PS2, Line 10: 619502 619503 -- To view, visit https://review.coreboot.org/c/coreboot/+/55230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59 Gerrit-Change-Number: 55230 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 20:05:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy: Do not let FSP-S init UART 0
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55236 ) Change subject: mb/google/poppy: Do not let FSP-S init UART 0 ...................................................................... mb/google/poppy: Do not let FSP-S init UART 0 FSP-S configures the GPIOs for enabled SerialIO devices. However, Poppy boards only enable UART 0 because it's function 0 of PCI device 30, and the PCI specification requires that function 0 of multifunction devices be implemented if other functions are implemented as well. Nautilus got remedied in commit 8a1f095e50e068e42d378f47c79467e7b6295b7b (mb/google/poppy/variants/nautilus: Update camera power enable GPIOs) by using `PchSerialIoSkipInit` for UART 0, which tells FSP to not touch the SerialIO device. This way, it remains enabled and the GPIO settings will not be overwritten by FSP. However, not all variants do this, but use some UART 0 pads as GPIOs. To prevent any issues, configure UART 0 as `PchSerialIoSkipInit` on all the variants. Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/55236/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index c5d8539..ebf61e3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -238,7 +238,7 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoDisabled, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 885fcbd..193d0fc 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -258,7 +258,7 @@ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, [PchSerialIoIndexSpi0] = PchSerialIoPci, [PchSerialIoIndexSpi1] = PchSerialIoPci, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 4ea4740..da04547 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -219,7 +219,7 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoPci, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index df571aa..49ecb49 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -239,7 +239,7 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, [PchSerialIoIndexSpi0] = PchSerialIoDisabled, [PchSerialIoIndexSpi1] = PchSerialIoDisabled, - [PchSerialIoIndexUart0] = PchSerialIoPci, + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, [PchSerialIoIndexUart1] = PchSerialIoDisabled, [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/55236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e3a61769ef9e3b348ce84c663f67d3c4c5d9485 Gerrit-Change-Number: 55236 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: skylake boards: Auto-config SerialIO UPDs (consistent)
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Felix Singer, Frans Hendriks, Michael Niewöhner, Wim Vervoorn. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55235 ) Change subject: skylake boards: Auto-config SerialIO UPDs (consistent) ...................................................................... skylake boards: Auto-config SerialIO UPDs (consistent) On those mainboards where the SerialIO configuration is consistent, select the `DERIVE_SERIALIO_CFG_FROM_DEV_STATE` Kconfig option and omit the `SerialIoDevMode` devicetree setting. Consistent settings signify that these changes should not have any functional impact. Change-Id: I05430ce2b9ef0b66792c188901009491247720fc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/Kconfig M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/kunimitsu/devicetree.cb 6 files changed, 5 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/55235/1 diff --git a/src/mainboard/clevo/kbl-u/Kconfig b/src/mainboard/clevo/kbl-u/Kconfig index c8c364b..9c7313a 100644 --- a/src/mainboard/clevo/kbl-u/Kconfig +++ b/src/mainboard/clevo/kbl-u/Kconfig @@ -3,6 +3,7 @@ config BOARD_CLEVO_KBLU_COMMON def_bool n select BOARD_ROMSIZE_KB_8192 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 607e586..4cdc69b 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -35,10 +35,6 @@ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" - register "SerialIoDevMode" = "{ - [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index fe3b056..ae0d907 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select DISABLE_ACPI_HIBERNATE select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 13b3abc..895247e 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -198,21 +198,6 @@ register "SsicPortEnable" = "0" - # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ - }" - # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, @@ -233,6 +218,7 @@ device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 device pci 1d.0 on end # PCI Express Port 9 x4 FPGA + # Must leave UART0 enabled or SD/eMMC will not work as PCI device pci 1e.0 on end # UART #0 device pci 1e.4 on end # eMMC device pci 1f.0 on # LPC Interface diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index cf67ca1..30d48e6 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select DRIVERS_GENERIC_MAX98357A select DRIVERS_I2C_GENERIC select DRIVERS_I2C_NAU8825 diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 505a598..31cf75b 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -132,7 +132,6 @@ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ [PchSerialIoIndexI2C1] = PchSerialIoPci, \ @@ -255,6 +254,7 @@ device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 + # Must leave UART0 enabled or SD/eMMC will not work as PCI device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 -- To view, visit https://review.coreboot.org/c/coreboot/+/55235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I05430ce2b9ef0b66792c188901009491247720fc Gerrit-Change-Number: 55235 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: skylake boards: Auto-config SerialIO UPDs (all disabled)
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55234 ) Change subject: skylake boards: Auto-config SerialIO UPDs (all disabled) ...................................................................... skylake boards: Auto-config SerialIO UPDs (all disabled) On boards where all SerialIO devices are disabled (default when not specified), select the `DERIVE_SERIALIO_CFG_FROM_DEV_STATE` Kconfig option and omit the `SerialIoDevMode` devicetree setting. Change-Id: Idead3c0a06c1853696b4f3dba7e35ac5bd2e014b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/51nb/x210/Kconfig M src/mainboard/asrock/h110m/Kconfig M src/mainboard/kontron/bsl6/Kconfig M src/mainboard/libretrend/lt1000/Kconfig M src/mainboard/protectli/vault_kbl/Kconfig M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig 8 files changed, 7 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/55234/1 diff --git a/src/mainboard/51nb/x210/Kconfig b/src/mainboard/51nb/x210/Kconfig index efd21da..7621637 100644 --- a/src/mainboard/51nb/x210/Kconfig +++ b/src/mainboard/51nb/x210/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select EC_51NB_NPCE985LA0DX select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index cec5db8..8c2ee65 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index dd8f4fa..a4322b8 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -3,6 +3,7 @@ config BOARD_KONTRON_BSL6_COMMON def_bool n select BOARD_ROMSIZE_KB_16384 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select SOC_INTEL_SKYLAKE select SKYLAKE_SOC_PCH_H select EXCLUDE_NATIVE_SD_INTERFACE diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig index bfd532a..4edde08 100644 --- a/src/mainboard/libretrend/lt1000/Kconfig +++ b/src/mainboard/libretrend/lt1000/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 7aa78aa..c30615b 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index dc73f91..a70f344 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -177,20 +177,6 @@ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ - }" - # Lock Down CHIPSET_LOCKDOWN_COREBOOT register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index c59f7fa..c86c7d6 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -1,6 +1,7 @@ config BOARD_PURISM_BASEBOARD_LIBREM_SKL def_bool n select BOARD_ROMSIZE_KB_16384 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select DRIVERS_GENERIC_CBFS_SERIAL select GFX_GMA_IGNORE_PRESENCE_STRAPS select HAVE_ACPI_RESUME diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 3342b04..b54a749 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -1,6 +1,7 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES def_bool n select BOARD_ROMSIZE_KB_16384 + select DERIVE_SERIALIO_CFG_FROM_DEV_STATE select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT -- To view, visit https://review.coreboot.org/c/coreboot/+/55234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idead3c0a06c1853696b4f3dba7e35ac5bd2e014b Gerrit-Change-Number: 55234 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/tianocore: Add Kconfig option to enable cbmem logging
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Martin Roth, Matt DeVillier. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55144 ) Change subject: payloads/tianocore: Add Kconfig option to enable cbmem logging ...................................................................... Patch Set 2: (1 comment) File payloads/external/tianocore/Kconfig: https://review.coreboot.org/c/coreboot/+/55144/comment/fe68013f_4ec10e18 PS2, Line 64: kb Kilobits? I guess it's either KiB or KB in uppercase -- To view, visit https://review.coreboot.org/c/coreboot/+/55144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Gerrit-Change-Number: 55144 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 19:51:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/dell: Add OptiPlex 7020 SFF port
by Paul Menzel (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Máté Kukri, Martin Roth, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55232 ) Change subject: [WIP] mb/dell: Add OptiPlex 7020 SFF port ...................................................................... Patch Set 1: (1 comment) File src/mainboard/dell/optiplex_7020/smscprog.c: PS1: Please run this through clang-format or indent, so Jenkins does not add so many comments. ;-) -- To view, visit https://review.coreboot.org/c/coreboot/+/55232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 19:39:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]soc/intel/common/block/pmc: Don't link get_uint_option in SMM
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Arthur Heymans, Michael Niewöhner, Kyösti Mälkki, Andrey Petrov, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Morgan Jang, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55114 ) Change subject: [RFC]soc/intel/common/block/pmc: Don't link get_uint_option in SMM ...................................................................... Patch Set 2: Code-Review+1 (1 comment) File src/soc/intel/common/block/pmc/pmclib.c: https://review.coreboot.org/c/coreboot/+/55114/comment/4a004708_efc8ecbc PS2, Line 585: be safely nit: safely be Yes, my mistake. Sorry. -- To view, visit https://review.coreboot.org/c/coreboot/+/55114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60986979d7f7905b312b7d03abd46ac0465ae4cf Gerrit-Change-Number: 55114 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 04 Jun 2021 19:38:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/dell: Add OptiPlex 7020 SFF port
by Angel Pons (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Máté Kukri, Martin Roth, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55232 ) Change subject: [WIP] mb/dell: Add OptiPlex 7020 SFF port ...................................................................... Patch Set 1: (8 comments) Patchset: PS1: I didn't review the obviously-WIP parts, but still left some comments. File src/mainboard/dell/optiplex_7020/Kconfig: https://review.coreboot.org/c/coreboot/+/55232/comment/09b39b48_2dd6144e PS1, Line 22: default 0x100000 Isn't it the default? File src/mainboard/dell/optiplex_7020/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/55232/comment/f28220dd_3fd99b28 PS1, Line 15: Device (PWRB) FADT flags make this unnecessary. File src/mainboard/dell/optiplex_7020/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55232/comment/644b0ab4_f82acbf4 PS1, Line 16: subsystemid 0x1028 0x05a5 Can be inherited, see other boards https://review.coreboot.org/c/coreboot/+/55232/comment/17dcc062_c7ca7179 PS1, Line 57: device pci 1c.3 off end # TODO: what's this? : device pci 1c.4 off end # TODO: what's this? : device pci 1c.5 off end # TODO: what's this? More PCIe ports! Or is it that you don't know if they're actually used? File src/mainboard/dell/optiplex_7020/dsdt.asl: https://review.coreboot.org/c/coreboot/+/55232/comment/0d01193e_c9f35c41 PS1, Line 20: Scope (\_SB) : { : Device (PCI0) : { : #include <northbridge/intel/haswell/acpi/hostbridge.asl> : #include <southbridge/intel/lynxpoint/acpi/pch.asl> : } : } I usually write this as follows: Device (\_SB.PCI0) #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> } File src/mainboard/dell/optiplex_7020/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/55232/comment/e10c7365_37ef460e PS1, Line 11: -- TODO: Add DP ports to the list You can add all of them and look at libgfxinit logs with a DP display attached to see which one is which. Linux can also know via the VBT File src/southbridge/intel/lynxpoint/early_pch.c: https://review.coreboot.org/c/coreboot/+/55232/comment/d7105d0f_e33453da PS1, Line 72: pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0a01); You could set `gen1_dec` in the devicetree, or any other available `genX_dec` -- To view, visit https://review.coreboot.org/c/coreboot/+/55232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a Gerrit-Change-Number: 55232 Gerrit-PatchSet: 1 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 04 Jun 2021 19:28:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Add Kconfig option to enable cbmem logging
by Benjamin Doron (Code Review) 04 Jun '21

04 Jun '21

Attention is currently required from: Martin Roth, Matt DeVillier. Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55144 ) Change subject: payloads/tianocore: Add Kconfig option to enable cbmem logging ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/55144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idef125235dc7ba885eb22ac69c6f752588a9e295 Gerrit-Change-Number: 55144 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Jun 2021 19:16:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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