coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by build bot (Jenkins) (Code Review) 31 May '21

31 May '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... Patch Set 1: (1 comment) File src/drivers/i2c/designware/dw_i2c.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120344): https://review.coreboot.org/c/coreboot/+/55088/comment/af865422_e33c4bcf PS1, Line 836: if (bcfg->speed_config[i].speed && speed != bcfg->speed_config[i].speed ) space prohibited before that close parenthesis ')' -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 31 May 2021 05:30:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_apl2: Disable unused I2C controllers
by Werner Zeh (Code Review) 31 May '21

31 May '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55090 ) Change subject: mb/siemens/mc_apl2: Disable unused I2C controllers ...................................................................... mb/siemens/mc_apl2: Disable unused I2C controllers Only I2C controller 3 is used on this mainboard. Disable all other controllers. Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/55090/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 06f4c05..1749636 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -97,9 +97,9 @@ end device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI - device pci 16.0 on end # - I2C 0 - device pci 16.1 on end # - I2C 1 - device pci 16.2 on end # - I2C 2 + device pci 16.0 off end # - I2C 0 + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 device pci 16.3 on # - I2C 3 # Enable external RTC chip chip drivers/i2c/rx6110sa @@ -115,10 +115,10 @@ device i2c 0x32 on end # RTC RX6110 SA end end - device pci 17.0 on end # - I2C 4 - device pci 17.1 on end # - I2C 5 - device pci 17.2 on end # - I2C 6 - device pci 17.3 on end # - I2C 7 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 device pci 18.0 on end # - UART 0 device pci 18.1 on end # - UART 1 device pci 18.2 on end # - UART 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id06d98787a0574a5b3a8dc2e86858dfcc7154606 Gerrit-Change-Number: 55090 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz
by Werner Zeh (Code Review) 31 May '21

31 May '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55089 ) Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz ...................................................................... mb/siemens/mc_apl{1,2,3,5,6}: Provide I2C timings for 400 kHz The I2C bus at which the external RTC is attached to is operated at standard speed (100 kHz) at coreboot runtime. The OS can chose to run it at fast speed since it uses its own driver and controller set up. Report additional bus timings for fast mode so that OS can do it right. Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb 5 files changed, 35 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/55089/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index b7590fa..20d44bb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -49,7 +49,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 160, .fall_time_ns = 110, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x58, + .scl_lcnt = 0xcf, + .sda_hold = 0x28 + }, }, }" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 336d6c4..06f4c05 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -47,7 +47,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 60, .fall_time_ns = 20, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x68, + .scl_lcnt = 0xd4, + .sda_hold = 0x28 + }, }, }" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 635ff3f..45cfd85 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -44,7 +44,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 40, .fall_time_ns = 10, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x68, + .scl_lcnt = 0xd1, + .sda_hold = 0x28 + }, }, }" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 48b4ad8..2500e08 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -47,7 +47,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 160, .fall_time_ns = 110, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x5b, + .scl_lcnt = 0xce, + .sda_hold = 0x28 + }, }, }" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index e2a3ea0..e058fde 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -18,7 +18,13 @@ .speed = I2C_SPEED_STANDARD, .rise_time_ns = 40, .fall_time_ns = 10, - .data_hold_time_ns = 300 + .data_hold_time_ns = 300, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_hcnt = 0x68, + .scl_lcnt = 0xd1, + .sda_hold = 0x28 + }, } }" -- To view, visit https://review.coreboot.org/c/coreboot/+/55089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82e11e5dde8ad1047713f105c5a6d020eebf1ffd Gerrit-Change-Number: 55089 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Werner Zeh (Code Review) 31 May '21

31 May '21

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... drivers/i2c/designware: Report I2C timings for additional bus speeds Since the OS provides its own driver for the I2C controller it can chose to use a bus speed other than the one used at coreboot runtime. In this case it would be good to provide a way how the needed bus timings are communicated to the OS, since these are very board-specific and there is no way that the OS can know them other than read the appropriate ACPI reported timings. This patch adds some code to report additional bus speed timings if there are some defined in the devicetree. Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/55088/1 diff --git a/src/drivers/i2c/designware/dw_i2c.c b/src/drivers/i2c/designware/dw_i2c.c index 2e2d20d..4d97a38 100644 --- a/src/drivers/i2c/designware/dw_i2c.c +++ b/src/drivers/i2c/designware/dw_i2c.c @@ -803,7 +803,7 @@ struct dw_i2c_speed_config sgen; int bus; const char *path; - unsigned int speed; + unsigned int speed, i; bus = dw_i2c_soc_dev_to_bus(dev); @@ -826,12 +826,17 @@ /* Ensure a default speed is available */ speed = (bcfg->speed == 0) ? I2C_SPEED_FAST : bcfg->speed; - /* Report timing values for the OS driver */ + /* Report currently used timing values for the OS driver */ + acpigen_write_scope(path); if (dw_i2c_gen_speed_config(dw_i2c_addr, speed, bcfg, &sgen) >= 0) { - acpigen_write_scope(path); dw_i2c_acpi_write_speed_config(&sgen); - acpigen_pop_len(); } + /* Now check if there are more speed settings available and report them as well. */ + for (i = 0; i < DW_I2C_SPEED_CONFIG_COUNT; i++) { + if (bcfg->speed_config[i].speed && speed != bcfg->speed_config[i].speed ) + dw_i2c_acpi_write_speed_config(&bcfg->speed_config[i]); + } + acpigen_pop_len(); } static int dw_i2c_dev_transfer(struct device *dev, -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Werner Zeh (Code Review) 31 May '21

31 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55082 ) Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... Patch Set 8: Code-Review+1 (3 comments) File src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55082/comment/070770fe_ca3a3e32 PS8, Line 84: # LPSS Serial IO (I2C/UART/GSPI) related UPDs I would expect this line being part of CB:54959 File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55082/comment/1ba797f8_6835256f PS8, Line 20: DEF_DITOVAL Would you mind to change it to DEF_DITOVAL_MS to clarify that this value is in ms units? https://review.coreboot.org/c/coreboot/+/55082/comment/c3d30f71_905df324 PS8, Line 253: params->SataPortsDmVal[i] = config->SataPortsDmVal[i] ? : config->SataPortsDmVal[i] : DEF_DMVAL; Here you can shorten down the line as you are checking for a value which is assigned in the "true"-case to the variable: 'params->SataPortsDmVal[i] = config->SataPortsDmVal[i] ? : DEF_DMVAL;' Same for the next statement. For details see https://en.wikipedia.org/wiki/%3F:#C -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 8 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 May 2021 04:51:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs
by Werner Zeh (Code Review) 31 May '21

31 May '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55034 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Gerrit-Change-Number: 55034 Gerrit-PatchSet: 9 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 May 2021 04:38:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related set...
by Werner Zeh (Code Review) 31 May '21

31 May '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54960 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related settings ...................................................................... Patch Set 13: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54960/comment/8b4ae094_03aa3f41 PS13, Line 7: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related settings Please try to fit the headline on one line. MAybe something like: soc/intel/elkhartlake:Update FSP-S UPD settings for graphic & chipset https://review.coreboot.org/c/coreboot/+/54960/comment/1ebfc61c_dba208ed PS13, Line 9: Silicon silicon -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 13 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 May 2021 04:16:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
by Werner Zeh (Code Review) 31 May '21

31 May '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54959 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/54959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Gerrit-Change-Number: 54959 Gerrit-PatchSet: 11 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 May 2021 04:02:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI support
by Werner Zeh (Code Review) 31 May '21

31 May '21

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55003 ) Change subject: drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI support ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55003/comment/d194bd63_a830e865 PS3, Line 18: RTC driver. > Which Linux commit added ACPI support for the RTC driver? The ACPI-support for RX6110SA was added in Linux-commit 8d69f62fddf6c1a8c7745120c4d6aab9322b001a -- To view, visit https://review.coreboot.org/c/coreboot/+/55003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6 Gerrit-Change-Number: 55003 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 31 May 2021 03:49:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Move variant_has_fpmcu() after eSPI init
by build bot (Jenkins) (Code Review) 31 May '21

31 May '21

Attention is currently required from: Raul Rangel, Furquan Shaikh, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54740 ) Change subject: mb/google/guybrush: Move variant_has_fpmcu() after eSPI init ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/guybrush/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120343): https://review.coreboot.org/c/coreboot/+/54740/comment/7434f2e2_9b23585a PS3, Line 40: void bootblock_mainboard_init(void){ open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/54740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6de44119e92c8820b266f9f07287706c7d4eb505 Gerrit-Change-Number: 54740 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Mon, 31 May 2021 02:14:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021