coreboot-gerrit May 2021

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Change in coreboot[master]: mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configuration
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54911 ) Change subject: mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configuration ...................................................................... mb/siemens/{mc_apl2,...,mc_apl6}: Do early UART pad configuration With commit 405f229689 (soc/intel/*: drop UART pad configuration from common code) the UART pad configuration was dropped from common SoC code. Through a second commit 5ff17ed393 (mb/siemens/mc_apl1: do UART pad configuration at board-level) the UART pad configuration was made for mc_apl1 baseboard. This change is also needed for all other mc_apl boards. Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54911 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c 5 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c index 4bf4bb5..c94bfb8 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -528,6 +528,9 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ /* Not connected */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, PWROK, NF1, HIZCRx0, SAME), diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c index 40f8e18..8ab0a93 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c @@ -357,6 +357,9 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ /* Debug tracing. */ PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c index 6b4897b..32bc61b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -337,6 +337,10 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ + /* Southwest Community */ /* Multiplexed I2C7 */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c index 04e04db..17958a7 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -357,6 +357,9 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ /* Debug tracing. */ PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c index 081a9cf..8b056cb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/gpio.c @@ -357,6 +357,9 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ /* Debug tracing. */ PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ -- To view, visit https://review.coreboot.org/c/coreboot/+/54911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If78726d9b141e4e7580cca3267f49c1a5b95d7fa Gerrit-Change-Number: 54911 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: merged

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Change in coreboot[master]: arch/x86/acpi_bert_storage: change return type of bert_errors_present
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55023 ) Change subject: arch/x86/acpi_bert_storage: change return type of bert_errors_present ...................................................................... arch/x86/acpi_bert_storage: change return type of bert_errors_present The return value is a boolean, so use the bool type. Also add the types.h header to have the bool type defined. Also change type of bert_region_broken static variable to bool. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55023 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/acpi_bert_storage.c M src/arch/x86/include/arch/bert_storage.h 2 files changed, 8 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index b07b67e..a8b8628 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -8,6 +8,7 @@ #include <acpi/acpi.h> #include <arch/bert_storage.h> #include <string.h> +#include <types.h> /* BERT region management: Allow the chipset to determine the specific * location of the BERT region. We find that base and size, then manage @@ -19,7 +20,7 @@ * resume cycles. If the requirements change, consider using IMD to help * manage the space. */ -static int bert_region_broken; +static bool bert_region_broken; static void *bert_region_base; static size_t bert_region_size; static size_t bert_region_used; @@ -32,9 +33,9 @@ return bert_region_broken ? 0 : bert_region_size - bert_region_used; } -int bert_errors_present(void) +bool bert_errors_present(void) { - return bert_region_broken ? 0 : !!bert_region_used; + return !bert_region_broken && bert_region_used; } void bert_errors_region(void **start, size_t *size) @@ -585,14 +586,14 @@ /* Always start with a blank bert region. Make sure nothing is * maintained across reboots or resumes. */ - bert_region_broken = 0; + bert_region_broken = false; bert_region_used = 0; bert_reserved_region(&bert_region_base, &bert_region_size); if (!bert_region_base || !bert_region_size) { printk(BIOS_ERR, "Bug: Can't find/add BERT storage area\n"); - bert_region_broken = 1; + bert_region_broken = true; return; } diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h index 0d373e1..6378333 100644 --- a/src/arch/x86/include/arch/bert_storage.h +++ b/src/arch/x86/include/arch/bert_storage.h @@ -3,8 +3,8 @@ #ifndef _BERT_STORAGE_H_ #define _BERT_STORAGE_H_ -#include <stdint.h> #include <acpi/acpi.h> +#include <types.h> /* Items in the BERT region * @@ -55,7 +55,7 @@ /* Get amount of available storage left for error info */ size_t bert_storage_remaining(void); /* Find if errors were added, a BERT region is present, and ACPI table needed */ -int bert_errors_present(void); +bool bert_errors_present(void); /* Get the number of entries associated with status */ static inline size_t bert_entry_count(acpi_generic_error_status_t *status) -- To view, visit https://review.coreboot.org/c/coreboot/+/55023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d6472deeb26ba92d257761df069e32d9b2e5d4 Gerrit-Change-Number: 55023 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/elkhartlake: Update FADT table
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54958 ) Change subject: soc/intel/elkhartlake: Update FADT table ...................................................................... soc/intel/elkhartlake: Update FADT table Update FADT table per relevant PM settings: Fix PM Timer block access size and disable C2 and C3 states for the CPU. Further on, set the century byte offset in FADT to point to the common location in CMOS. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54958 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/elkhartlake/acpi.c 1 file changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 0006b5f..a0c966e 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -156,9 +156,14 @@ fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; fadt->x_pm_tmr_blk.addrh = 0x0; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->duty_width = 0x3; /* CLK_VAL bits 3:1 */ + fadt->century = 0x32; if (config->s0ix_enable) fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; -- To view, visit https://review.coreboot.org/c/coreboot/+/54958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188 Gerrit-Change-Number: 54958 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-M UPD related configs
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54892 ) Change subject: soc/intel/elkhartlake: Update FSP-M UPD related configs ...................................................................... soc/intel/elkhartlake: Update FSP-M UPD related configs Upload the FSP-M UPD configs. This CL also updated the chip.h and devicetree.cb with the relevant variables and configs. This CL also updated the GPIO related settings (PMC & SD card) in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/romstage/fsp_params.c 3 files changed, 179 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index bf66e4b..d67b217 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -4,6 +4,48 @@ device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_F" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "Heci2Enable" = "1" + + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + + # Enable All Root Ports (1-7) + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + + register "PcieClkSrcUsage[0]" = "0x00" + register "PcieClkSrcUsage[1]" = "0x06" + register "PcieClkSrcUsage[2]" = "0x04" + register "PcieClkSrcUsage[3]" = "0xFF" + register "PcieClkSrcUsage[4]" = "0xFF" + register "PcieClkSrcUsage[5]" = "0xFF" + + register "PcieClkSrcClkReq[0]" = "0x0" + register "PcieClkSrcClkReq[1]" = "0x1" + register "PcieClkSrcClkReq[2]" = "0x2" + register "PcieClkSrcClkReq[3]" = "0x3" + register "PcieClkSrcClkReq[4]" = "0x4" + register "PcieClkSrcClkReq[5]" = "0x5" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 94174cf..ce09841 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -19,9 +19,10 @@ #include <soc/usb.h> #include <stdint.h> -#define MAX_HD_AUDIO_DMIC_LINKS 2 -#define MAX_HD_AUDIO_SNDW_LINKS 4 -#define MAX_HD_AUDIO_SSP_LINKS 6 +#define MAX_HD_AUDIO_SDI_LINKS 2 +#define MAX_HD_AUDIO_DMIC_LINKS 2 +#define MAX_HD_AUDIO_SNDW_LINKS 4 +#define MAX_HD_AUDIO_SSP_LINKS 6 struct soc_intel_elkhartlake_config { @@ -63,16 +64,15 @@ /* TCC activation offset */ uint32_t tcc_offset; - /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. - * When enabled memory will be training at two different frequencies. - * 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, - * 4:FixedPoint3, 5:Enabled */ + /* System Agent dynamic frequency support. + * When enabled memory will be trained at different frequencies. + * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2 + * (high), 4:Enabled */ enum { SaGv_Disabled, SaGv_FixedPoint0, SaGv_FixedPoint1, SaGv_FixedPoint2, - SaGv_FixedPoint3, SaGv_Enabled, } SaGv; @@ -96,12 +96,10 @@ /* Audio related */ uint8_t PchHdaDspEnable; uint8_t PchHdaAudioLinkHdaEnable; + uint8_t PchHdaSdiEnable[MAX_HD_AUDIO_SDI_LINKS]; uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; - uint8_t PchHdaIDispLinkTmode; - uint8_t PchHdaIDispLinkFrequency; - uint8_t PchHdaIDispCodecDisconnect; /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; @@ -129,6 +127,10 @@ uint8_t SdCardPowerEnableActiveHigh; /* Gfx related */ + uint8_t Heci2Enable; + uint8_t Heci3Enable; + + /* Gfx related */ uint8_t SkipExtGfxScan; uint8_t Device4Enable; @@ -198,10 +200,6 @@ /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ bool CnviBtAudioOffload; - /* Tcss */ - uint8_t TcssXhciEn; - uint8_t TcssXdciEn; - /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/elkhartlake/romstage/fsp_params.c b/src/soc/intel/elkhartlake/romstage/fsp_params.c index 464e1d4..5264a74 100644 --- a/src/soc/intel/elkhartlake/romstage/fsp_params.c +++ b/src/soc/intel/elkhartlake/romstage/fsp_params.c @@ -1,16 +1,138 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <console/console.h> #include <device/device.h> #include <fsp/util.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/soc_chip.h> +#include <string.h> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_elkhartlake_config *config) { - /* TODO: Update with UPD details as FSP matures */ + unsigned int i; + const struct device *dev; + uint32_t mask = 0; + + /* + * If IGD is enabled, set IGD stolen size to 60MB. + * Otherwise, skip IGD init in FSP. + */ + dev = pcidev_path_on_root(SA_DEVFN_IGD); + m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev); + m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; + + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->RMT = config->RMT; + + /* PCIe root port configuration */ + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + + m_cfg->PcieRpEnableMask = mask; + + _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcUsage) >= + ARRAY_SIZE(config->PcieClkSrcUsage), "copy buffer overflow!"); + memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage)); + + _Static_assert(ARRAY_SIZE(m_cfg->PcieClkSrcClkReq) >= + ARRAY_SIZE(config->PcieClkSrcClkReq), "copy buffer overflow!"); + memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + + m_cfg->PrmrrSize = config->PrmrrSize; + + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + + /* Set CPU Ratio */ + m_cfg->CpuRatio = 0; + + /* Set debug interface flags */ + m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; + + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (is_dev_enabled(dev) && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + } + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + /* PCH Master Gating Control */ + m_cfg->PchMasterClockGating = 1; + m_cfg->PchMasterPowerGating = 1; + + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT; + + /* DMAR related config */ + m_cfg->VtdDisable = 0; + m_cfg->X2ApicOptOut = 0x1; + if (m_cfg->InternalGfx) { + m_cfg->VtdIgdEnable = 0x1; + m_cfg->DisableTeIgd = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + } + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; + + /* DllBwEn0/1/2/3, per frequency */ + m_cfg->DllBwEn0 = 0; + m_cfg->DllBwEn1 = 0; + m_cfg->DllBwEn2 = 0; + m_cfg->DllBwEn3 = 0; + + /* Disable and Lock Watch Dog Register */ + m_cfg->WdtDisableAndLock = 0x1; + + m_cfg->HeciCommunication2 = config->Heci2Enable; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + + /* Audio */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + m_cfg->PchHdaEnable = is_dev_enabled(dev); + m_cfg->PchHdaDspEnable = config->PchHdaDspEnable; + m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable; + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaSdiEnable) >= + ARRAY_SIZE(config->PchHdaSdiEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaSdiEnable, config->PchHdaSdiEnable, + sizeof(config->PchHdaSdiEnable)); + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkDmicEnable) >= + ARRAY_SIZE(config->PchHdaAudioLinkDmicEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable, + sizeof(config->PchHdaAudioLinkDmicEnable)); + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSspEnable) >= + ARRAY_SIZE(config->PchHdaAudioLinkSspEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable, + sizeof(config->PchHdaAudioLinkSspEnable)); + + _Static_assert(ARRAY_SIZE(m_cfg->PchHdaAudioLinkSndwEnable) >= + ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!"); + memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, + sizeof(config->PchHdaAudioLinkSndwEnable)); + + /* Skip the CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck; + + /* Processor Early Power On Configuration FCLK setting */ + m_cfg->FClkFrequency = 0x1; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) @@ -20,13 +142,10 @@ soc_memory_init_params(m_cfg, config); - /* Set debug probe type */ - m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT; - mainboard_memory_init_params(mupd); } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* TODO: Update later together with UPD updates */ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } -- To view, visit https://review.coreboot.org/c/coreboot/+/54892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Gerrit-Change-Number: 54892 Gerrit-PatchSet: 9 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Apply more uses for Kconfig TPM
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55016 ) Change subject: Apply more uses for Kconfig TPM ...................................................................... Apply more uses for Kconfig TPM Change-Id: I54b296563940cd46fe9da9fe789b746f2fc1987d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55016 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/drivers/tpm/Kconfig M src/security/intel/txt/Kconfig M src/security/tpm/Kconfig M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 5 files changed, 7 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Aaron Durbin: Looks good to me, approved Julius Werner: Looks good to me, approved diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig index 79b860f..735cfee 100644 --- a/src/drivers/tpm/Kconfig +++ b/src/drivers/tpm/Kconfig @@ -1,6 +1,6 @@ config TPM_INIT_RAMSTAGE bool - default y if TPM1 || TPM2 + default y if TPM depends on !VBOOT && !VENDORCODE_ELTAN_VBOOT && !VENDORCODE_ELTAN_MBOOT \ && !TPM_MEASURED_BOOT_INIT_BOOTBLOCK help @@ -9,7 +9,7 @@ config TPM_PPI bool "Generate ACPI code to implement TPM physical presence interface" - depends on TPM1 || TPM2 + depends on TPM depends on HAVE_ACPI_TABLES depends on !CHROMEOS default y if PAYLOAD_TIANOCORE diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 14b4f6a..3648925 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -7,7 +7,7 @@ select ENABLE_VMX if CPU_INTEL_COMMON select AP_IN_SIPI_WAIT select TPM_MEASURED_BOOT_INIT_BOOTBLOCK if TPM_MEASURED_BOOT - depends on (TPM1 || TPM2) + depends on TPM depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE depends on PLATFORM_HAS_DRAM_CLEAR depends on (SOC_INTEL_COMMON_BLOCK_SA || HAVE_CF9_RESET) diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index e228a3d..4864f12 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -70,7 +70,7 @@ bool "Output verbose TPM debug messages" default n select DRIVER_TPM_DISPLAY_TIS_BYTES if I2C_TPM - depends on TPM1 || TPM2 + depends on TPM help This option enables additional TPM related debug messages. @@ -96,7 +96,7 @@ bool "Enable Measured Boot" default n select VBOOT_LIB - depends on TPM1 || TPM2 + depends on TPM depends on !VBOOT_RETURN_FROM_VERSTAGE help Enables measured boot (experimental) diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 515efc7..0368758 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -13,7 +13,7 @@ bool "Verify firmware with vboot." default n select VBOOT_LIB - select VBOOT_MOCK_SECDATA if !TPM1 && !TPM2 + select VBOOT_MOCK_SECDATA if !TPM depends on 0 = 0 # Must have a 'depends on' or board overrides will break it. help Enabling VBOOT will use vboot to verify the components of the firmware diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 668d3d9..47830f3 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -109,9 +109,7 @@ ramstage-y += secdata_tpm.c endif -ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) -verstage-y += tpm_common.c -endif +verstage-$(CONFIG_TPM) += tpm_common.c romstage-y += common.c -- To view, visit https://review.coreboot.org/c/coreboot/+/55016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b296563940cd46fe9da9fe789b746f2fc1987d Gerrit-Change-Number: 55016 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55082 to look at the new patch set (#8). Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 80 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 8 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55082 to look at the new patch set (#7). Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 80 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 7 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related set...
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54960 to look at the new patch set (#13). Change subject: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related settings ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related settings Further add initial Silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/fsp_params.c 2 files changed, 63 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/54960/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 13 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [NOTFORMERGE]link Agesa into bootblock
by Paul Menzel (Code Review) 30 May '21

30 May '21

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55070 ) Change subject: [NOTFORMERGE]link Agesa into bootblock ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Successfully tested on Asus F2A85-M PRO with Idec3832d8d1ab95ae9747ce87792ee7b474540c7 (sb/amd/hudson: Skip setting up LPC decode for base < 0x20) [1] cherry-picked on top. ``` $ more defconfig CONFIG_ANY_TOOLCHAIN=y CONFIG_VENDOR_ASUS=y CONFIG_VGA_BIOS_ID="1002,9996" CONFIG_VGA_BIOS=y CONFIG_BOARD_ASUS_F2A85_M_PRO=y CONFIG_SEABIOS_MASTER=y $ grep SEPARATE_ROMSTAGE .config CONFIG_SEPARATE_ROMSTAGE=y ``` ``` FMAP REGION: COREBOOT Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/ramstage 0x80 stage 129931 LZMA (295660 decompressed) config 0x1fc80 raw 208 none (empty) 0x1fd80 null 36 none apu/amdfw 0x1fdc0 raw 69632 none fallback/romstage 0x30e00 stage 313904 none revision 0x7d8c0 raw 716 none build_info 0x7dbc0 raw 97 none fallback/dsdt.aml 0x7dc80 raw 6458 none cmos_layout.bin 0x7f600 cmos_layout 616 none pci1002,9996.rom 0x7f8c0 optionrom 61952 none fallback/postcar 0x8eb00 stage 18760 none fallback/payload 0x934c0 simple elf 70504 none payload_config 0xa4880 raw 1621 none payload_revision 0xa4f00 raw 233 none (empty) 0xa5040 null 6663524 none s3nv 0x6ffdc0 raw 8192 none (empty) 0x701e00 null 1027236 none bootblock 0x7fcac0 bootblock 13056 none Built asus/f2a85-m (F2A85-M_PRO) ``` [1]: https://review.coreboot.org/c/coreboot/+/54669 -- To view, visit https://review.coreboot.org/c/coreboot/+/55070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4c71b9c9a245e07d713839fb3628cbfc0dc3457 Gerrit-Change-Number: 55070 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 30 May 2021 17:50:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55082 to look at the new patch set (#6). Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 81 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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