coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related set...
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54960 to look at the new patch set (#12). Change subject: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related settings ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related settings Further add initial Silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/fsp_params.c 2 files changed, 63 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/54960/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 12 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55034 to look at the new patch set (#7). Change subject: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 111 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/55034/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/55034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Gerrit-Change-Number: 55034 Gerrit-PatchSet: 7 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55082 to look at the new patch set (#4). Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 72 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related set...
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54960 to look at the new patch set (#11). Change subject: soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related settings ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD graphic & chipset related settings Further add initial Silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/fsp_params.c 2 files changed, 63 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/54960/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/54960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Gerrit-Change-Number: 54960 Gerrit-PatchSet: 11 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55082 to look at the new patch set (#3). Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 73 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S storage related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Hello Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55082 to look at the new patch set (#2). Change subject: soc/intel/elkhartlake: Update FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 80 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 2 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/elkhartlake: FSP-S storage related configs
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55082 ) Change subject: soc/intel/elkhartlake: FSP-S storage related configs ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/elkhartlake/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120328): https://review.coreboot.org/c/coreboot/+/55082/comment/b1851bb7_4cb79b6c PS1, Line 248: params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i].enable ? line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 May 2021 16:14:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: FSP-S storage related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55082 ) Change subject: soc/intel/elkhartlake: FSP-S storage related configs ...................................................................... soc/intel/elkhartlake: FSP-S storage related configs Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 4 files changed, 79 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/55082/1 diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index be2b6c9..b3e3027 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -70,6 +70,19 @@ register "PcieClkSrcClkReq[4]" = "0x4" register "PcieClkSrcClkReq[5]" = "0x5" + # Storage (SATA/SDCARD/EMMC) related UPDs + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "1" + + register "ScsEmmcHs400Enabled" = "1" + register "ScsEmmcDdr50Enabled" = "1" + register "SdCardPowerEnableActiveHigh" = "1" + + # LPSS Serial IO (I2C/UART/GSPI) related UPDs register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index b55884c..a522db5 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -109,6 +109,10 @@ int default 7 +config MAX_SATA_PORTS + int + default 2 + config MAX_PCIE_CLOCK_SRC int default 6 diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index ebe14d5..c0dc58c 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -90,8 +90,21 @@ /* SATA related */ uint8_t SataMode; uint8_t SataSalpSupport; - uint8_t SataPortsEnable[8]; - uint8_t SataPortsDevSlp[8]; + uint8_t SataPortsEnable[CONFIG_MAX_SATA_PORTS]; + uint8_t SataPortsDevSlp[CONFIG_MAX_SATA_PORTS]; + + /* eMMC related */ + uint8_t ScsEmmcHs400Enabled; + uint8_t ScsEmmcDdr50Enabled; + + /* Enable if SD Card Power Enable Signal is Active High */ + uint8_t SdCardPowerEnableActiveHigh; + + /* + * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. + * Default 0. Setting this to 1 disables the SATA Power Optimizer. + */ + uint8_t SataPwrOptimizeDisable; /* Audio related */ uint8_t PchHdaDspEnable; diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 69a99e8..4bd29cb 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -15,6 +15,13 @@ #include <soc/soc_chip.h> #include <string.h> +/* SATA DEVSLP idle timeout default values */ +#define DEF_DMVAL 15 +#define DEF_DITOVAL 625 + +/* Native function controls pads termination */ +#define GPIO_TERM_NATIVE 0x1F + /* * Chip config parameter PcieRpL1Substates uses (UPD value + 1) * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. @@ -224,6 +231,46 @@ params->PcieRpVc1TcMap[i] = 0x60; } + /* SATA */ + dev = pcidev_path_on_root(PCH_DEVFN_SATA); + params->SataEnable = is_dev_enabled(dev); + if (params->SataEnable) { + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); + + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + params->SataPortsEnable[i] = config->SataPortsEnable[i]; + params->SataPortsDevSlp[i] = config->SataPortsDevSlp[i]; + if (config->SataPortsEnableDitoConfig[i]) { + params->SataPortsDmVal[i] = config->SataPortsDmVal[i].enable ? + config->SataPortsDmVal[i] : DEF_DMVAL; + params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i].enable ? + config->SataPortsDitoVal[i] : DEF_DITOVAL; + } + } + } + + /* SDCard related configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + params->ScsSdCardEnabled = is_dev_enabled(dev); + if (params->ScsSdCardEnabled) { + params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; + params->SdCardGpioCmdPadTermination = GPIO_TERM_NATIVE; + params->SdCardGpioDataPadTermination[0] = GPIO_TERM_NATIVE; + params->SdCardGpioDataPadTermination[1] = GPIO_TERM_NATIVE; + params->SdCardGpioDataPadTermination[2] = GPIO_TERM_NATIVE; + params->SdCardGpioDataPadTermination[3] = GPIO_TERM_NATIVE; + } + + /* eMMC configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + params->ScsEmmcEnabled = is_dev_enabled(dev); + if (params->ScsEmmcEnabled) { + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled; + } + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Gerrit-Change-Number: 55082 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55034 ) Change subject: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55034/comment/468243f4_0e30a057 PS2, Line 10: root ports > PCIe root ports Done File src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb: https://review.coreboot.org/c/coreboot/+/55034/comment/4b809184_888fff5d PS2, Line 50: Root Ports > PCIe root ports Done File src/soc/intel/elkhartlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/55034/comment/ae29a659_0a6de576 PS2, Line 215: RP Configs > PCIe root ports config Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Gerrit-Change-Number: 55034 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sun, 30 May 2021 14:21:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs
by Lean Sheng Tan (Code Review) 30 May '21

30 May '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Mario Scheithauer, Subrata Banik, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55034 to look at the new patch set (#6). Change subject: soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs ...................................................................... soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configs Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 --- M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/soc/intel/elkhartlake/chip.h M src/soc/intel/elkhartlake/fsp_params.c 3 files changed, 108 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/55034/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/55034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Gerrit-Change-Number: 55034 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021