coreboot-gerrit May 2021

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Change in coreboot[master]: HACK sc7280: Add PCIe RC driver in Coreboot HACK
by Ravi kumar (Code Review) 30 May '21

30 May '21

Attention is currently required from: Taniya Das. Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55081 to review the following change. Change subject: HACK sc7280: Add PCIe RC driver in Coreboot HACK ...................................................................... HACK sc7280: Add PCIe RC driver in Coreboot HACK As part of clock driver cleanup, renamed the clock api in pcie driver. Change-Id: I603d5a35ab4aab1cd91d60976b62ca0c15a7357c Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/pcie_host.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/55081/1 diff --git a/src/soc/qualcomm/sc7280/pcie_host.c b/src/soc/qualcomm/sc7280/pcie_host.c index b2b227c..cb7bd94 100644 --- a/src/soc/qualcomm/sc7280/pcie_host.c +++ b/src/soc/qualcomm/sc7280/pcie_host.c @@ -1061,7 +1061,7 @@ qcom_ep_reset_assert(pcierc->perst); /* Enable gdsc before enable pcie clocks */ - ret = pcie_enable_gdsc(PCIE_1_GDSC); + ret = clock_enable_gdsc(PCIE_1_GDSC); if (ret) { printk(BIOS_ERR, "Failed to enable gdsc\n"); return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/55081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I603d5a35ab4aab1cd91d60976b62ca0c15a7357c Gerrit-Change-Number: 55081 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK HACK soc: qcom: Update the GPIO macro for consumers HACK HACK
by Ravi kumar (Code Review) 30 May '21

30 May '21

Attention is currently required from: Taniya Das. Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55080 to review the following change. Change subject: HACK HACK soc: qcom: Update the GPIO macro for consumers HACK HACK ...................................................................... HACK HACK soc: qcom: Update the GPIO macro for consumers HACK HACK As we are proceeding to use the common gpio driver across qcom chipsets, the gpio macros used across drivers need to be renamed as per the latest gpio changes. Change-Id: I97656a7399c018f8508525ae7cbcffe7fad956e2 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/qspi.c M src/soc/qualcomm/sc7180/qupv3_i2c.c M src/soc/qualcomm/sc7280/pcie_host.c M src/soc/qualcomm/sc7280/qspi.c M src/soc/qualcomm/sc7280/qupv3_i2c.c 5 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/55080/1 diff --git a/src/soc/qualcomm/sc7180/qspi.c b/src/soc/qualcomm/sc7180/qspi.c index c1e9779..825e298 100644 --- a/src/soc/qualcomm/sc7180/qspi.c +++ b/src/soc/qualcomm/sc7180/qspi.c @@ -146,13 +146,13 @@ gpio_output(GPIO(68), 1); gpio_configure(GPIO(64), GPIO64_FUNC_QSPI_DATA_0, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); gpio_configure(GPIO(65), GPIO65_FUNC_QSPI_DATA_1, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); gpio_configure(GPIO(63), GPIO63_FUNC_QSPI_CLK, - GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT_ENABLE); + GPIO_NO_PULL, GPIO_8MA, GPIO_OUTPUT); } static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, diff --git a/src/soc/qualcomm/sc7180/qupv3_i2c.c b/src/soc/qualcomm/sc7180/qupv3_i2c.c index c9adba4..5dc4d31 100644 --- a/src/soc/qualcomm/sc7180/qupv3_i2c.c +++ b/src/soc/qualcomm/sc7180/qupv3_i2c.c @@ -92,9 +92,9 @@ /* GPIO Configuration */ gpio_configure(qup[bus].pin[0], qup[bus].func[0], GPIO_PULL_UP, - GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_2MA, GPIO_OUTPUT); gpio_configure(qup[bus].pin[1], qup[bus].func[1], GPIO_PULL_UP, - GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_2MA, GPIO_OUTPUT); /* Select and setup FIFO mode */ write32(&regs->geni_m_irq_clear, 0xFFFFFFFF); diff --git a/src/soc/qualcomm/sc7280/pcie_host.c b/src/soc/qualcomm/sc7280/pcie_host.c index 81b37f2..b2b227c 100644 --- a/src/soc/qualcomm/sc7280/pcie_host.c +++ b/src/soc/qualcomm/sc7280/pcie_host.c @@ -447,7 +447,7 @@ static void configure_pcie_gpios(gpio_t perst_gpio) { gpio_configure(perst_gpio, 0, GPIO_NO_PULL, - GPIO_16MA, GPIO_OUTPUT_ENABLE); + GPIO_16MA, GPIO_OUTPUT); printk(BIOS_INFO, "pcie ep PERST GPIO configured\n"); } diff --git a/src/soc/qualcomm/sc7280/qspi.c b/src/soc/qualcomm/sc7280/qspi.c index a6837bc..4941425 100644 --- a/src/soc/qualcomm/sc7280/qspi.c +++ b/src/soc/qualcomm/sc7280/qspi.c @@ -146,13 +146,13 @@ gpio_output(GPIO(15), 1); gpio_configure(GPIO(12), GPIO12_FUNC_QSPI_DATA_0, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); gpio_configure(GPIO(13), GPIO13_FUNC_QSPI_DATA_1, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); gpio_configure(GPIO(14), GPIO14_FUNC_QSPI_CLK, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); } static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, diff --git a/src/soc/qualcomm/sc7280/qupv3_i2c.c b/src/soc/qualcomm/sc7280/qupv3_i2c.c index c9adba4..5dc4d31 100644 --- a/src/soc/qualcomm/sc7280/qupv3_i2c.c +++ b/src/soc/qualcomm/sc7280/qupv3_i2c.c @@ -92,9 +92,9 @@ /* GPIO Configuration */ gpio_configure(qup[bus].pin[0], qup[bus].func[0], GPIO_PULL_UP, - GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_2MA, GPIO_OUTPUT); gpio_configure(qup[bus].pin[1], qup[bus].func[1], GPIO_PULL_UP, - GPIO_2MA, GPIO_OUTPUT_ENABLE); + GPIO_2MA, GPIO_OUTPUT); /* Select and setup FIFO mode */ write32(&regs->geni_m_irq_clear, 0xFFFFFFFF); -- To view, visit https://review.coreboot.org/c/coreboot/+/55080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97656a7399c018f8508525ae7cbcffe7fad956e2 Gerrit-Change-Number: 55080 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Add target specific GPIO pin definitions
by Ravi kumar (Code Review) 30 May '21

30 May '21

Attention is currently required from: Taniya Das. Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55079 to review the following change. Change subject: sc7180: Add target specific GPIO pin definitions ...................................................................... sc7180: Add target specific GPIO pin definitions The common gpio driver can be re-used for SC7180, thus remove the existing gpio driver support and also cleanup the common macro definitions. Add GPIO pin details specific to SC7180 chipset for the consumers to be able to request for the gpio functionality as per their requirement. BUG=b:182963902 TEST=Validated on qualcomm sc7180 development board Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268 --- M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/gpio.c M src/soc/qualcomm/sc7180/include/soc/gpio.h 3 files changed, 3 insertions(+), 214 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/55079/1 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index e347365..e84dcc8 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -6,7 +6,7 @@ decompressor-y += ../common/timer.c all-y += ../common/timer.c all-y += spi.c -all-y += gpio.c +all-y += ../common/gpio.c all-y += qupv3_i2c.c all-y += qupv3_spi.c all-y += clock.c diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c deleted file mode 100644 index 67204e8..0000000 --- a/src/soc/qualcomm/sc7180/gpio.c +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <assert.h> -#include <device/mmio.h> -#include <types.h> - -#include <gpio.h> - -void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, - uint32_t drive_str, uint32_t enable) -{ - uint32_t reg_val; - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - - /* gpio pull only PULLNONE, PULLUP, KEEPER, PULLDOWN status */ - assert(pull <= GPIO_PULL_UP); - - reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | - ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | - ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | - ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); - - write32(&regs->cfg, reg_val); -} - -void gpio_set(gpio_t gpio, int value) -{ - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - - write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); -} - -int gpio_get(gpio_t gpio) -{ - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - - return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & - GPIO_IO_IN_BMSK); -} - -void gpio_input_pulldown(gpio_t gpio) -{ - gpio_configure(gpio, GPIO_FUNC_GPIO, - GPIO_PULL_DOWN, GPIO_2MA, GPIO_OUTPUT_DISABLE); -} - -void gpio_input_pullup(gpio_t gpio) -{ - gpio_configure(gpio, GPIO_FUNC_GPIO, - GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT_DISABLE); -} - -void gpio_input(gpio_t gpio) -{ - gpio_configure(gpio, GPIO_FUNC_GPIO, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_DISABLE); -} - -void gpio_output(gpio_t gpio, int value) -{ - gpio_set(gpio, value); - gpio_configure(gpio, GPIO_FUNC_GPIO, - GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); -} - -void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) -{ - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - - gpio_configure(gpio, GPIO_FUNC_GPIO, - pull, GPIO_2MA, GPIO_OUTPUT_DISABLE); - - clrsetbits32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK << - GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); - clrsetbits32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE - << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE - << GPIO_INTR_RAW_STATUS_EN_SHIFT); -} - -int gpio_irq_status(gpio_t gpio) -{ - struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; - - if (!(read32(&regs->intr_status) & GPIO_INTR_STATUS_MASK)) - return 0; - - write32(&regs->intr_status, GPIO_INTR_STATUS_DISABLE); - return 1; -} diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h index 8bfa36e..c044157 100644 --- a/src/soc/qualcomm/sc7180/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h @@ -5,112 +5,10 @@ #include <types.h> #include <soc/addressmap.h> - -typedef struct { - u32 addr; -} gpio_t; - -#define TLMM_TILE_SIZE 0x00400000 -#define TLMM_GPIO_OFF_DELTA 0x00001000 -#define TLMM_GPIO_TILE_NUM 3 - -#define TLMM_GPIO_IN_OUT_OFF 0x4 -#define TLMM_GPIO_ID_STATUS_OFF 0x10 - -#define GPIO_FUNC_GPIO 0 - -/* GPIO INTR CFG MASK */ -#define GPIO_INTR_DECT_CTL_MASK 0x3 -#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 - -/* GPIO INTR CFG SHIFT */ -#define GPIO_INTR_DECT_CTL_SHIFT 2 -#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 - -/* GPIO INTR STATUS MASK */ -#define GPIO_INTR_STATUS_MASK 0x1 - -/* GPIO INTR RAW STATUS */ -#define GPIO_INTR_RAW_STATUS_ENABLE 1 -#define GPIO_INTR_RAW_STATUS_DISABLE 0 - -/* GPIO INTR STATUS */ -#define GPIO_INTR_STATUS_ENABLE 1 -#define GPIO_INTR_STATUS_DISABLE 0 - -/* GPIO INTR CFG MASK */ -#define GPIO_INTR_DECT_CTL_MASK 0x3 -#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 - -/* GPIO INTR CFG SHIFT */ -#define GPIO_INTR_DECT_CTL_SHIFT 2 -#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 - -/* GPIO INTR STATUS MASK */ -#define GPIO_INTR_STATUS_MASK 0x1 - -/* GPIO INTR RAW STATUS */ -#define GPIO_INTR_RAW_STATUS_ENABLE 1 -#define GPIO_INTR_RAW_STATUS_DISABLE 0 - -/* GPIO INTR STATUS */ -#define GPIO_INTR_STATUS_ENABLE 1 -#define GPIO_INTR_STATUS_DISABLE 0 - -/* GPIO TLMM: Direction */ -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 - -/* GPIO TLMM: Pullup/Pulldown */ -#define GPIO_NO_PULL 0 -#define GPIO_PULL_DOWN 1 -#define GPIO_KEEPER 2 -#define GPIO_PULL_UP 3 - -/* GPIO TLMM: Drive Strength */ -#define GPIO_2MA 0 -#define GPIO_4MA 1 -#define GPIO_6MA 2 -#define GPIO_8MA 3 -#define GPIO_10MA 4 -#define GPIO_12MA 5 -#define GPIO_14MA 6 -#define GPIO_16MA 7 - -/* GPIO TLMM: Status */ -#define GPIO_OUTPUT_DISABLE 0 -#define GPIO_OUTPUT_ENABLE 1 - -/* GPIO TLMM: Mask */ -#define GPIO_CFG_PULL_BMSK 0x3 -#define GPIO_CFG_FUNC_BMSK 0xF -#define GPIO_CFG_DRV_BMSK 0x7 -#define GPIO_CFG_OE_BMSK 0x1 - -/* GPIO TLMM: Shift */ -#define GPIO_CFG_PULL_SHFT 0 -#define GPIO_CFG_FUNC_SHFT 2 -#define GPIO_CFG_DRV_SHFT 6 -#define GPIO_CFG_OE_SHFT 9 - -/* GPIO IO: Mask */ -#define GPIO_IO_IN_BMSK 0x1 -#define GPIO_IO_OUT_BMSK 0x1 - -/* GPIO IO: Shift */ -#define GPIO_IO_IN_SHFT 0 -#define GPIO_IO_OUT_SHFT 1 - -/* GPIO ID STATUS: Mask */ -#define GPIO_ID_STATUS_BMSK 0x1 - -/* GPIO MAX Valid # */ -#define GPIO_NUM_MAX 118 - -#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) +#include <soc/gpio_common.h> #define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \ -GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + (index * 0x1000), \ GPIO##index##_FUNC_##func1 = 1, \ GPIO##index##_FUNC_##func2 = 2, \ GPIO##index##_FUNC_##func3 = 3, \ @@ -265,24 +163,4 @@ RES_6, RES_7), PIN(118, WEST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7), }; - -enum gpio_irq_type { - IRQ_TYPE_LEVEL = 0, - IRQ_TYPE_RISING_EDGE = 1, - IRQ_TYPE_FALLING_EDGE = 2, - IRQ_TYPE_DUAL_EDGE = 3, -}; - -struct tlmm_gpio { - uint32_t cfg; - uint32_t in_out; - uint32_t intr_cfg; - uint32_t intr_status; -}; - -void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, - uint32_t drive_str, uint32_t enable); -void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); -int gpio_irq_status(gpio_t gpio); - #endif /* _SOC_QUALCOMM_SC7180_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd206e6bc9a549706e7a2c4bde0b7d5527ca6268 Gerrit-Change-Number: 55079 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: gpio: eGPIO support on sc7280
by Ravi kumar (Code Review) 30 May '21

30 May '21

Attention is currently required from: Taniya Das. Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55078 to review the following change. Change subject: sc7280: gpio: eGPIO support on sc7280 ...................................................................... sc7280: gpio: eGPIO support on sc7280 eGPIO is a scheme which allows special power island domain IOs to be reused as regular chip GPIOs by muxing regular TLMM functions with Island Domain functions. With this scheme, an IO can be controlled both by APPS and Island processor. This change provides an API to configure the eGPIO's. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Change-Id: I2c54a14c50fb7b5921d1961d2de83098ed2d4358 --- M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/include/soc/gpio.h A src/soc/qualcomm/sc7280/sc7280_egpio.c 3 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/55078/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index abcc3fb..7462664 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -3,6 +3,7 @@ all-y += ../common/timer.c all-y += spi.c all-y += ../common/gpio.c +all-y += sc7280_egpio.c ################################################################################ bootblock-y += bootblock.c diff --git a/src/soc/qualcomm/sc7280/include/soc/gpio.h b/src/soc/qualcomm/sc7280/include/soc/gpio.h index 6d6d0cd..b12aa70 100644 --- a/src/soc/qualcomm/sc7280/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7280/include/soc/gpio.h @@ -192,4 +192,16 @@ PIN(174, RES_1, RES_2, RES_3, RES_4), }; +enum egpio_cfg { + EGPIO_CFG_BMSK = 0x1, + EGPIO_CFG_SHFT = 11, + EGPIO_CFG_EN = 12, +}; + +struct egpio { + gpio_t index; +}; + +int egpio_configure_all(void); + #endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */ diff --git a/src/soc/qualcomm/sc7280/sc7280_egpio.c b/src/soc/qualcomm/sc7280/sc7280_egpio.c new file mode 100644 index 0000000..1fdc1e8 --- /dev/null +++ b/src/soc/qualcomm/sc7280/sc7280_egpio.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <gpio.h> + +static struct egpio egpio_list[] = { + {GPIO(144)}, + {GPIO(145)}, + {GPIO(146)}, + {GPIO(147)}, + {GPIO(148)}, + {GPIO(149)}, + {GPIO(150)}, + {GPIO(151)}, + {GPIO(152)}, + {GPIO(153)}, + {GPIO(154)}, + {GPIO(155)}, + {GPIO(156)}, + {GPIO(157)}, + {GPIO(158)}, + {GPIO(159)}, + {GPIO(160)}, + {GPIO(161)}, + {GPIO(162)}, + {GPIO(163)}, + {GPIO(164)}, + {GPIO(165)}, + {GPIO(166)}, + {GPIO(167)}, + {GPIO(168)}, + {GPIO(169)}, + {GPIO(170)}, + {GPIO(171)}, + {GPIO(172)}, + {GPIO(173)}, + {GPIO(174)}, +}; + +int egpio_configure_all(void) +{ + struct tlmm_gpio *regs; + int idx; + + for (idx = 0; idx < ARRAY_SIZE(egpio_list); idx++) { + regs = (void *)(uintptr_t)egpio_list[idx].index.addr; + + if (!((read32(&regs->cfg) >> EGPIO_CFG_SHFT) & + EGPIO_CFG_BMSK)) { + printk(BIOS_ERR, + "ERROR: eGPIO index %d is not a valid eGPIO\n", + idx); + continue; + } + setbits32(&regs->cfg, BIT(EGPIO_CFG_EN)); + } + + return CB_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/55078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c54a14c50fb7b5921d1961d2de83098ed2d4358 Gerrit-Change-Number: 55078 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: Add target specific GPIO pin definitions
by Ravi kumar (Code Review) 30 May '21

30 May '21

Attention is currently required from: Taniya Das. Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55077 to review the following change. Change subject: sc7280: Add target specific GPIO pin definitions ...................................................................... sc7280: Add target specific GPIO pin definitions Add GPIO pin details specific to SC7280 chipset for the consumers to be able to request for the gpio functionality as per their requirement. BUG=b:182963902 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc --- M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/include/soc/addressmap.h M src/soc/qualcomm/sc7280/include/soc/gpio.h 3 files changed, 198 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/55077/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 3fc9d88..abcc3fb 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -2,6 +2,7 @@ all-y += ../common/timer.c all-y += spi.c +all-y += ../common/gpio.c ################################################################################ bootblock-y += bootblock.c diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h new file mode 100644 index 0000000..7fa9136 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ +#define _SOC_QUALCOMM_SC7280_ADDRESS_MAP_H_ + +#include <stdint.h> + +#define TLMM_TILE_BASE 0x0F100000 + +#endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ + diff --git a/src/soc/qualcomm/sc7280/include/soc/gpio.h b/src/soc/qualcomm/sc7280/include/soc/gpio.h index 82a0c39..6d6d0cd 100644 --- a/src/soc/qualcomm/sc7280/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7280/include/soc/gpio.h @@ -4,9 +4,192 @@ #define _SOC_QUALCOMM_SC7280_GPIO_H_ #include <types.h> +#include <soc/addressmap.h> +#include <soc/gpio_common.h> -typedef struct { - u32 addr; -} gpio_t; +#define PIN(index, func1, func2, func3, func4) \ +GPIO##index##_ADDR = TLMM_TILE_BASE + (index * 0x1000), \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4 + +enum { + PIN(0, QUP0_L0, RES_2, RES_3, RES_4), + PIN(1, QUP0_L1, RES_2, RES_3, RES_4), + PIN(2, QUP0_L2, QUP0_L4, RES_3, RES_4), + PIN(3, QUP0_L3, QUP0_L5, RES_3, RES_4), + PIN(4, QUP0_L0, RES_2, RES_3, RES_4), + PIN(5, QUP0_L1, RES_2, RES_3, RES_4), + PIN(6, QUP0_L2, QUP0_L6, RES_3, RES_4), + PIN(7, USB_AUDIO_INT_N__SBU_SW_OE, QUP0_L3, RES_3, RES_4), + PIN(8, QUP0_L0, RES_2, RES_3, RES_4), + PIN(9, QUP0_L1, RES_2, RES_3, RES_4), + PIN(10, QUP0_L2, RES_2, RES_3, RES_4), + PIN(11, QUP0_L3, RES_2, RES_3, RES_4), + PIN(12, QUP0_L0, QSPI_DATA_0, RES_3, RES_4), + PIN(13, QUP0_L1, QSPI_DATA_1, RES_3, RES_4), + PIN(14, QUP0_L2, QSPI_CLK, RES_3, RES_4), + PIN(15, QUP0_L3, QSPI_CS_N_0, RES_3, RES_4), + PIN(16, QUP0_L0, QSPI_DATA_2, RES_3, RES_4), + PIN(17, QUP0_L1, QSPI_DATA_3, RES_3, RES_4), + PIN(18, QUP0_L2, RES_2, RES_3, RES_4), + PIN(19, QUP0_L3, QSPI_CS_N_1, RES_3, RES_4), + PIN(20, QUP0_L0, CCI_TIMER_0, RES_3, RES_4), + PIN(21, QUP0_L1, CCI_TIMER_1, RES_3, RES_4), + PIN(22, QUP0_L2, RES_2, RES_3, RES_4), + PIN(23, QUP0_L3, RES_2, RES_3, RES_4), + PIN(24, QUP0_L0, RES_2, RES_3, RES_4), + PIN(25, QUP0_L1, RES_2, RES_3, RES_4), + PIN(26, QUP0_L2, RES_2, RES_3, RES_4), + PIN(27, QUP0_L3, RES_2, RES_3, RES_4), + PIN(28, QUP0_L0, RES_2, RES_3, RES_4), + PIN(29, QUP0_L1, RES_2, RES_3, RES_4), + PIN(30, QUP0_L2, RES_2, RES_3, RES_4), + PIN(31, QUP0_L3, RES_2, RES_3, RES_4), + PIN(32, QUP1_L0, RES_2, RES_3, RES_4), + PIN(33, QUP1_L1, RES_2, RES_3, RES_4), + PIN(34, QUP1_L2, RES_2, RES_3, RES_4), + PIN(35, QUP1_L3, RES_2, RES_3, RES_4), + PIN(36, QUP1_L0, RES_2, RES_3, RES_4), + PIN(37, QUP1_L1, RES_2, RES_3, RES_4), + PIN(38, QUP1_L2, QUP1_L6, RES_3, RES_4), + PIN(39, QUP1_L3, RES_2, RES_3, RES_4), + PIN(40, QUP1_L0, RES_2, RES_3, RES_4), + PIN(41, QUP1_L1, RES_2, RES_3, RES_4), + PIN(42, QUP1_L2, RES_2, RES_3, RES_4), + PIN(43, QUP1_L3, RES_2, RES_3, RES_4), + PIN(44, QUP1_L0, RES_2, RES_3, RES_4), + PIN(45, QUP1_L1, RES_2, RES_3, RES_4), + PIN(46, QUP1_L2, RES_2, RES_3, RES_4), + PIN(47, QUP1_L3, DP_HOT_PLUG_DETECT, RES_3, RES_4), + PIN(48, QUP1_L0, RES_2, RES_3, RES_4), + PIN(49, QUP1_L1, RES_2, RES_3, RES_4), + PIN(50, QUP1_L2, QUP1_L6, RES_3, RES_4), + PIN(51, QUP1_L3, RES_2, RES_3, RES_4), + PIN(52, QUP1_L0, RES_2, RES_3, RES_4), + PIN(53, QUP1_L1, RES_2, RES_3, RES_4), + PIN(54, QUP1_L2, QUP1_L5, RES_3, RES_4), + PIN(55, QUP1_L3, QUP1_L4, RES_3, RES_4), + PIN(56, QUP1_L0, RES_2, RES_3, RES_4), + PIN(57, QUP1_L1, RES_2, RES_3, RES_4), + PIN(58, QUP1_L2, RES_2, RES_3, RES_4), + PIN(59, QUP1_L3, RES_2, RES_3, RES_4), + PIN(60, QUP1_L0, EDP_HOT_PLUG_DETECT, RES_3, RES_4), + PIN(61, QUP1_L1, SD_WRITE_PROTECT, RES_3, RES_4), + PIN(62, QUP1_L2, QUP1_L4, RES_3, RES_4), + PIN(63, QUP1_L3, QUP1_L5, RES_3, RES_4), + PIN(64, CAM_MCLK0, RES_2, RES_3, RES_4), + PIN(65, CAM_MCLK1, RES_2, RES_3, RES_4), + PIN(66, CAM_MCLK2, RES_2, RES_3, RES_4), + PIN(67, CAM_MCLK3, RES_2, RES_3, RES_4), + PIN(68, CAM_MCLK4, RES_2, RES_3, RES_4), + PIN(69, CCI_I2C_SDA0, RES_2, RES_3, RES_4), + PIN(70, CCI_I2C_SCL0, RES_2, RES_3, RES_4), + PIN(71, CCI_I2C_SDA1, RES_2, RES_3, RES_4), + PIN(72, CCI_I2C_SCL1, RES_2, RES_3, RES_4), + PIN(73, CCI_I2C_SDA2, RES_2, RES_3, RES_4), + PIN(74, CCI_I2C_SCL2, RES_2, RES_3, RES_4), + PIN(75, CCI_I2C_SDA3, RES_2, RES_3, RES_4), + PIN(76, CCI_I2C_SCL3, GCC_GP1_CLK_MIRB, RES_3, RES_4), + PIN(77, CCI_TIMER2, GCC_GP2_CLK_MIRB, RES_3, RES_4), + PIN(78, CCI_TIMER3, CCI_ASYNC_IN1, GCC_GP3_CLK_MIRB, RES_4), + PIN(79, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4), + PIN(80, RES_1, RES_2, RES_3, RES_4), + PIN(81, RES_1, RES_2, RES_3, RES_4), + PIN(82, RES_1, RES_2, RES_3, RES_4), + PIN(83, RES_1, RES_2, RES_3, RES_4), + PIN(84, USB2PHY_AC_EN0, RES_2, RES_3, RES_4), + PIN(85, USB2PHY_AC_EN1, RES_2, RES_3, RES_4), + PIN(86, RES_1, RES_2, RES_3, RES_4), + PIN(87, RES_1, RES_2, RES_3, RES_4), + PIN(88, RES_1, RES_2, RES_3, RES_4), + PIN(89, RES_1, RES_2, RES_3, RES_4), + PIN(90, RES_1, RES_2, RES_3, RES_4), + PIN(91, RES_1, RES_2, RES_3, RES_4), + PIN(92, RES_1, RES_2, RES_3, RES_4), + PIN(93, CAM_MCLK5, CCI_ASYNC_IN0, RES_3, RES_4), + PIN(94, LPASS_SLIMBUS_CLK, RES_2, RES_3, RES_4), + PIN(95, LPASS_SLIMBUS_DATA0, RES_2, RES_3, RES_4), + PIN(96, PRI_MI2S_MCLK, RES_2, RES_3, RES_4), + PIN(97, MI2S0_SCK, RES_2, RES_3, RES_4), + PIN(98, MI2S0_DATA0, RES_2, RES_3, RES_4), + PIN(99, MI2S0_DATA1, RES_2, RES_3, RES_4), + PIN(100, MI2S0_WS, RES_2, RES_3, RES_4), + PIN(101, MI2S2_SCK, RES_2, RES_3, RES_4), + PIN(102, MI2S2_DATA0, RES_2, RES_3, RES_4), + PIN(103, MI2S2_WS, RES_2, RES_3, RES_4), + PIN(104, MI2S2_DATA1, RES_2, RES_3, RES_4), + PIN(105, SEC_MI2S_MCLK, MI2S1_DATA1, RES_3, GCC_GP1_CLK_MIRA), + PIN(106, MI2S1_SCK, GCC_GP2_CLK_MIRA, RES_3, RES_4), + PIN(107, MI2S1_DATA0, GCC_GP3_CLK_MIRA, RES_3, RES_4), + PIN(108, MI2S1_WS, RES_2, RES_3, RES_4), + PIN(109, RES_1, RES_2, RES_3, RES_4), + PIN(110, RES_1, RES_2, RES_3, RES_4), + PIN(111, RES_1, RES_2, RES_3, RES_4), + PIN(112, RES_1, RES_2, RES_3, RES_4), + PIN(113, RES_1, RES_2, RES_3, RES_4), + PIN(114, RES_1, RES_2, RES_3, RES_4), + PIN(115, RES_1, RES_2, RES_3, RES_4), + PIN(116, RES_1, RES_2, RES_3, RES_4), + PIN(117, RES_1, RES_2, RES_3, RES_4), + PIN(118, RES_1, RES_2, RES_3, RES_4), + PIN(119, RES_1, RES_2, RES_3, RES_4), + PIN(120, RES_1, RES_2, RES_3, RES_4), + PIN(121, RES_1, RES_2, RES_3, RES_4), + PIN(122, RES_1, RES_2, RES_3, RES_4), + PIN(123, RES_1, RES_2, RES_3, RES_4), + PIN(124, RES_1, RES_2, RES_3, RES_4), + PIN(125, RES_1, RES_2, RES_3, RES_4), + PIN(126, RES_1, RES_2, RES_3, RES_4), + PIN(127, RES_1, RES_2, RES_3, RES_4), + PIN(128, RES_1, RES_2, RES_3, RES_4), + PIN(129, RES_1, RES_2, RES_3, RES_4), + PIN(130, RES_1, RES_2, RES_3, RES_4), + PIN(131, RES_1, RES_2, RES_3, RES_4), + PIN(132, RES_1, RES_2, RES_3, RES_4), + PIN(133, RES_1, RES_2, RES_3, RES_4), + PIN(134, RES_1, RES_2, RES_3, RES_4), + PIN(135, RES_1, RES_2, RES_3, RES_4), + PIN(136, RES_1, RES_2, RES_3, RES_4), + PIN(137, RES_1, RES_2, RES_3, RES_4), + PIN(138, RES_1, RES_2, RES_3, RES_4), + PIN(139, RES_1, RES_2, RES_3, RES_4), + PIN(140, USB_PHY_PS, RES_2, RES_3, RES_4), + PIN(141, RES_1, RES_2, RES_3, RES_4), + PIN(142, RES_1, RES_2, RES_3, RES_4), + PIN(143, RES_1, RES_2, RES_3, RES_4), + PIN(144, RES_1, RES_2, RES_3, RES_4), + PIN(145, RES_1, RES_2, RES_3, RES_4), + PIN(146, RES_1, RES_2, RES_3, RES_4), + PIN(147, RES_1, RES_2, RES_3, RES_4), + PIN(148, RES_1, RES_2, RES_3, RES_4), + PIN(149, RES_1, RES_2, RES_3, RES_4), + PIN(150, RES_1, RES_2, RES_3, RES_4), + PIN(151, RES_1, RES_2, RES_3, RES_4), + PIN(152, RES_1, RES_2, RES_3, RES_4), + PIN(153, RES_1, RES_2, RES_3, RES_4), + PIN(154, RES_1, RES_2, RES_3, RES_4), + PIN(155, RES_1, RES_2, RES_3, RES_4), + PIN(156, RES_1, RES_2, RES_3, RES_4), + PIN(157, RES_1, RES_2, RES_3, RES_4), + PIN(158, RES_1, RES_2, RES_3, RES_4), + PIN(159, RES_1, RES_2, RES_3, RES_4), + PIN(160, RES_1, RES_2, RES_3, RES_4), + PIN(161, RES_1, RES_2, RES_3, RES_4), + PIN(162, RES_1, RES_2, RES_3, RES_4), + PIN(163, RES_1, RES_2, RES_3, RES_4), + PIN(164, RES_1, RES_2, RES_3, RES_4), + PIN(165, RES_1, RES_2, RES_3, RES_4), + PIN(166, RES_1, RES_2, RES_3, RES_4), + PIN(167, RES_1, RES_2, RES_3, RES_4), + PIN(168, RES_1, RES_2, RES_3, RES_4), + PIN(169, RES_1, RES_2, RES_3, RES_4), + PIN(170, RES_1, RES_2, RES_3, RES_4), + PIN(171, RES_1, RES_2, RES_3, RES_4), + PIN(172, RES_1, RES_2, RES_3, RES_4), + PIN(173, RES_1, RES_2, RES_3, RES_4), + PIN(174, RES_1, RES_2, RES_3, RES_4), +}; #endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc Gerrit-Change-Number: 55077 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc: common: gpio: Add support for common GPIO driver
by Ravi kumar (Code Review) 30 May '21

30 May '21

Attention is currently required from: Taniya Das. Hello Taniya Das, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/55076 to review the following change. Change subject: soc: common: gpio: Add support for common GPIO driver ...................................................................... soc: common: gpio: Add support for common GPIO driver Add common gpio functionalities across qualcomm soc targets. This common gpio driver would allow the consumers to be able to configure gpio function, set/get gpio direction as input/output, configure the gpio as pull-up/pull-down, configure the gpio as an IRQ and also query the gpio irq status. The GPIO pin definition would be SoC specific. BUG=b:182963902 TEST=Validated on qualcomm sc7180 and sc7280 development board Signed-off-by: Taniya Das <tdas(a)codeaurora.org> Change-Id: Ia672130c6ca938d9284cae5071307637709480d1 --- A src/soc/qualcomm/common/gpio.c A src/soc/qualcomm/common/include/soc/gpio_common.h 2 files changed, 189 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/55076/1 diff --git a/src/soc/qualcomm/common/gpio.c b/src/soc/qualcomm/common/gpio.c new file mode 100644 index 0000000..1ed8e8a --- /dev/null +++ b/src/soc/qualcomm/common/gpio.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + uint32_t reg_val; + + /* gpio pull only PULLNONE, PULLUP, KEEPER, PULLDOWN status */ + assert(pull <= GPIO_PULL_UP); + + reg_val = ((enable & GPIO_BMSK) << GPIO_CFG_OE_SHFT) | + ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | + ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + + write32(&regs->cfg, reg_val); +} + +void gpio_set(gpio_t gpio, int value) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); +} + +int gpio_get(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & GPIO_BMSK); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_INPUT); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_UP, GPIO_2MA, GPIO_INPUT); +} + +void gpio_input(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_INPUT); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set(gpio, value); + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT); +} + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + gpio_configure(gpio, GPIO_FUNC_GPIO, + pull, GPIO_2MA, GPIO_INPUT); + + clrsetbits32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + GPIO_INTR_DECT_CTL_SHFT, type << GPIO_INTR_DECT_CTL_SHFT); + clrsetbits32(&regs->intr_cfg, GPIO_INTR_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHFT, GPIO_INTR_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHFT); +} + +int gpio_irq_status(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + if (!(read32(&regs->intr_status) & GPIO_INTR_STATUS_MASK)) + return GPIO_INTR_STATUS_DISABLE; + + write32(&regs->intr_status, GPIO_INTR_STATUS_DISABLE); + + return GPIO_INTR_STATUS_ENABLE; +} diff --git a/src/soc/qualcomm/common/include/soc/gpio_common.h b/src/soc/qualcomm/common/include/soc/gpio_common.h new file mode 100644 index 0000000..0ad582d --- /dev/null +++ b/src/soc/qualcomm/common/include/soc/gpio_common.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_COMMON_GPIO_H_ +#define _SOC_QUALCOMM_COMMON_GPIO_H_ + +#include <soc/gpio.h> +#include <soc/addressmap.h> + +#define GPIO_FUNC_GPIO 0 + +/* GPIO TLMM INTR: Mask */ +enum gpio_tlmm_intr_bmsk { + GPIO_INTR_STATUS_MASK = 0x1, + GPIO_INTR_DECT_CTL_MASK = 0x3, +}; + +/* GPIO TLMM: Mask */ +enum gpio_tlmm_bmsk { + GPIO_BMSK = 0x1, + GPIO_CFG_PULL_BMSK = 0x3, + GPIO_CFG_FUNC_BMSK = 0xF, + GPIO_CFG_DRV_BMSK = 0x7, +}; + +/* GPIO TLMM INTR: Shift */ +enum gpio_tlmm_intr_shft { + GPIO_INTR_DECT_CTL_SHFT = 2, + GPIO_INTR_RAW_STATUS_EN_SHFT = 4, +}; + +/* GPIO TLMM: Shift */ +enum gpio_tlmm_shft { + GPIO_CFG_PULL_SHFT = 0, + GPIO_CFG_FUNC_SHFT = 2, + GPIO_CFG_DRV_SHFT = 6, + GPIO_CFG_OE_SHFT = 9, +}; + +/* GPIO IO: Shift */ +enum gpio_io_shft { + GPIO_IO_IN_SHFT, + GPIO_IO_OUT_SHFT, +}; + +/* GPIO INTR STATUS */ +enum gpio_irq_status { + GPIO_INTR_STATUS_DISABLE, + GPIO_INTR_STATUS_ENABLE, +}; + +/* GPIO TLMM: Direction */ +enum gpio_direction { + GPIO_INPUT, + GPIO_OUTPUT, +}; + +/* GPIO TLMM: Pullup/Pulldown */ +enum gpio_pull { + GPIO_NO_PULL, + GPIO_PULL_DOWN, + GPIO_KEEPER, + GPIO_PULL_UP, +}; + +/* GPIO TLMM: Drive Strength */ +enum gpio_drv_str { + GPIO_2MA, + GPIO_4MA, + GPIO_6MA, + GPIO_8MA, + GPIO_10MA, + GPIO_12MA, + GPIO_14MA, + GPIO_16MA, +}; + +enum gpio_irq_type { + IRQ_TYPE_LEVEL, + IRQ_TYPE_RISING_EDGE, + IRQ_TYPE_FALLING_EDGE, + IRQ_TYPE_DUAL_EDGE, +}; + +typedef struct { + u32 addr; +} gpio_t; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; +}; + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); + +#endif /* _SOC_QUALCOMM_COMMON_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia672130c6ca938d9284cae5071307637709480d1 Gerrit-Change-Number: 55076 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sc7280: Add GSI FW download support
by Ravi kumar (Code Review) 30 May '21

30 May '21

Attention is currently required from: Shelley Chen, Ravi kumar. Hello build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52371 to look at the new patch set (#14). Change subject: sc7280: Add GSI FW download support ...................................................................... sc7280: Add GSI FW download support Add GSI Firmware download support for QUP wrappers. Change-Id: I8b966a6a074fc43c62d2639da9cf68b083cc7319 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/include/soc/addressmap.h M src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h M src/soc/qualcomm/sc7280/include/soc/qupv3_config.h M src/soc/qualcomm/sc7280/qupv3_config.c 5 files changed, 132 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/52371/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/52371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b966a6a074fc43c62d2639da9cf68b083cc7319 Gerrit-Change-Number: 52371 Gerrit-PatchSet: 14 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: WIP sc7280: Add USB support WIP
by Ravi kumar (Code Review) 30 May '21

30 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Sandeep Maheswaram, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51520 to look at the new patch set (#37). Change subject: WIP sc7280: Add USB support WIP ...................................................................... WIP sc7280: Add USB support WIP Change-Id: I0c10821ea2c9a5082df555caac710011ea3a0af5 Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> --- M src/mainboard/google/herobrine/mainboard.c M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/usb.h A src/soc/qualcomm/sc7280/usb.c 5 files changed, 743 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/51520/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/51520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c10821ea2c9a5082df555caac710011ea3a0af5 Gerrit-Change-Number: 51520 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: WIP sc7280: add clock driver WIP
by Ravi kumar (Code Review) 30 May '21

30 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, Taniya Das, Paul Menzel, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Taniya Das, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50580 to look at the new patch set (#39). Change subject: WIP sc7280: add clock driver WIP ...................................................................... WIP sc7280: add clock driver WIP Add support for clock driver on SC7280. BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/clock.h 4 files changed, 1,198 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/50580/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/50580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Gerrit-Change-Number: 50580 Gerrit-PatchSet: 39 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Add a common romstage entry
by Angel Pons (Code Review) 30 May '21

30 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, Arthur Heymans, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55067 ) Change subject: arch/x86: Add a common romstage entry ...................................................................... Patch Set 2: (2 comments) File src/arch/x86/romstage.c: https://review.coreboot.org/c/coreboot/+/55067/comment/fee63585_eadfa494 PS2, Line 7: static void _romstage_main(void) Does this need to be a separate function? File src/include/romstage_common.h: https://review.coreboot.org/c/coreboot/+/55067/comment/11ea18c8_a99cfaa8 PS2, Line 3: __ROMSTAGE_COMMON_H Identifiers starting with two leading underscores are reserved. I'd just name this `ROMSTAGE_COMMON_H` -- To view, visit https://review.coreboot.org/c/coreboot/+/55067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Gerrit-Change-Number: 55067 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 30 May 2021 09:58:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021