coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

1 participants
6048 discussions

Change in coreboot[master]: sc7280: Add target specific GPIO pin definitions
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Shelley Chen, Taniya Das, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55077 ) Change subject: sc7280: Add target specific GPIO pin definitions ...................................................................... Patch Set 1: (1 comment) File src/soc/qualcomm/sc7280/include/soc/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120322): https://review.coreboot.org/c/coreboot/+/55077/comment/0c302c76_1cc850f6 PS1, Line 10: #define PIN(index, func1, func2, func3, func4) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/55077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc Gerrit-Change-Number: 55077 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sun, 30 May 2021 12:28:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7180: Add display support for mipi panels
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52662 ) Change subject: sc7180: Add display support for mipi panels ...................................................................... Patch Set 12: (15 comments) File src/mainboard/google/trogdor/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/8c1e0b93_8e9e8ba7 PS12, Line 104: if(CONFIG(TROGDOR_HAS_MIPI_PANEL)) space required before the open parenthesis '(' File src/soc/qualcomm/sc7180/display/dsi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/50d42446_137c7f83 PS12, Line 65: write32(&dsi0->trig_ctrl,DSI_DMA_STREAM1 << 8 | DSI_DMA_TRIGGER_SEL); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/b27c9d69_6da459b8 PS12, Line 172: write32(&dsi0->int_ctrl,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/e9acb811_b427c83a PS12, Line 210: printk(BIOS_ERR, Invalid vsprintf pointer extension '%pk' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/10196f91_39aa1784 PS12, Line 281: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/fda0bc1f_62731cb8 PS12, Line 289: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/461ccce8_ee5b2386 PS12, Line 292: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/f170b5b1_92461b19 PS12, Line 299: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/a5387cf5_87053ecc PS12, Line 302: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/99e04c85_32a4c8da PS12, Line 319: write32(&dsi0->int_ctrl,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/b07f520f_f360c3bc PS12, Line 322: setbits32(&dsi0->int_ctrl,DSI_CMD_MODE_DMA_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/f6e842b6_bdc45702 PS12, Line 325: setbits32(&dsi0->int_ctrl,DSI_CMD_MODE_MDP_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/a0857881_9a3aea25 PS12, Line 328: setbits32(&dsi0->int_ctrl,DSI_VIDEO_MODE_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/e8177868_ef3895ee PS12, Line 333: setbits32(&dsi0->int_ctrl,DSI_ERROR_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120319): https://review.coreboot.org/c/coreboot/+/52662/comment/2059d503_7273a153 PS12, Line 343: if(!pinfo && !pinfo->init_cmd) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/52662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Gerrit-Change-Number: 52662 Gerrit-PatchSet: 12 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Sun, 30 May 2021 12:27:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode HACK
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode HACK ...................................................................... Patch Set 42: (1 comment) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120315): https://review.coreboot.org/c/coreboot/+/50586/comment/d9923c29_af891ac3 PS42, Line 499: while (1) suspect code indent for conditional statements (16, 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Sun, 30 May 2021 12:26:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7280: Add PCIe RC driver in Coreboot
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Shelley Chen, Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe RC driver in Coreboot ...................................................................... Patch Set 9: (26 comments) File src/soc/qualcomm/sc7280/include/soc/addressmap.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/117bb28c_afe1b293 PS9, Line 68: #define PCIE1_MEM_SIZE 0x1fd00000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/ec39182f_08f73f13 PS9, Line 69: #define PCIE_MEM_END 0x404fffff please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/f476b677_09716972 PS9, Line 72: #define PCIE_1_QMP_PHY 0x01C0E000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/1a702de2_b9fe4277 PS9, Line 76: #define PCE1_QPHY_SERDES 0x01C0E000 please, no space before tabs File src/soc/qualcomm/sc7280/include/soc/pcie.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/45438585_08a49a71 PS9, Line 18: #define DEV_ID_SZ 16 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/5a653136_0e81ad0f PS9, Line 19: #define CLASS_SZ 16 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/261531d2_8da6a023 PS9, Line 20: #define HEADER_SZ 8 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/5a4bdd2b_4c54d992 PS9, Line 21: #define VEND_ID_SZ 16 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/be3cb32a_63d62ecc PS9, Line 25: #define PCIE_CLASS 0x0a please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/c2069017_2ab6a025 PS9, Line 26: #define PCI_MAX_DEV_FN 0x100 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/5fea0ead_8b816d72 PS9, Line 41: #define PCIE1_3x2_NUM_LANES 2 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/18d94c7d_692c0d5f PS9, Line 57: #define PERST_DELAY_US 1000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/ec6fa1db_e1dfcb53 PS9, Line 58: #define PCIE_MAX_BARS 6 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/6b72de4a_a63266f8 PS9, Line 154: #define PCIE1_QMP_PHY_PCS_COM 0x01C0EA00 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/c722efd2_9ea60c6c PS9, Line 155: #define PCE1_QPHY_SERDES 0x01C0E000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/be8d5104_ce2dbca6 PS9, Line 156: #define PCE1_QPHY_TX0 0x01C0E200 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/26842e02_b1cf6d23 PS9, Line 157: #define PCE1_QPHY_RX0 0x01C0E400 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/c1315793_882d3631 PS9, Line 169: #define PCIE_DEV_FUNC (dev,func) PCI_SLOT(devfn) | PCI_FUNC(devfn) space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/dbfedbf6_39589aaf PS9, Line 169: #define PCIE_DEV_FUNC (dev,func) PCI_SLOT(devfn) | PCI_FUNC(devfn) Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/d8503ff2_08b54285 PS9, Line 188: #define PCIE_DEV(_bus, _dev, _fn) (0x80000000 | \ Macros with complex values should be enclosed in parentheses File src/soc/qualcomm/sc7280/pcie_host.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/159a396c_b014dea4 PS9, Line 303: pci_ep_cfg_info.config_base = (void*)PCIE1_GEN3x2_CONF; "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/f8da87a4_83fd2c65 PS9, Line 459: printk(BIOS_INFO,"pcie ep PERST asserted \n"); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/432eb8f3_f918e6be PS9, Line 459: printk(BIOS_INFO,"pcie ep PERST asserted \n"); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/5c44a62e_569d498f PS9, Line 468: printk(BIOS_NOTICE,"pcie ep PERST desserted\n"); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/0427fa55_c6a32071 PS9, Line 773: if (vend_id == 0xffff || vend_id == 0x0000) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120311): https://review.coreboot.org/c/coreboot/+/53902/comment/455fabbb_05b4bf8a PS9, Line 1140: if(!ret) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 9 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Sun, 30 May 2021 12:26:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload: Add MMIO support in PCI lib
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53903 ) Change subject: libpayload: Add MMIO support in PCI lib ...................................................................... Patch Set 9: (5 comments) File payloads/libpayload/include/arm64/arch/io.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120312): https://review.coreboot.org/c/coreboot/+/53903/comment/d3465059_a5cd86a5 PS9, Line 154: } void function return statements are not generally useful Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120312): https://review.coreboot.org/c/coreboot/+/53903/comment/6b1c9bb2_085e77e4 PS9, Line 159: } void function return statements are not generally useful File src/commonlib/include/commonlib/coreboot_tables.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120312): https://review.coreboot.org/c/coreboot/+/53903/comment/b287abf1_1fedeac0 PS9, Line 332: uint32_t tag; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120312): https://review.coreboot.org/c/coreboot/+/53903/comment/f257f4f3_606c2adf PS9, Line 333: uint32_t size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120312): https://review.coreboot.org/c/coreboot/+/53903/comment/db5c55b4_d366cbb1 PS9, Line 334: void *config_base; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/53903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cfb95e31b7ee984ee0c2e7586e6caeecd7deadd Gerrit-Change-Number: 53903 Gerrit-PatchSet: 9 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Sun, 30 May 2021 12:26:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7280: Add GSI FW download support
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Shelley Chen, Ravi kumar. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52371 ) Change subject: sc7280: Add GSI FW download support ...................................................................... Patch Set 14: (11 comments) File src/soc/qualcomm/sc7280/include/soc/qupv3_config.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/22b02d19_c26ac9b8 PS14, Line 77: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/7da794d7_7e5cc948 PS14, Line 79: uint32_t iram_dword1; /* word 1 of a single IRAM firmware entry */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/a1de59fe_c387c316 PS14, Line 83: { open brace '{' following struct go on the same line File src/soc/qualcomm/sc7280/qupv3_config.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/25bfe665_a352701c PS14, Line 204: write32(&regs->gsi_periph_base_lsb,0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/1529fb9d_89e582fc PS14, Line 205: write32(&regs->gsi_periph_base_msb,0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/54e636cd_1af21858 PS14, Line 210: if (fwIep[i].offset < GSI_REG_BASE_SIZE) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/7457e068_7b93ab88 PS14, Line 221: memcpy((&regs->gsi_inst_ramn),(void *)fwIRam, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/6c1a2dd8_c3323603 PS14, Line 223: setbits_le32(&regs->gsi_mcs_cfg, GSI_MCS_CFG_MCS_ENABLE_BMSK ); space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/139546ca_8cd03b85 PS14, Line 224: setbits_le32(&regs->gsi_cfg, GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK | GSI_CFG_GSI_ENABLE_BMSK); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/89bb08c9_96faf387 PS14, Line 226: write32(&regs->gsi_ee_n_scratch_0_addr,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120309): https://review.coreboot.org/c/coreboot/+/52371/comment/ff727a10_6e4be5da PS14, Line 227: write32(&regs->ee_n_gsi_ee_generic_cmd,0x81); space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/52371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b966a6a074fc43c62d2639da9cf68b083cc7319 Gerrit-Change-Number: 52371 Gerrit-PatchSet: 14 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Sun, 30 May 2021 12:25:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: WIP sc7280: Add USB support WIP
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Sandeep Maheswaram, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51520 ) Change subject: WIP sc7280: Add USB support WIP ...................................................................... Patch Set 37: (2 comments) File src/soc/qualcomm/sc7280/include/soc/addressmap.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120307): https://review.coreboot.org/c/coreboot/+/51520/comment/1f6b2859_38ccf917 PS37, Line 41: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120307): https://review.coreboot.org/c/coreboot/+/51520/comment/5aa08039_b7a89d65 PS37, Line 41: please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/51520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c10821ea2c9a5082df555caac710011ea3a0af5 Gerrit-Change-Number: 51520 Gerrit-PatchSet: 37 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sun, 30 May 2021 12:25:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7280: cpucp loading changes
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: cpucp loading changes ...................................................................... Patch Set 41: (42 comments) File src/soc/qualcomm/sc7280/cpucp_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/6c7b5636_1d2b897e PS41, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/2695f7bb_b16c78ee PS41, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/2b613b4d_4d12ccc4 PS41, Line 16: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/2c49e2fe_ed484e42 PS41, Line 16: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/f7eb49b6_4d7d1d60 PS41, Line 18: /* allow NS access to EPSS memory*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/15ffc25c_fc482a83 PS41, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/12cc77d7_34733784 PS41, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/691db941_f49b19f2 PS41, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/414322a3_7e2884ae PS41, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/447ce84f_674faaa8 PS41, Line 22: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/901a8c4f_29012187 PS41, Line 22: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/8b2f2a11_54596b55 PS41, Line 24: /* Enable subsystem clock. Required for CPUCP PDMEM access*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/1ec77aee_9f7b089f PS41, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/c89a1b9b_4d3b08f6 PS41, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/0c954f08_2791eeab PS41, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/493fba2d_c970fbfd PS41, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/04e04c40_47565211 PS41, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/c303f6fc_0da4116b PS41, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/f8155c2c_31fb11b8 PS41, Line 32: bool cpucp_fw_entry; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/c1e5610f_7d8c6d2a PS41, Line 32: bool cpucp_fw_entry; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/f7708135_3a48b44e PS41, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/c6c59b38_dcc6bfb6 PS41, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/7b54c5b2_037169ca PS41, Line 35: struct prog cpucp_fw_prog = code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/f3da3576_cb2bc870 PS41, Line 35: struct prog cpucp_fw_prog = please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/d1810e23_3b263073 PS41, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/3fa289ed_d93b1f06 PS41, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/d3333c82_488cf850 PS41, Line 38: cpucp_prepare(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/a5fc0a62_b81950b2 PS41, Line 38: cpucp_prepare(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/b5d6cf72_b83b7790 PS41, Line 40: if (prog_locate(&cpucp_fw_prog)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/e0d998df_145cbbc1 PS41, Line 40: if (prog_locate(&cpucp_fw_prog)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/f21eb117_5508e1a8 PS41, Line 41: die("SOC imagpe: CPUCP_FW not found"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/b547ed0a_29fdd07a PS41, Line 41: die("SOC imagpe: CPUCP_FW not found"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/48d302f3_73605614 PS41, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/634c88b3_841456dd PS41, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/f63261f4_52eaf570 PS41, Line 44: if (!cpucp_fw_entry) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/cd52a810_f77620d5 PS41, Line 44: if (!cpucp_fw_entry) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/d7f0d4cc_3267d2b1 PS41, Line 45: die("SOC image: CPUCP load failed"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/d48c0c3f_da7c7823 PS41, Line 45: die("SOC image: CPUCP load failed"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/09ad31df_9ffab0a8 PS41, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/8c0afeeb_98c50d57 PS41, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/6e789262_23fe086d PS41, Line 20: REGION_SIZE(dram_cpucp) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120301): https://review.coreboot.org/c/coreboot/+/49768/comment/fd4f8d9b_b9658888 PS41, Line 20: REGION_SIZE(dram_cpucp) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 41 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sun, 30 May 2021 12:23:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7280: aop loading changes
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

1 0

Change in coreboot[master]: sc7280: shrm.elf loading changes
by build bot (Jenkins) (Code Review) 30 May '21

30 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49392 ) Change subject: sc7280: shrm.elf loading changes ...................................................................... Patch Set 42: (1 comment) File src/soc/qualcomm/sc7280/shrm_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120299): https://review.coreboot.org/c/coreboot/+/49392/comment/294ab8e2_ada17ca6 PS42, Line 9: void shrm_fw_load_reset() Bad function definition - void shrm_fw_load_reset() should probably be void shrm_fw_load_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sun, 30 May 2021 12:22:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2021