coreboot-gerrit May 2021

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Change in coreboot[master]: lib/rtc: Add sanity check for time and date
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54913 ) Change subject: lib/rtc: Add sanity check for time and date ...................................................................... lib/rtc: Add sanity check for time and date Add a function to check sanity of a given RTC date and time. Invalid values in terms of overrun ranges of the registers can lead to strange issues in the OS. Change-Id: I0a381d445c894eee4f82b50fe86dad22cc587605 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54913 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/include/rtc.h M src/lib/rtc.c 2 files changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved diff --git a/src/include/rtc.h b/src/include/rtc.h index 0a38074..6d562f7 100644 --- a/src/include/rtc.h +++ b/src/include/rtc.h @@ -21,5 +21,6 @@ int rtc_to_tm(int tim, struct rtc_time *tm); unsigned long rtc_mktime(const struct rtc_time *tm); void rtc_display(const struct rtc_time *tm); +int rtc_invalid(const struct rtc_time *tm); #endif /* _RTC_H_ */ diff --git a/src/lib/rtc.c b/src/lib/rtc.c index c5fffa0..d151480 100644 --- a/src/lib/rtc.c +++ b/src/lib/rtc.c @@ -121,3 +121,19 @@ (tm->wday < 0 || tm->wday > 6) ? "unknown " : weekdays[tm->wday], tm->hour, tm->min, tm->sec); } + +static int rtc_month_days(unsigned int month, unsigned int year) +{ + int month_days[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; + + return month_days[month] + (LEAP_YEAR(year) && month == 2); +} + +int rtc_invalid(const struct rtc_time *tm) +{ + if (tm->sec > 59 || tm->min > 59 || tm->hour > 23 || tm->mon == 0 || tm->mon > 12 || + tm->year < 1970 || tm->mday > rtc_month_days(tm->mon - 1, tm->year)) + return 1; + else + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/54913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a381d445c894eee4f82b50fe86dad22cc587605 Gerrit-Change-Number: 54913 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55004 ) Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110 ...................................................................... mb/siemens/mc_apl{1,2,3,5,6}: Disable ACPI-support for RX6110 Already released Linux versions did not have the needed ACPI-extension in the RTC driver. If the ACPI-Support is enabled for the RTC, this older Linux will not be able to use this device as it will be claimed by the PNP-drivers. As there is no way to avoid that an older Linux kernel meets a newer coreboot in the field, we need to disable the ACPI support for the RTC for the mc_apl-based mainboards. Change-Id: I9f9939ba3234dc3654a4ef8a498649453941ebdf Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55004 Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig 5 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig index 8b10a74..ae76f7b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig index 86244a2..c1ec2eb 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig index 32db935b..d690157 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig index 71dfa0b..c82c840 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig index b34c9d8..44bff7c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig @@ -5,6 +5,7 @@ def_bool y select DRIVER_INTEL_I210 select DRIVERS_I2C_RX6110SA + select RX6110SA_DISABLE_ACPI select DRIVER_SIEMENS_NC_FPGA select NC_FPGA_NOTIFY_CB_READY select APL_SKIP_SET_POWER_LIMITS -- To view, visit https://review.coreboot.org/c/coreboot/+/55004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f9939ba3234dc3654a4ef8a498649453941ebdf Gerrit-Change-Number: 55004 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI support
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55003 ) Change subject: drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI support ...................................................................... drivers/i2c/rx6110sa: Add a Kconfig switch to disable ACPI support In commit b64db833d6 a basic ACPI support was added to the driver. With this support an SSDT-entry is created for this RTC and it is now visible to the OS via ACPI. In Linux the PNP-devices, which are reported over ACPI, are scanned rather early and if the entry is found, the device is claimed even if there is no driver available yet. In this case, when the native RTC-driver without ACPI-support is loaded and tries to register this device, the RTC is already blocked by the PNP-drivers and cannot be used anymore. This leads to a non-usable RTC on kernels where the needed ACPI-extension is not yet merged into the RTC driver. This patch provides a way to disable the ACPI-support for the RTC if needed. Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55003 Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/i2c/rx6110sa/Kconfig M src/drivers/i2c/rx6110sa/rx6110sa.c 2 files changed, 9 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, approved diff --git a/src/drivers/i2c/rx6110sa/Kconfig b/src/drivers/i2c/rx6110sa/Kconfig index a5608f8..7f3febc 100644 --- a/src/drivers/i2c/rx6110sa/Kconfig +++ b/src/drivers/i2c/rx6110sa/Kconfig @@ -3,3 +3,10 @@ default n help Enable support for external RTC chip RX6110 SA. + +config RX6110SA_DISABLE_ACPI + bool + default n + help + Disable the generation of an ACPI entry for this RTC. This is helpful + when the native driver for this RTC in OS does not have ACPI support enabled. diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index 2b8b9b2..3cab8fa 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -166,7 +166,7 @@ rx6110sa_write(dev, CTRL_REG, reg); } -#if CONFIG(HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) && !CONFIG(RX6110SA_DISABLE_ACPI) static void rx6110sa_fill_ssdt(const struct device *dev) { struct drivers_i2c_rx6110sa_config *config = dev->chip_info; @@ -227,7 +227,7 @@ .set_resources = noop_set_resources, .init = rx6110sa_init, .final = rx6110sa_final, -#if CONFIG(HAVE_ACPI_TABLES) +#if CONFIG(HAVE_ACPI_TABLES) && !CONFIG(RX6110SA_DISABLE_ACPI) .acpi_name = rx6110sa_acpi_name, .acpi_fill_ssdt = rx6110sa_fill_ssdt, #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/55003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic65794d409d13a78d17275c86ec14ee6f04cd2a6 Gerrit-Change-Number: 55003 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/smm: Fix u32 type mismatch in print statement
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54343 ) Change subject: cpu/x86/smm: Fix u32 type mismatch in print statement ...................................................................... cpu/x86/smm: Fix u32 type mismatch in print statement The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c:415:42: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'u32' {aka 'unsigned int'} [-Werror=format=] 415 | printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", | ~~^ | | | long unsigned int | %x 416 | __func__, stub_params->stack_top - total_stack_size); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | u32 {aka unsigned int} The size of `size_t` differs between i386-elf (32-bit) and x86_64-elf/x86_64-linux-gnu (64-bit). Unfortunately, coreboot hardcodes src/include/inttypes.h:#define PRIx32 "x" so `PRIx32` cannot be used. There use `z` as length modifier, as size_t should be always big enough to hold the value. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54343 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 9f0ae92..101b7c5 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -411,7 +411,7 @@ const size_t total_stack_size = params->num_concurrent_stacks * params->per_cpu_stack_size; - printk(BIOS_DEBUG, "%s: stack_end = 0x%lx\n", + printk(BIOS_DEBUG, "%s: stack_end = 0x%zx\n", __func__, stub_params->stack_top - total_stack_size); printk(BIOS_DEBUG, "%s: stack_top = 0x%x\n", __func__, stub_params->stack_top); -- To view, visit https://review.coreboot.org/c/coreboot/+/54343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib504bc5e5b19f62d4702b7f485522a2ee3d26685 Gerrit-Change-Number: 54343 Gerrit-PatchSet: 7 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/smm: Fix size_t type mismatch in print statement
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54342 ) Change subject: cpu/x86/smm: Fix size_t type mismatch in print statement ...................................................................... cpu/x86/smm: Fix size_t type mismatch in print statement The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_module_setup_stub': src/cpu/x86/smm/smm_module_loader.c:360:70: error: format '%lx' expects argument of type 'long unsigned int', but argument 5 has type 'unsigned int' [-Werror=format=] 360 | printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", | ~~^ | | | long unsigned int | %x As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `l` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. So, use the correct length modifier `z` for the type `size_t`. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Change-Id: I4172e0f4dc40437250da89b7720a5c1e5fbab709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54342 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 6d999a7..9f0ae92 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -356,7 +356,7 @@ /* The save state size encroached over the first SMM entry point. */ if (size <= SMM_ENTRY_OFFSET) { printk(BIOS_ERR, "%s: encroachment over SMM entry point\n", __func__); - printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n", + printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %zx\n", __func__, size, (size_t)SMM_ENTRY_OFFSET); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/54342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4172e0f4dc40437250da89b7720a5c1e5fbab709 Gerrit-Change-Number: 54342 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rocky Phagura Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/x86/smm: Fix uintptr_t type mismatches in print statements
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54341 ) Change subject: cpu/x86/smm: Fix uintptr_t type mismatches in print statements ...................................................................... cpu/x86/smm: Fix uintptr_t type mismatches in print statements The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format warning below: CC ramstage/cpu/x86/smm/smm_module_loader.o src/cpu/x86/smm/smm_module_loader.c: In function 'smm_create_map': src/cpu/x86/smm/smm_module_loader.c:146:19: error: format '%zx' expects argument of type 'size_t', but argument 3 has type 'uintptr_t' {aka 'long unsigned int'} [-Werror=format=] 146 | " smbase %zx entry %zx\n", | ~~^ | | | unsigned int | %lx 147 | cpus[i].smbase, cpus[i].entry); | ~~~~~~~~~~~~~~ | | | uintptr_t {aka long unsigned int} In coreboot `uintptr_t` is defined in `src/include/stdint.h`: typedef unsigned long uintptr_t; As `size_t` is defined as `long unsigned int` in i386-elf (32-bit), the length modifier `z` matches there. With x86_64-elf/x86_64-linux-gnu (64-bit) and `-m32` `size_t` is defined as `unsigned int` resulting in a type mismatch. Normally, `PRIxPTR` would need to be used as a length modifier, but as coreboot always defines `uintptr_t` to `unsigned long` (and in `src/include/inttypes.h` also defines `PRIxPTR` as `"lx"`), use the length modifier `l` to make the code more readable. Found-by: x86_64-linux-gnu-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110 Fixes: afb7a814 ("cpu/x86/smm: Introduce SMM module loader version 2") Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Change-Id: I32bff397c8a033fe34390e6c1a7dfe773707a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54341 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index e3b8417..6d999a7 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -143,10 +143,10 @@ for (i = 0; i < num_cpus; i++) { printk(BIOS_DEBUG, "CPU 0x%x\n", i); printk(BIOS_DEBUG, - " smbase %zx entry %zx\n", + " smbase %lx entry %lx\n", cpus[i].smbase, cpus[i].entry); printk(BIOS_DEBUG, - " ss_start %zx code_end %zx\n", + " ss_start %lx code_end %lx\n", cpus[i].ss_start, cpus[i].code_end); seg_count++; if (seg_count >= cpus_in_segment) { @@ -217,13 +217,13 @@ if (cpus[num_cpus].active) { if (cpus[num_cpus - 1].smbase + SMM_ENTRY_OFFSET < stack_top) { printk(BIOS_ERR, "%s: stack encroachment\n", __func__); - printk(BIOS_ERR, "%s: smbase %zx, stack_top %lx\n", + printk(BIOS_ERR, "%s: smbase %lx, stack_top %lx\n", __func__, cpus[num_cpus].smbase, stack_top); return 0; } } - printk(BIOS_INFO, "%s: smbase %zx, stack_top %lx\n", + printk(BIOS_INFO, "%s: smbase %lx, stack_top %lx\n", __func__, cpus[num_cpus-1].smbase, stack_top); /* start at 1, the first CPU stub code is already there */ @@ -231,9 +231,9 @@ for (i = 1; i < num_cpus; i++) { memcpy((int *)cpus[i].code_start, (int *)cpus[0].code_start, size); printk(BIOS_DEBUG, - "SMM Module: placing smm entry code at %zx, cpu # 0x%x\n", + "SMM Module: placing smm entry code at %lx, cpu # 0x%x\n", cpus[i].code_start, i); - printk(BIOS_DEBUG, "%s: copying from %zx to %zx 0x%x bytes\n", + printk(BIOS_DEBUG, "%s: copying from %lx to %lx 0x%x bytes\n", __func__, cpus[0].code_start, cpus[i].code_start, size); } return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/54341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32bff397c8a033fe34390e6c1a7dfe773707a4e8 Gerrit-Change-Number: 54341 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rocky Phagura <rphagura(a)fb.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp_m: add ec device entry to devicetree
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54490 ) Change subject: mb/intel/adlrvp_m: add ec device entry to devicetree ...................................................................... mb/intel/adlrvp_m: add ec device entry to devicetree TEST=Boot to OS and verify acpi tables. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: John Zhao <john.zhao(a)intel.corp-partner.google.com> Reviewed-by: John Zhao <john.zhao(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified John Zhao: Looks good to me, approved John Zhao: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb index 80450e7..68a1bfa 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb @@ -1,5 +1,12 @@ chip soc/intel/alderlake device domain 0 on + device pci 1f.0 on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end # eSPI device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the -- To view, visit https://review.coreboot.org/c/coreboot/+/54490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90 Gerrit-Change-Number: 54490 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add placeholder SPD file
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55021 ) Change subject: soc/intel/alderlake: Add placeholder SPD file ...................................................................... soc/intel/alderlake: Add placeholder SPD file Change-Id: I38eb4bb684c511fff5ae148091c066682e9c35cb Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55021 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/soc/intel/alderlake/spd/placeholder.spd.hex 1 file changed, 32 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/alderlake/spd/placeholder.spd.hex b/src/soc/intel/alderlake/spd/placeholder.spd.hex new file mode 100644 index 0000000..1a5be53 --- /dev/null +++ b/src/soc/intel/alderlake/spd/placeholder.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/55021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38eb4bb684c511fff5ae148091c066682e9c35cb Gerrit-Change-Number: 55021 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Update vboot submodule to upstream main
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55026 ) Change subject: Update vboot submodule to upstream main ...................................................................... Update vboot submodule to upstream main Updating from commit id e681c37: change node locked version expectations to commit id b38e3a63: cros_ec: Use boot mode to check if EC can be trusted Change-Id: Id6de185af85a61a3843b302fef6fa0d4d3c17aef Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55026 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/3rdparty/vboot b/3rdparty/vboot index e681c37..b38e3a6 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e681c371484b50c0cc35d91123b176acdc2449eb +Subproject commit b38e3a63a8b1d42fd707e4c23e71c3f3ed84e6ad -- To view, visit https://review.coreboot.org/c/coreboot/+/55026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6de185af85a61a3843b302fef6fa0d4d3c17aef Gerrit-Change-Number: 55026 Gerrit-PatchSet: 3 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/mc_apl1: Move gpio.c from baseboard to mc_apl1
by Patrick Georgi (Code Review) 30 May '21

30 May '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/54945 ) Change subject: mb/siemens/mc_apl1: Move gpio.c from baseboard to mc_apl1 ...................................................................... mb/siemens/mc_apl1: Move gpio.c from baseboard to mc_apl1 Variant mc_apl1 is the only one that uses gpio.c from baseboard. For this reason, gpio.c is moved from baseboard to mc_apl1. Change-Id: Ie2ba8181dfe887df9abbbd648f2cbdc6ffc65530 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54945 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc M src/mainboard/siemens/mc_apl1/variants/mc_apl1/Makefile.inc R src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Werner Zeh: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc index 1d38b77..e553581 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/Makefile.inc @@ -1,5 +1,2 @@ -bootblock-y += gpio.c romstage-y += memory.c - -ramstage-y += gpio.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Makefile.inc index 81633a1..3629aca 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/Makefile.inc @@ -1,2 +1,5 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c ramstage-y += mainboard.c ramstage-y += lcd_panel.c diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c similarity index 100% rename from src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c rename to src/mainboard/siemens/mc_apl1/variants/mc_apl1/gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/54945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2ba8181dfe887df9abbbd648f2cbdc6ffc65530 Gerrit-Change-Number: 54945 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2021