coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchp...
by zanxi chen (Code Review) 31 May '21

31 May '21

Attention is currently required from: Furquan Shaikh, Henry Sun, Paul Menzel, Tao Xia, Karthik Ramasubramanian, Karthikeyan Ramasubramanian. zanxi chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54249 ) Change subject: mb/google/dedede/var/blipper: Configure I2C times for touchpad/touchpanel/codec ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Hi,Karthik&Pual: Please help merge this CL. If need add something, please give some details,thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/54249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8438e37be49f8a74f53fd8460110dac1a3f06993 Gerrit-Change-Number: 54249 Gerrit-PatchSet: 3 Gerrit-Owner: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-CC: zanxi chen <chenzanxi(a)huaqin.corp-partner.google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tao Xia <xiatao5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Mon, 31 May 2021 07:04:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Create primus variant
by Scott Chao (Code Review) 31 May '21

31 May '21

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55092 ) Change subject: mb/google/brya: Create primus variant ...................................................................... mb/google/brya: Create primus variant Create the primus variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-generated by create_coreboot_variant.sh version 4.5.0) BUG=b:188272162 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PRIMUS Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I539d3066ca8db54b2b2be5175adeffaf1c2a8570 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/primus/include/variant/ec.h A src/mainboard/google/brya/variants/primus/include/variant/gpio.h A src/mainboard/google/brya/variants/primus/memory/Makefile.inc A src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/primus/overridetree.cb 8 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/55092/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index c28c293..3acb07e 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -72,10 +72,12 @@ config MAINBOARD_PART_NUMBER string default "Brya" if BOARD_GOOGLE_BRYA0 + default "Primus" if BOARD_GOOGLE_PRIMUS config VARIANT_DIR string default "brya0" if BOARD_GOOGLE_BRYA0 + default "primus" if BOARD_GOOGLE_PRIMUS config DIMM_SPD_SIZE int diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 70af2d2..4bf5ca4 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -5,3 +5,8 @@ select BOARD_ROMSIZE_KB_32768 select ADL_ENABLE_USB4_PCIE_RESOURCES select DRIVERS_GENESYSLOGIC_GL9755 + +config BOARD_GOOGLE_PRIMUS + bool "-> Primus" + select BOARD_GOOGLE_BASEBOARD_BRYA + select BASEBOARD_BRYA_LAPTOP diff --git a/src/mainboard/google/brya/variants/primus/include/variant/ec.h b/src/mainboard/google/brya/variants/primus/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/primus/include/variant/gpio.h b/src/mainboard/google/brya/variants/primus/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/primus/memory/Makefile.inc b/src/mainboard/google/brya/variants/primus/memory/Makefile.inc new file mode 100644 index 0000000..b0ca222 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt new file mode 100644 index 0000000..9cff262 --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x. +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/55092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I539d3066ca8db54b2b2be5175adeffaf1c2a8570 Gerrit-Change-Number: 55092 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Add board id for MR DDR5 SKU
by Deepti Deshatty (Code Review) 31 May '21

31 May '21

Attention is currently required from: Balaji Manigandan, Deepti Deshatty. Hello build bot (Jenkins), Subrata Banik, Balaji Manigandan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52760 to look at the new patch set (#5). Change subject: mb/intel/adlrvp: Add board id for MR DDR5 SKU ...................................................................... mb/intel/adlrvp: Add board id for MR DDR5 SKU Add support for Maple Ridge DDR5 SKU with boardid 0x16 TEST=Verified build for ADL-P Chrome RVP Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db --- M src/mainboard/intel/adlrvp/include/baseboard/variants.h M src/mainboard/intel/adlrvp/mainboard.c M src/mainboard/intel/adlrvp/memory.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c 4 files changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52760/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db Gerrit-Change-Number: 52760 Gerrit-PatchSet: 5 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/intel/adlrvp: Update Mainboard part number and Vendor
by Maulik V Vaghela (Code Review) 31 May '21

31 May '21

Attention is currently required from: Anil Kumar K, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51408 ) Change subject: mb/intel/adlrvp: Update Mainboard part number and Vendor ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/51408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Gerrit-Change-Number: 51408 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Mon, 31 May 2021 05:55:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Update Mainboard part number and Vendor
by Maulik V Vaghela (Code Review) 31 May '21

31 May '21

Attention is currently required from: Anil Kumar K, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath. Maulik V Vaghela has uploaded a new patch set (#8) to the change originally created by Meera Ravindranath. ( https://review.coreboot.org/c/coreboot/+/51408 ) Change subject: mb/intel/adlrvp: Update Mainboard part number and Vendor ...................................................................... mb/intel/adlrvp: Update Mainboard part number and Vendor dmidecode output should match with the Kernel updated string. This is required to probe the audio driver in kernel as it matches VENDOR and PRODUCT name. Reference: https://lore.kernel.org/alsa-devel/20210415175013.192862-6-pierre-louis.bos… TEST=dmidecode grep "Manufacturer" = Intel Corporation dmidecode grep "Product name" = Alder Lake Client Platform Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc --- M src/mainboard/intel/adlrvp/Kconfig 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/51408/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/51408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Gerrit-Change-Number: 51408 Gerrit-PatchSet: 8 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: configs: Update configs for OCP Delta Lake LinuxBoot payload
by Johnny Lin (Code Review) 31 May '21

31 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Paul Menzel, insomniac. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55058 ) Change subject: configs: Update configs for OCP Delta Lake LinuxBoot payload ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55058/comment/a9c97e5f_b4212cc9 PS1, Line 12: Linux OS > Nit: GNU/Linux […] Done File configs/builder/config.ocp.deltalake: https://review.coreboot.org/c/coreboot/+/55058/comment/b0af8d57_24a1942e PS1, Line 10: CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y > Please also mention this in the commit message. Done https://review.coreboot.org/c/coreboot/+/55058/comment/8420acdb_366ebe78 PS1, Line 23: CONFIG_CONSOLE_SERIAL_57600=y > Please mention in the commit message, why that speed is selected. Done https://review.coreboot.org/c/coreboot/+/55058/comment/5b078a95_9a2dd8d1 PS1, Line 24: CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4=y > Please mention in the commit message, why the reduced log level is useful. Done https://review.coreboot.org/c/coreboot/+/55058/comment/077c9e53_237f9f3e PS1, Line 26: CONFIG_PAYLOAD_FILE="site-local/deltalake/linuxboot_uroot_ttys0" > Is that file present on the builder? No the LinuxBoot payload binary is not uploaded. -- To view, visit https://review.coreboot.org/c/coreboot/+/55058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Gerrit-Change-Number: 55058 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: insomniac <insomniac(a)slackware.it> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: insomniac <insomniac(a)slackware.it> Gerrit-Comment-Date: Mon, 31 May 2021 05:49:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: configs: Update configs for OCP Delta Lake LinuxBoot payload
by Arthur Heymans (Code Review) 31 May '21

31 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Johnny Lin, insomniac. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55058 ) Change subject: configs: Update configs for OCP Delta Lake LinuxBoot payload ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Gerrit-Change-Number: 55058 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: insomniac <insomniac(a)slackware.it> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: insomniac <insomniac(a)slackware.it> Gerrit-Comment-Date: Mon, 31 May 2021 05:47:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: configs: Update configs for OCP Delta Lake LinuxBoot payload
by Johnny Lin (Code Review) 31 May '21

31 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Johnny Lin, insomniac. Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, insomniac, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55058 to look at the new patch set (#2). Change subject: configs: Update configs for OCP Delta Lake LinuxBoot payload ...................................................................... configs: Update configs for OCP Delta Lake LinuxBoot payload OCP Delta Lake is developed and validated against LinuxBoot payload. Need to put the respective binary blobs in site-local/deltalake to build the final coreboot image. Add LINUX_COMMAND_LINE for LinuxBoot payload kernel cmdline, CPU_UCODE_BINARIES for CPU microcode binary, CONSOLE_SERIAL_57600 is the serial baud rate used by OCP Delta Lake, DEFAULT_CONSOLE_LOGLEVEL_4 is for a faster boot time. Tested=On OCP Delta Lake it can boot up target CentOS 8 GNU/Linux OS. Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M configs/builder/config.ocp.deltalake 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/55058/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494e4170a7ebb445d9e11df83c370b40a9e5194 Gerrit-Change-Number: 55058 Gerrit-PatchSet: 2 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: insomniac <insomniac(a)slackware.it> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: insomniac <insomniac(a)slackware.it> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/cret: Add ssfc codec cs42l42 support
by Dtrain Hsu (Code Review) 31 May '21

31 May '21

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55091 ) Change subject: mb/google/dedede/var/cret: Add ssfc codec cs42l42 support ...................................................................... mb/google/dedede/var/cret: Add ssfc codec cs42l42 support Add cs42l42 codec support in cret. BUG=b:189524295 TEST=Build and boot to check functional with cs42l42 EV board. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 --- M src/mainboard/google/dedede/Kconfig M src/mainboard/google/dedede/variants/cret/gpio.c M src/mainboard/google/dedede/variants/cret/overridetree.cb 3 files changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/55091/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index e237b80..3f6a4ab 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -2,6 +2,7 @@ def_bool n select BOARD_ROMSIZE_KB_16384 if !BOARD_ROMSIZE_KB_32768 select DRIVERS_GENERIC_GPIO_KEYS + select DRIVERS_I2C_CS42L42 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_GPIO_MUX select DRIVERS_I2C_HID diff --git a/src/mainboard/google/dedede/variants/cret/gpio.c b/src/mainboard/google/dedede/variants/cret/gpio.c index 5acef69..abe0c20 100644 --- a/src/mainboard/google/dedede/variants/cret/gpio.c +++ b/src/mainboard/google/dedede/variants/cret/gpio.c @@ -41,6 +41,8 @@ PAD_NC(GPP_H6, NONE), /* H7 : AP_I2C_CAM_SCL ==> NC */ PAD_NC(GPP_H7, NONE), + /* H16 : AP_SUB_IO_L ==> HP_RST_ODL */ + PAD_CFG_GPO(GPP_H16, 1, PWROK), /* H17 : WWAN_RST_L */ PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* G0 : SD_CMD ==> NC */ diff --git a/src/mainboard/google/dedede/variants/cret/overridetree.cb b/src/mainboard/google/dedede/variants/cret/overridetree.cb index 2586322..772bd96 100644 --- a/src/mainboard/google/dedede/variants/cret/overridetree.cb +++ b/src/mainboard/google/dedede/variants/cret/overridetree.cb @@ -1,3 +1,12 @@ +fw_config + field AUDIO_CODEC_SOURCE 41 44 + option AUDIO_CODEC_UNPROVISIONED 0 + option AUDIO_CODEC_DA7219 1 + option AUDIO_CODEC_RT5682 2 + option AUDIO_CODEC_CS42l42 3 + end +end + chip soc/intel/jasperlake # USB Port Configuration @@ -166,7 +175,29 @@ register "adc_1bit_rpt" = "1" register "micbias_lvl" = "2600" register "mic_amp_in_sel" = ""diff"" - device i2c 1a on end + device i2c 1a on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_DA7219 + end + end + chip drivers/i2c/cs42l42 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H16)" + register "ts_inv" = "true" + register "ts_dbnc_rise" = "RISE_DEB_1000_MS" + register "ts_dbnc_fall" = "FALL_DEB_0_MS" + register "btn_det_init_dbnce" = "100" + register "btn_det_event_dbnce" = "10" + register "bias_lvls[0]" = "15" + register "bias_lvls[1]" = "8" + register "bias_lvls[2]" = "4" + register "bias_lvls[3]" = "1" + register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW" + register "hs_bias_sense_disable" = "true" + device i2c 48 on + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED + probe AUDIO_CODEC_SOURCE AUDIO_CODEC_CS42l42 + end end end #I2C 4 device pci 1f.3 on -- To view, visit https://review.coreboot.org/c/coreboot/+/55091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 Gerrit-Change-Number: 55091 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Werner Zeh (Code Review) 31 May '21

31 May '21

Werner Zeh has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... drivers/i2c/designware: Report I2C timings for additional bus speeds Since the OS provides its own driver for the I2C controller it can chose to use a bus speed other than the one used at coreboot runtime. In this case it would be good to provide a way how the needed bus timings are communicated to the OS, since these are very board-specific and there is no way that the OS can know them other than read the appropriate ACPI reported timings. This patch adds some code to report additional bus speed timings if there are some defined in the devicetree. Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/designware/dw_i2c.c 1 file changed, 9 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/55088/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2021