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Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55050 )
Change subject: soc/mediatek: Move the SSPM driver to common
......................................................................
Patch Set 2: Code-Review+2
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Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35645 )
Change subject: vboot: Fix wrong algorithm in TCPA log for BOOT_MODE
......................................................................
vboot: Fix wrong algorithm in TCPA log for BOOT_MODE
The hash algorithm for VBOOTs BOOT_MODE is fixed to sha1 but TCPA log
uses sha256 as the name for the algorithm. This leads to an log entry
with 20 bytes (sha1) while the algorithm is set to sha256 (which needs
32 bytes of hash). Fix it by using the matching algorithm name for
BOOT_MODE.
Change-Id: Ia25938ac5f6c29f60a4819023b99f7796849f574
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/security/vboot/tpm_common.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/35645/1
diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c
index 0a211c5..1db7189 100644
--- a/src/security/vboot/tpm_common.c
+++ b/src/security/vboot/tpm_common.c
@@ -46,7 +46,7 @@
switch (which_digest) {
/* SHA1 of (devmode|recmode|keyblock) bits */
case BOOT_MODE_PCR:
- return tpm_extend_pcr(pcr, VB2_HASH_SHA256, buffer, size,
+ return tpm_extend_pcr(pcr, VB2_HASH_SHA1, buffer, size,
TPM_PCR_BOOT_MODE);
/* SHA256 of HWID */
case HWID_DIGEST_PCR:
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/mediatek: Initialize SSPM
......................................................................
soc/mediatek: Initialize SSPM
Load SSPM firmware and boot up SSPM in ramstage.
TEST=none
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: Ia227ea9f7d58129068cb36ec2de7d9feb677006b
---
M src/soc/mediatek/mt8195/Kconfig
M src/soc/mediatek/mt8195/Makefile.inc
M src/soc/mediatek/mt8195/soc.c
3 files changed, 11 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/55051/3
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Rex-BC Chen has uploaded a new patch set (#96) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/52260 )
Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT
......................................................................
DO-NOT-SUBMIT: MT8195 Cherry review ToT
Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com>
Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0
---
M 3rdparty/amd_blobs
M 3rdparty/blobs
M 3rdparty/intel-microcode
M README.md
4 files changed, 4 insertions(+), 3 deletions(-)
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to look at the new patch set (#2).
Change subject: soc/mediatek: Move the SSPM driver to common
......................................................................
soc/mediatek: Move the SSPM driver to common
The SSPM driver can be shared by MT8183, MT8192 and MT8195.
TEST=emerge-{asurada, kukui} coreboot;
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: If9779853becb298eeeabb3dc6096bc474baae202
---
A src/soc/mediatek/common/include/soc/sspm.h
R src/soc/mediatek/common/sspm.c
M src/soc/mediatek/mt8183/Makefile.inc
D src/soc/mediatek/mt8183/include/soc/sspm.h
M src/soc/mediatek/mt8192/Makefile.inc
D src/soc/mediatek/mt8192/include/soc/sspm.h
D src/soc/mediatek/mt8192/sspm.c
7 files changed, 17 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/55050/2
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Tao Xia has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55035 )
Change subject: mb/google/dedede/var/sasukette: Modify the touch pad slave address
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55035/comment/e4d0ed57_1db7d852
PS1, Line 10: It will cause one of the touch pad hid identification error.
> Please paste that error, and summarize the bug report.
Done
https://review.coreboot.org/c/coreboot/+/55035/comment/91497154_6ed2901e
PS1, Line 14: TEST=Verify OK
> Please be more specific.
Done
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Attention is currently required from: Ravi kumar.
Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50587 )
Change subject: sc7280: Reserve wlan & wpss dram memory regions
......................................................................
Patch Set 38:
(1 comment)
File src/soc/qualcomm/sc7280/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/50587/comment/038352c6_e9677917
PS38, Line 56: REGION(dram_wpss, 0x9AE00000, 0x1900000, 0x1000)
> Can you explain what this is? In particular, if it's related to the modem again, are there parts tha […]
Hi Julius,
these are wifi co-processor regions.
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