coreboot-gerrit May 2021

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Change in coreboot[master]: mb/google/volteer/var/volet: add volet memory configuration.
by Sheng-Liang Pan (Code Review) 31 May '21

31 May '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Nick Vaccaro, Paul Fagerburg. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Nick Vaccaro, Paul Fagerburg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55096 to look at the new patch set (#3). Change subject: mb/google/volteer/var/volet: add volet memory configuration. ...................................................................... mb/google/volteer/var/volet: add volet memory configuration. volet use same memory configuration from Voxel, copy voxel setting to volet. BUG=b:186334008 TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 --- A src/mainboard/google/volteer/variants/volet/Makefile.inc A src/mainboard/google/volteer/variants/volet/memory.c M src/mainboard/google/volteer/variants/volet/memory/Makefile.inc M src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt 5 files changed, 81 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/55096/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/55096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 Gerrit-Change-Number: 55096 Gerrit-PatchSet: 3 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/var/volet: add volet memory configuration.
by Sheng-Liang Pan (Code Review) 31 May '21

31 May '21

Attention is currently required from: YH Lin, Tim Wawrzynczak, Nick Vaccaro, Paul Fagerburg, Sheng-Liang Pan. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Nick Vaccaro, Paul Fagerburg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55096 to look at the new patch set (#2). Change subject: mb/google/volteer/var/volet: add volet memory configuration. ...................................................................... mb/google/volteer/var/volet: add volet memory configuration. volet use same memory configuration from Voxel, copy voxel setting to volet. BUG=b:186334008 TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 --- A src/mainboard/google/volteer/variants/volet/Makefile.inc A src/mainboard/google/volteer/variants/volet/memory.c M src/mainboard/google/volteer/variants/volet/memory/Makefile.inc M src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt 5 files changed, 86 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/55096/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 Gerrit-Change-Number: 55096 Gerrit-PatchSet: 2 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer/var/volet: add volet memory configuration.
by Sheng-Liang Pan (Code Review) 31 May '21

31 May '21

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55096 ) Change subject: mb/google/volteer/var/volet: add volet memory configuration. ...................................................................... mb/google/volteer/var/volet: add volet memory configuration. volet use same memory configuration from Voxel, copy voxel setting to volet. BUG=b:186334008 TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 --- A src/mainboard/google/volteer/variants/volet/Makefile.inc A src/mainboard/google/volteer/variants/volet/memory.c M src/mainboard/google/volteer/variants/volet/memory/Makefile.inc M src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt 5 files changed, 86 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/55096/1 diff --git a/src/mainboard/google/volteer/variants/volet/Makefile.inc b/src/mainboard/google/volteer/variants/volet/Makefile.inc new file mode 100644 index 0000000..3488dc6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/Makefile.inc @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += memory.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/volteer/variants/volet/memory.c b/src/mainboard/google/volteer/variants/volet/memory.c new file mode 100644 index 0000000..fe2b2b1 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volet/memory.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct mb_cfg board_memcfg = { + .type = MEM_TYPE_LP4X, + + /* DQ byte map */ + .lp4x_dq_map = { + .ddr0 = { + .dq0 = { 3, 0, 1, 2, 6, 7, 5, 4, }, /* DDR0_DQ0[7:0] */ + .dq1 = { 12, 15, 14, 13, 8, 9, 10, 11 }, /* DDR0_DQ1[7:0] */ + }, + .ddr1 = { + .dq0 = { 12, 15, 13, 14, 10, 8, 11, 9, }, /* DDR1_DQ0[7:0] */ + .dq1 = { 5, 6, 7, 4, 0, 3, 1, 2 }, /* DDR1_DQ1[7:0] */ + }, + .ddr2 = { + .dq0 = { 2, 3, 0, 1, 7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */ + .dq1 = { 12, 14, 15, 13, 10, 9, 8, 11 }, /* DDR2_DQ1[7:0] */ + }, + .ddr3 = { + .dq0 = { 15, 12, 13, 14, 8, 9, 10, 11, }, /* DDR3_DQ0[7:0] */ + .dq1 = { 7, 6, 4, 5, 2, 0, 3, 1 }, /* DDR3_DQ1[7:0] */ + }, + .ddr4 = { + .dq0 = { 6, 5, 4, 7, 0, 3, 2, 1, }, /* DDR4_DQ0[7:0] */ + .dq1 = { 15, 14, 13, 12, 11, 8, 9, 10 }, /* DDR4_DQ1[7:0] */ + }, + .ddr5 = { + .dq0 = { 11, 9, 10, 8, 12, 14, 13, 15, }, /* DDR5_DQ0[7:0] */ + .dq1 = { 1, 0, 2, 3, 6, 7, 5, 4 }, /* DDR5_DQ1[7:0] */ + }, + .ddr6 = { + .dq0 = { 2, 3, 0, 1, 5, 4, 6, 7, }, /* DDR6_DQ0[7:0] */ + .dq1 = { 13, 14, 15, 12, 11, 10, 8, 9 }, /* DDR6_DQ1[7:0] */ + }, + .ddr7 = { + .dq0 = { 14, 13, 15, 12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */ + .dq1 = { 4, 5, 1, 2, 6, 0, 3, 7 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .lp4x_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR0_DQS[1:0] */ + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR1_DQS[1:0] */ + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR2_DQS[1:0] */ + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR3_DQS[1:0] */ + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR4_DQS[1:0] */ + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR5_DQS[1:0] */ + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, /* DDR6_DQS[1:0] */ + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = true, /* Enable Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} diff --git a/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc index b0ca222..f40fba6 100644 --- a/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt index fa24790..8d472df 100644 --- a/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt @@ -1 +1,7 @@ DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +H9HCNNNCPMMLXR-NEE 2 (0010) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt index e4258b5..5ddd52e 100644 --- a/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt @@ -1,11 +1,6 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/{ddr4,lp4x}. -# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. - -# Part Name +MT53E512M32D2NP-046 WT:E +H9HCNNNBKMMLXR-NEE +K4U6E3S4AA-MGCR +MT53E1G32D2NP-046 WT:A +H9HCNNNCPMMLXR-NEE +K4UBE3D4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/55096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61 Gerrit-Change-Number: 55096 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/Linuxboot/u-root: Explicitly set GO111MODULE=off
by Arthur Heymans (Code Review) 31 May '21

31 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55095 ) Change subject: payloads/Linuxboot/u-root: Explicitly set GO111MODULE=off ...................................................................... payloads/Linuxboot/u-root: Explicitly set GO111MODULE=off With go1.16 the default for GO111MODULe was changed from 'off' to 'on' which breaks building u-root. Change-Id: Ie90b400418ccd06426a0e00ec7f7932066f57d7e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M payloads/external/LinuxBoot/targets/u-root.mk 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/55095/1 diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk index 0cf91fe..026ff5d 100644 --- a/payloads/external/LinuxBoot/targets/u-root.mk +++ b/payloads/external/LinuxBoot/targets/u-root.mk @@ -40,10 +40,10 @@ get: version if [ -d "$(go_path_dir)/src/$(uroot_package)" ]; then \ git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet master; \ - GOPATH=$(go_path_dir) go get -d -u -v $(uroot_package) || \ + GOPATH=$(go_path_dir) GO111MODULE=off go get -d -u -v $(uroot_package) || \ echo -e "\n<<u-root package update failed>>\n"; \ else \ - GOPATH=$(go_path_dir) go get -d -u -v $(uroot_package) || \ + GOPATH=$(go_path_dir) GO111MODULE=off go get -d -u -v $(uroot_package) || \ (echo -e "\n<<failed to get u-root package. Please check your internet access>>\n" && \ exit 1); \ fi @@ -52,10 +52,10 @@ git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet $(CONFIG_LINUXBOOT_UROOT_VERSION) build: checkout - GOPATH=$(go_path_dir) go build -o $(uroot_bin) $(uroot_package) + GOPATH=$(go_path_dir) GO111MODULE=off go build -o $(uroot_bin) $(uroot_package) u-root: build - GOARCH=$(ARCH-y) GOPATH=$(go_path_dir) $(uroot_bin) \ + GOARCH=$(ARCH-y) GOPATH=$(go_path_dir) GO111MODULE=off $(uroot_bin) \ $(uroot_args) -o $(project_dir)/initramfs_u-root.cpio $(uroot_cmds) .PHONY: all u-root build checkout get version -- To view, visit https://review.coreboot.org/c/coreboot/+/55095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie90b400418ccd06426a0e00ec7f7932066f57d7e Gerrit-Change-Number: 55095 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [NOTFORMERGE]link Agesa into bootblock
by build bot (Jenkins) (Code Review) 31 May '21

31 May '21

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55070 ) Change subject: [NOTFORMERGE]link Agesa into bootblock ...................................................................... Patch Set 3: (1 comment) File src/drivers/amd/agesa/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120364): https://review.coreboot.org/c/coreboot/+/55070/comment/2af57b06_d52e14a9 PS3, Line 47: void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); function definition argument 'void' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/55070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4c71b9c9a245e07d713839fb3628cbfc0dc3457 Gerrit-Change-Number: 55070 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 31 May 2021 11:21:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: use initial_lapicid() instead of opencoding it
by Arthur Heymans (Code Review) 31 May '21

31 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Anjaneya "Reddy" Chagam, Marshall Dawson, Jonathan Zhang, Johnny Lin, Paul Menzel, Arthur Heymans, Morgan Jang, Patrick Rudolph, Felix Held. Arthur Heymans has uploaded a new patch set (#2) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/55063 ) Change subject: use initial_lapicid() instead of opencoding it ...................................................................... use initial_lapicid() instead of opencoding it Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/romstage.c M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c M src/soc/intel/xeon_sp/smmrelocate.c 5 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/55063/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Gerrit-Change-Number: 55063 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2197_00
by Ronak Kanabar (Code Review) 31 May '21

31 May '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Sridhar Siricilla, Balaji Manigandan, Tim Wawrzynczak, Srinidhi N Kaushik, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Sridhar Siricilla, Balaji Manigandan, Tim Wawrzynczak, Srinidhi N Kaushik, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/55094 to look at the new patch set (#2). Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2197_00 ...................................................................... vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2197_00 The headers added are generated as per FSP v2197_00. Previous FSP version was v2162_00. Changes Include: - Add IbeccProtectedRangeEnable, IbeccProtectedRangeBase and IbeccProtectedRangeMask in FspmUpd.h - Adjust Reserved UPD Offset in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BUG=b:189731004 BRANCH=None TEST=Build and boot brya Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd Cq-Depend: TBD Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 72 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/55094/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd Gerrit-Change-Number: 55094 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp1_1/romstage.c: Remove MCU update
by Frans Hendriks (Code Review) 31 May '21

31 May '21

Attention is currently required from: Lee Leahy, Paul Menzel, Huang Jin, Arthur Heymans, Patrick Rudolph, Wim Vervoorn. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55064 ) Change subject: drivers/intel/fsp1_1/romstage.c: Remove MCU update ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Build and booted without problems on facebook FBG1701 -- To view, visit https://review.coreboot.org/c/coreboot/+/55064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Gerrit-Change-Number: 55064 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Mon, 31 May 2021 10:09:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2197_00
by Ronak Kanabar (Code Review) 31 May '21

31 May '21

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55094 ) Change subject: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2197_00 ...................................................................... vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2197_00 The headers added are generated as per FSP v2197_00. Previous FSP version was v2162_00. Changes Include: - Add IbeccProtectedRangeEnable, IbeccProtectedRangeBase and IbeccProtectedRangeMask in FspmUpd.h - Adjust Reserved UPD Offset in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h BRANCH=None TEST=Build and boot brya Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd Cq-Depend: TBD Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h 2 files changed, 72 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/55094/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 2c04f90..8b6ad1b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -240,9 +240,21 @@ **/ UINT8 IbeccOperationMode; -/** Offset 0x012C - Reserved +/** Offset 0x012C - IbeccProtectedRangeEnable + In-Band ECC Protected Region Enable + $EN_DIS **/ - UINT8 Reserved0[72]; + UINT8 IbeccProtectedRangeEnable[8]; + +/** Offset 0x0134 - IbeccProtectedRangeBase + IBECC Protected Region Base +**/ + UINT32 IbeccProtectedRangeBase[8]; + +/** Offset 0x0154 - IbeccProtectedRangeMask + IBECC Protected Region Mask +**/ + UINT32 IbeccProtectedRangeMask[8]; /** Offset 0x0174 - MRC Fast Boot Enables/Disable the MRC fast path thru the MRC @@ -266,7 +278,7 @@ /** Offset 0x0177 - Reserved **/ - UINT8 Reserved1; + UINT8 Reserved0; /** Offset 0x0178 - Tseg Size Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build @@ -365,7 +377,7 @@ /** Offset 0x019A - Reserved **/ - UINT8 Reserved2[5]; + UINT8 Reserved1[5]; /** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set @@ -381,7 +393,7 @@ /** Offset 0x01A1 - Reserved **/ - UINT8 Reserved3[3]; + UINT8 Reserved2[3]; /** Offset 0x01A4 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine @@ -450,7 +462,7 @@ /** Offset 0x01D1 - Reserved **/ - UINT8 Reserved4; + UINT8 Reserved3; /** Offset 0x01D2 - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, @@ -539,9 +551,11 @@ UINT8 ScramblerSupport; /** Offset 0x01E1 - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2 + Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, + 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP + User Profile 5 + 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP + Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5 **/ UINT8 SpdProfileSelected; @@ -553,7 +567,7 @@ /** Offset 0x01E3 - Reserved **/ - UINT8 Reserved5; + UINT8 Reserved4; /** Offset 0x01E4 - Memory Voltage DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM @@ -582,7 +596,7 @@ /** Offset 0x01E9 - Reserved **/ - UINT8 Reserved6; + UINT8 Reserved5; /** Offset 0x01EA - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected @@ -604,7 +618,7 @@ /** Offset 0x01EF - Reserved **/ - UINT8 Reserved7; + UINT8 Reserved6; /** Offset 0x01F0 - tREFI Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected @@ -759,7 +773,7 @@ /** Offset 0x0221 - Reserved **/ - UINT8 Reserved8[3]; + UINT8 Reserved7[3]; /** Offset 0x0224 - Temporary MMIO address for GMADR Obsolete field now and it has been extended to 64 bit address, used GmAdr64 @@ -996,7 +1010,7 @@ /** Offset 0x0289 - Reserved **/ - UINT8 Reserved9[7]; + UINT8 Reserved8[7]; /** Offset 0x0290 - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address space to access GMADR @@ -1022,7 +1036,7 @@ /** Offset 0x029B - Reserved **/ - UINT8 Reserved10; + UINT8 Reserved9; /** Offset 0x029C - SA/Uncore Voltage Override The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override @@ -1053,7 +1067,7 @@ /** Offset 0x02A2 - Reserved **/ - UINT8 Reserved11[111]; + UINT8 Reserved10[111]; /** Offset 0x0311 - Enable Gt CLOS 0(Default)=Disable, 1=Enable @@ -1223,7 +1237,7 @@ /** Offset 0x037B - Reserved **/ - UINT8 Reserved12[54]; + UINT8 Reserved11[54]; /** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo Set ASPM Control configuration @@ -1345,8 +1359,7 @@ UINT8 Avx2RatioOffset; /** Offset 0x03C4 - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. + DEPRECATED **/ UINT8 Avx3RatioOffset; @@ -1381,7 +1394,7 @@ /** Offset 0x03CD - Reserved **/ - UINT8 Reserved13; + UINT8 Reserved12; /** Offset 0x03CE - Ring Downbin Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always @@ -1404,7 +1417,7 @@ /** Offset 0x03D1 - Reserved **/ - UINT8 Reserved14; + UINT8 Reserved13; /** Offset 0x03D2 - Ring voltage override The ring voltage override which is applied to the entire range of cpu ring frequencies. @@ -1450,7 +1463,7 @@ /** Offset 0x03DC - Reserved **/ - UINT8 Reserved15[24]; + UINT8 Reserved14[24]; /** Offset 0x03F4 - Core VF Point Offset Mode Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. @@ -1462,7 +1475,7 @@ /** Offset 0x03F5 - Reserved **/ - UINT8 Reserved16; + UINT8 Reserved15; /** Offset 0x03F6 - Core VF Point Offset Array used to specifies the Core Voltage Offset applied to the each selected VF @@ -1489,7 +1502,7 @@ /** Offset 0x0433 - Reserved **/ - UINT8 Reserved17[25]; + UINT8 Reserved16[25]; /** Offset 0x044C - Per Core Max Ratio override Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new @@ -1505,7 +1518,7 @@ /** Offset 0x0455 - Reserved **/ - UINT8 Reserved18[5]; + UINT8 Reserved17[5]; /** Offset 0x045A - Pvd Ratio Threshold Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default. @@ -1527,7 +1540,7 @@ /** Offset 0x045D - Reserved **/ - UINT8 Reserved19[62]; + UINT8 Reserved18[62]; /** Offset 0x049B - BCLK Frequency Source Clock source of BCLK OC frequency, 1:CPU BCLK, 2:PCH BCLK, 3:External CLK @@ -1544,7 +1557,7 @@ /** Offset 0x049D - Reserved **/ - UINT8 Reserved20[3]; + UINT8 Reserved19[3]; /** Offset 0x04A0 - CPU BCLK OC Frequency CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 @@ -1554,7 +1567,7 @@ /** Offset 0x04A4 - Reserved **/ - UINT8 Reserved21[40]; + UINT8 Reserved20[40]; /** Offset 0x04CC - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable @@ -1574,7 +1587,7 @@ /** Offset 0x04CF - Reserved **/ - UINT8 Reserved22; + UINT8 Reserved21; /** Offset 0x04D0 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable @@ -1638,7 +1651,7 @@ /** Offset 0x0509 - Reserved **/ - UINT8 Reserved23[32]; + UINT8 Reserved22[32]; /** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value. @@ -1825,7 +1838,7 @@ /** Offset 0x0745 - Reserved **/ - UINT8 Reserved24; + UINT8 Reserved23; /** Offset 0x0746 - SMBUS Base Address SMBUS Base Address (IO space). @@ -1846,7 +1859,7 @@ /** Offset 0x075B - Reserved **/ - UINT8 Reserved25[14]; + UINT8 Reserved24[14]; /** Offset 0x0769 - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc @@ -1855,7 +1868,7 @@ /** Offset 0x077B - Reserved **/ - UINT8 Reserved26[93]; + UINT8 Reserved25[93]; /** Offset 0x07D8 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 @@ -1917,7 +1930,7 @@ /** Offset 0x07F5 - Reserved **/ - UINT8 Reserved27[3]; + UINT8 Reserved26[3]; /** Offset 0x07F8 - DMIC<N> Data Pin Muxing Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* @@ -1954,7 +1967,7 @@ /** Offset 0x080D - Reserved **/ - UINT8 Reserved28; + UINT8 Reserved27; /** Offset 0x080E - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, @@ -1977,7 +1990,7 @@ /** Offset 0x0811 - Reserved **/ - UINT8 Reserved29[3]; + UINT8 Reserved28[3]; /** Offset 0x0814 - Serial Io Uart Debug BaudRate Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, @@ -2005,7 +2018,7 @@ /** Offset 0x081B - Reserved **/ - UINT8 Reserved30; + UINT8 Reserved29; /** Offset 0x081C - Serial Io Uart Debug Mmio Base Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode @@ -2325,7 +2338,7 @@ /** Offset 0x0854 - Reserved **/ - UINT8 Reserved31; + UINT8 Reserved30; /** Offset 0x0855 - Extern Therm Status Enables/Disable Extern Therm Status @@ -2365,7 +2378,7 @@ /** Offset 0x085B - Reserved **/ - UINT8 Reserved32; + UINT8 Reserved31; /** Offset 0x085C - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) @@ -2471,7 +2484,7 @@ /** Offset 0x086D - Reserved **/ - UINT8 Reserved33[2]; + UINT8 Reserved32[2]; /** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP @@ -2530,7 +2543,7 @@ /** Offset 0x087E - Reserved **/ - UINT8 Reserved34; + UINT8 Reserved33; /** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) @@ -2740,7 +2753,7 @@ /** Offset 0x08A8 - Reserved **/ - UINT8 Reserved35[2]; + UINT8 Reserved34[2]; /** Offset 0x08AA - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) @@ -2772,7 +2785,7 @@ /** Offset 0x08AF - Reserved **/ - UINT8 Reserved36; + UINT8 Reserved35; /** Offset 0x08B0 - User Manual Threshold Disabled: Predefined threshold will be used.\n @@ -2846,7 +2859,7 @@ /** Offset 0x08BB - Reserved **/ - UINT8 Reserved37; + UINT8 Reserved36; /** Offset 0x08BC - Post Code Output Port This option configures Post Code Output Port @@ -2873,7 +2886,7 @@ /** Offset 0x08C1 - Reserved **/ - UINT8 Reserved38[3]; + UINT8 Reserved37[3]; /** Offset 0x08C4 - BCLK RFI Frequency Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No @@ -2923,7 +2936,7 @@ /** Offset 0x08DB - Reserved **/ - UINT8 Reserved39[3]; + UINT8 Reserved38[3]; /** Offset 0x08DE - REFRESH_PANIC_WM Refresh Panic Watermark, range 1-9, Default is 9 @@ -2949,7 +2962,7 @@ /** Offset 0x08E2 - Reserved **/ - UINT8 Reserved40[9]; + UINT8 Reserved39[9]; /** Offset 0x08EB - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external @@ -2972,7 +2985,7 @@ /** Offset 0x08EE - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved40; /** Offset 0x08EF - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of @@ -2989,7 +3002,7 @@ /** Offset 0x08F1 - Reserved **/ - UINT8 Reserved42[3]; + UINT8 Reserved41[3]; /** Offset 0x08F4 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -3003,7 +3016,7 @@ /** Offset 0x08F9 - Reserved **/ - UINT8 Reserved43[95]; + UINT8 Reserved42[95]; /** Offset 0x0958 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -3019,7 +3032,7 @@ /** Offset 0x095C - Reserved **/ - UINT8 Reserved44[12]; + UINT8 Reserved43[12]; /** Offset 0x0968 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -3085,7 +3098,7 @@ /** Offset 0x0972 - Reserved **/ - UINT8 Reserved45[2]; + UINT8 Reserved44[2]; /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs @@ -3109,8 +3122,7 @@ UINT8 Avx2VoltageScaleFactor; /** Offset 0x0A95 - Avx512 Voltage Guardband Scaling Factor - AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200 - in 1/100 units, where a value of 125 would apply a 1.25 scale factor. + DEPRECATED **/ UINT8 Avx512VoltageScaleFactor; @@ -3123,7 +3135,7 @@ /** Offset 0x0A97 - Reserved **/ - UINT8 Reserved46; + UINT8 Reserved45; /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT Select RX pin muxing for SerialIo UART used for debug @@ -3149,7 +3161,7 @@ /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved47[16]; + UINT8 Reserved46[16]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index efacdc19..ea462a4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -1605,7 +1605,7 @@ UINT8 AvxDisable; /** Offset 0x06C8 - Avx3Disable - Enable or Disable AVX3 Support + DEPRECATED 0: Enable, 1: Disable **/ UINT8 Avx3Disable; @@ -3245,7 +3245,7 @@ UINT8 DisableProcHotOut; /** Offset 0x0CDE - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. + Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; @@ -3365,7 +3365,7 @@ UINT8 PpmIrmSetting; /** Offset 0x0CF2 - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable + Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; @@ -3881,7 +3881,7 @@ /** Offset 0x0FD8 **/ - UINT8 UnusedUpdSpace41[6]; + UINT8 UnusedUpdSpace40[6]; /** Offset 0x0FDE **/ -- To view, visit https://review.coreboot.org/c/coreboot/+/55094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice44dfbd41e8eca4f171b76e7a3dcdf133a516fd Gerrit-Change-Number: 55094 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp1_1/romstage.c: Remove MCU update
by Angel Pons (Code Review) 31 May '21

31 May '21

Attention is currently required from: Frans Hendriks, Lee Leahy, Paul Menzel, Huang Jin, Arthur Heymans, Patrick Rudolph, Wim Vervoorn. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55064 ) Change subject: drivers/intel/fsp1_1/romstage.c: Remove MCU update ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72c7b821e04169ae237d8adb6a8348f06e87b047 Gerrit-Change-Number: 55064 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Huang Jin <huang.jin(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Mon, 31 May 2021 09:25:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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