coreboot-gerrit May 2021

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Change in coreboot[master]: soc/intel/xeon_sp: Remove PARALLEL_MP_AP_WORK
by Arthur Heymans (Code Review) 31 May '21

31 May '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang, Patrick Rudolph. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55099 ) Change subject: soc/intel/xeon_sp: Remove PARALLEL_MP_AP_WORK ...................................................................... soc/intel/xeon_sp: Remove PARALLEL_MP_AP_WORK This is not required anymore. ocp/tiogapass however requires this to fill the smbios table. Change-Id: I36b72e908189b752013eaf898971808224630894 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/ocp/tiogapass/Kconfig M src/soc/intel/xeon_sp/Kconfig 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/55099/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index fd4e36f..72becee 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -14,6 +14,7 @@ select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 select VPD + select PARALLEL_MP_AP_WORK config MAINBOARD_DIR string diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 09f72a3..9345873 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -36,7 +36,6 @@ select POSTCAR_STAGE select IOAPIC select PARALLEL_MP - select PARALLEL_MP_AP_WORK select PMC_GLOBAL_RESET_ENABLE_LOCK select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK -- To view, visit https://review.coreboot.org/c/coreboot/+/55099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36b72e908189b752013eaf898971808224630894 Gerrit-Change-Number: 55099 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them
by Arthur Heymans (Code Review) 31 May '21

31 May '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55098 ) Change subject: soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them ...................................................................... soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them Move locking CPU MSRs during CPU init instead of using CONFIG_PARALLEL_MP_AP_WORK functions. The AES Lock enable bit caused CPU exception errors as this should not run on HT siblings. The set_aesni_lock() function takes care of that. Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/cpu.c 2 files changed, 10 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/55098/1 diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 9164b7c..19bf2af 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -14,7 +14,6 @@ #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/cpu.h> -#include <soc/msr.h> #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/p2sb.h> @@ -144,22 +143,6 @@ } -static void set_msr_locks(void *unused) -{ - /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions */ - msr_t msr; - - /* Lock Turbo */ - msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); - msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); - wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); - - /* Lock AES enable */ - msr = rdmsr(MSR_FEATURE_CONFIG); - msr.lo |= FEATURE_CONFIG_LOCK; - wrmsr(MSR_FEATURE_CONFIG, msr); -} - static void set_imc_locks(void) { struct device *dev = 0; @@ -182,7 +165,6 @@ /* LOCK PAM */ pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); - mp_run_on_all_cpus(set_msr_locks, NULL); set_pcu_locks(); set_imc_locks(); set_upi_locks(); diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 339bf09..37370c1 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -23,6 +23,7 @@ #include <soc/soc_util.h> #include <soc/smmrelocate.h> #include <soc/util.h> +#include <soc/pci_devs.h> #include "chip.h" @@ -103,6 +104,15 @@ /* Enable Vmx */ set_vmx_and_lock(); + set_aesni_lock(); + + /* + * The MSRs and CSRS have the same register layout. Use the CSRS bit definitions + * Lock Turbo. Did FSP-S set this up??? + */ + msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); + msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); + wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); } static struct device_operations cpu_dev_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/55098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21598c3e9a153dce25a09b187ddf9cf6363039d3 Gerrit-Change-Number: 55098 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/Linuxboot/u-root: Explicitly set GO111MODULE=off
by Paul Menzel (Code Review) 31 May '21

31 May '21

Attention is currently required from: Martin Roth, Stefan Reinauer, Christian Walter, Arthur Heymans, Ron Minnich. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55095 ) Change subject: payloads/Linuxboot/u-root: Explicitly set GO111MODULE=off ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55095/comment/3b20d7b4_07c83cf9 PS1, Line 9: GO111MODULe capital E -- To view, visit https://review.coreboot.org/c/coreboot/+/55095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie90b400418ccd06426a0e00ec7f7932066f57d7e Gerrit-Change-Number: 55095 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 31 May 2021 14:03:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add macros to increase code readability
by Subrata Banik (Code Review) 31 May '21

31 May '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Sugnan Prabhu S, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55097 ) Change subject: drivers/intel/mipi_camera: Add macros to increase code readability ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Gerrit-Change-Number: 55097 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 May 2021 13:59:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Set MSR locks
by Arthur Heymans (Code Review) 31 May '21

31 May '21

Attention is currently required from: Marc Jones. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52160 ) Change subject: soc/intel/xeon_sp: Set MSR locks ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52160/comment/7b3a9f02_2d0a32c5 PS2, Line 11: MSR_FEATURE_CONFIG > This is already done during the CPU init. Doing it again causes exception errors. Eh nvm. I confused FEATURE_CONFIG with FEATURE_CONTROL -- To view, visit https://review.coreboot.org/c/coreboot/+/52160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430 Gerrit-Change-Number: 52160 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Comment-Date: Mon, 31 May 2021 13:49:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Set MSR locks
by Arthur Heymans (Code Review) 31 May '21

31 May '21

Attention is currently required from: Marc Jones. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52160 ) Change subject: soc/intel/xeon_sp: Set MSR locks ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52160/comment/faed4645_b104b2c5 PS2, Line 11: MSR_FEATURE_CONFIG This is already done during the CPU init. Doing it again causes exception errors. https://review.coreboot.org/c/coreboot/+/52160/comment/84e35d5b_bf109fa1 PS2, Line 12: TURBO_ACTIVATION_RATIO_LOCK Any reason to do this here with PARALLEL_MP_AP_WORK instead of during the CPU init? -- To view, visit https://review.coreboot.org/c/coreboot/+/52160 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430 Gerrit-Change-Number: 52160 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Comment-Date: Mon, 31 May 2021 13:40:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Configure FIVR, VR, Turbo ratios
by V Sowmya (Code Review) 31 May '21

31 May '21

Hello build bot (Jenkins), Kedar J. Karanje, Maulik V Vaghela, vagdevi.p(a)intel.com, Tim Wawrzynczak, Vinay Kumar, Balaji Manigandan, Sanju Jose Thottan, Patrick Rudolph, Baieswara Reddy Sagili, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54055 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Configure FIVR, VR, Turbo ratios ...................................................................... soc/intel/alderlake: Configure FIVR, VR, Turbo ratios This patch configures the following, * VR configurations * FIVR configurations * CPU Power Mgmt Test Config * Turbo ratios * LTR config for PCIE Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Change-Id: I8d485872c8bae32f83ebf94bdaa4c6a793976ce7 --- M src/soc/intel/alderlake/fsp_params.c 1 file changed, 36 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/54055/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/54055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d485872c8bae32f83ebf94bdaa4c6a793976ce7 Gerrit-Change-Number: 54055 Gerrit-PatchSet: 5 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kedar J. Karanje <kedar.j.karanje(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: vagdevi.p(a)intel.com Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: Reserve wlan & wpss dram memory regions
by Ravi Kumar Bokka (Code Review) 31 May '21

31 May '21

Attention is currently required from: Ravi kumar. Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50587 ) Change subject: sc7280: Reserve wlan & wpss dram memory regions ...................................................................... Patch Set 38: (1 comment) File src/soc/qualcomm/sc7280/memlayout.ld: https://review.coreboot.org/c/coreboot/+/50587/comment/d1a286ce_df04e7bf PS38, Line 56: REGION(dram_wpss, 0x9AE00000, 0x1900000, 0x1000) > Hi Julius, […] I have check with wlan team internally. about wpss and wlan and these are wifi fw regions wpss is inside soc wlan is on the remote wlan card So reserving those regions in coreboot to avaid kernel panic while loading kernel image -- To view, visit https://review.coreboot.org/c/coreboot/+/50587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Gerrit-Change-Number: 50587 Gerrit-PatchSet: 38 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Comment-Date: Mon, 31 May 2021 13:03:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add macros to increase code readability
by Varshit B Pandya (Code Review) 31 May '21

31 May '21

Attention is currently required from: Maulik V Vaghela, Sugnan Prabhu S, Subrata Banik, Patrick Rudolph. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55097 ) Change subject: drivers/intel/mipi_camera: Add macros to increase code readability ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55097/comment/2256e71e_e2d3d27d PS3, Line 10: CL : 52013 > CB:52013 Done https://review.coreboot.org/c/coreboot/+/55097/comment/4650373b_f607313f PS3, Line 14: : BUG=none : : BRANCH=none > ideally you don't need unless specified Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Gerrit-Change-Number: 55097 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 May 2021 12:51:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add macros to increase code readability
by Subrata Banik (Code Review) 31 May '21

31 May '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Sugnan Prabhu S, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55097 ) Change subject: drivers/intel/mipi_camera: Add macros to increase code readability ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55097/comment/3d87624b_3ebb183b PS3, Line 10: CL : 52013 CB:52013 https://review.coreboot.org/c/coreboot/+/55097/comment/7190dc5c_09e67306 PS3, Line 14: : BUG=none : : BRANCH=none ideally you don't need unless specified -- To view, visit https://review.coreboot.org/c/coreboot/+/55097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Gerrit-Change-Number: 55097 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 May 2021 12:46:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2021