coreboot-gerrit May 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7280: cpucp loading changes
by build bot (Jenkins) (Code Review) 31 May '21

31 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: cpucp loading changes ...................................................................... Patch Set 42: (40 comments) File src/soc/qualcomm/sc7280/cpucp_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/f6829c11_0f2dff85 PS42, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/a6265b2d_fe4fe29f PS42, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/4669c40a_ae03c894 PS42, Line 16: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/e2391a25_fef3f1fe PS42, Line 16: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/2d5bc9cd_67bbce41 PS42, Line 18: /* allow NS access to EPSS memory*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/c6d90a17_16506939 PS42, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/e9aa5440_910c14ef PS42, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/6bcca8ed_572e1bfa PS42, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/d74a748f_18cbad13 PS42, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/e5fffcc8_5b857cf4 PS42, Line 22: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/3c54e6c8_6004385a PS42, Line 22: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/eef20741_f23d22b1 PS42, Line 24: /* Enable subsystem clock. Required for CPUCP PDMEM access*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/761a4f9a_b76918f3 PS42, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/91ad60dc_6afc8c28 PS42, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/6beba241_3243ea3c PS42, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/3d13fd2e_22a1741d PS42, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/67b67ed0_61eb7596 PS42, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/ce0ed408_e668e155 PS42, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/622280be_098e78d3 PS42, Line 32: bool cpucp_fw_entry; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/7444f7d9_9e7b3153 PS42, Line 32: bool cpucp_fw_entry; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/822dc988_e8efdc1c PS42, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/a16cce31_f8c1b3a5 PS42, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/9c6b974c_03ebe096 PS42, Line 35: struct prog cpucp_fw_prog = code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/23f7b3b5_9e054d72 PS42, Line 35: struct prog cpucp_fw_prog = please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/b136c7a1_6cbf9801 PS42, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/f4210956_9d029564 PS42, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/ff010d0f_1f55639e PS42, Line 38: cpucp_prepare(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/d380c8cd_aeb95ab9 PS42, Line 38: cpucp_prepare(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/d70e5a10_6acb1985 PS42, Line 40: if (prog_locate(&cpucp_fw_prog)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/8ce4d526_06c1182e PS42, Line 40: if (prog_locate(&cpucp_fw_prog)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/7f0154be_ae2e9407 PS42, Line 41: die("SOC imagpe: CPUCP_FW not found"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/c958acf9_6b1214e4 PS42, Line 41: die("SOC imagpe: CPUCP_FW not found"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/ac361575_1a04f166 PS42, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/bf93f634_f0a13005 PS42, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/55d63b52_069bfdf7 PS42, Line 44: if (!cpucp_fw_entry) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/b7446a95_c046768b PS42, Line 44: if (!cpucp_fw_entry) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/bcb275a0_1b4b1ed0 PS42, Line 45: die("SOC image: CPUCP load failed"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/a5df598e_08a6e7f4 PS42, Line 45: die("SOC image: CPUCP load failed"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/7ea426c2_c3dbed07 PS42, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120394): https://review.coreboot.org/c/coreboot/+/49768/comment/58b885a9_0c180683 PS42, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 31 May 2021 15:49:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: aop loading changes
by build bot (Jenkins) (Code Review) 31 May '21

31 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49767 ) Change subject: sc7280: aop loading changes ...................................................................... Patch Set 42: (26 comments) File src/soc/qualcomm/sc7280/aop_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/dd875ff3_0887b154 PS42, Line 11: bool aop_fw_entry; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/d9d91a8e_2bbc50e0 PS42, Line 11: bool aop_fw_entry; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/9aea8d4e_c627679c PS42, Line 13: struct prog aop_fw_prog = code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/7d10a9b9_8bb416b3 PS42, Line 13: struct prog aop_fw_prog = please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/c77d21ff_c021ab5d PS42, Line 14: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/9c7addaf_f27fad00 PS42, Line 14: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/8218a26d_c852ad1f PS42, Line 16: if (prog_locate(&aop_fw_prog)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/b891e520_aa175fc0 PS42, Line 16: if (prog_locate(&aop_fw_prog)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/a3502249_9e0d8f1b PS42, Line 17: die("SOC image: AOP_FW not found"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/80a775e0_977968e1 PS42, Line 17: die("SOC image: AOP_FW not found"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/46504379_d1baa048 PS42, Line 19: aop_fw_entry = selfload(&aop_fw_prog); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/606c2a4c_65756e35 PS42, Line 19: aop_fw_entry = selfload(&aop_fw_prog); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/d8d65bce_2738f58e PS42, Line 20: if (!aop_fw_entry) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/ac0eab1e_c679acf1 PS42, Line 20: if (!aop_fw_entry) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/e67f71c6_5d3c8158 PS42, Line 21: die("SOC image: AOP load failed"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/1a17c44e_5904f316 PS42, Line 21: die("SOC image: AOP load failed"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/32d8d76c_76abbdbc PS42, Line 23: clock_reset_aop(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/7ddc7fa0_2cc75949 PS42, Line 23: clock_reset_aop(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/091b8285_6be371a7 PS42, Line 25: printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/41cfa1de_e84ea811 PS42, Line 25: printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/mmu.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/0636b482_5419da9f PS42, Line 25: mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), CACHED_RAM); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/a5187bbb_203afef2 PS42, Line 25: mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), CACHED_RAM); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/4cb495ae_96f5841f PS42, Line 26: mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), CACHED_RAM); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/2bb136b6_b8d77ab4 PS42, Line 26: mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), CACHED_RAM); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/3850e902_053f11cb PS42, Line 21: REGION_SIZE(dram_aop) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120393): https://review.coreboot.org/c/coreboot/+/49767/comment/a48d163a_eedcbb93 PS42, Line 21: REGION_SIZE(dram_aop) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/49767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec Gerrit-Change-Number: 49767 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 31 May 2021 15:49:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: shrm.elf loading changes
by build bot (Jenkins) (Code Review) 31 May '21

31 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49392 ) Change subject: sc7280: shrm.elf loading changes ...................................................................... Patch Set 43: (1 comment) File src/soc/qualcomm/sc7280/shrm_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120392): https://review.coreboot.org/c/coreboot/+/49392/comment/73579892_1375721e PS43, Line 9: void shrm_fw_load_reset() Bad function definition - void shrm_fw_load_reset() should probably be void shrm_fw_load_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 43 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 31 May 2021 15:49:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add target specific GPIO pin definitions
by build bot (Jenkins) (Code Review) 31 May '21

31 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Taniya Das, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55077 ) Change subject: sc7280: Add target specific GPIO pin definitions ...................................................................... Patch Set 2: (1 comment) File src/soc/qualcomm/sc7280/include/soc/gpio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120380): https://review.coreboot.org/c/coreboot/+/55077/comment/86c26e6b_beeeb24b PS2, Line 10: #define PIN(index, func1, func2, func3, func4) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/c/coreboot/+/55077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63bcaed78a6eeb0e6fad857b89d40181613e50cc Gerrit-Change-Number: 55077 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 31 May 2021 15:45:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Reserve wlan & wpss dram regions index order corrected
by Ravi kumar (Code Review) 31 May '21

31 May '21

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55102 ) Change subject: sc7280: Reserve wlan & wpss dram regions index order corrected ...................................................................... sc7280: Reserve wlan & wpss dram regions index order corrected BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I8501e9ce52bb296bb42797d8b43fd38174b80550 --- M src/soc/qualcomm/sc7280/soc.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/55102/1 diff --git a/src/soc/qualcomm/sc7280/soc.c b/src/soc/qualcomm/sc7280/soc.c index 19cfbd9..c0fa32f 100644 --- a/src/soc/qualcomm/sc7280/soc.c +++ b/src/soc/qualcomm/sc7280/soc.c @@ -12,9 +12,9 @@ ddr_region->size / KiB); reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); - reserved_ram_resource(dev, 4, (uintptr_t)_dram_wlan / KiB, + reserved_ram_resource(dev, 2, (uintptr_t)_dram_wlan / KiB, REGION_SIZE(dram_wlan) / KiB); - reserved_ram_resource(dev, 5, (uintptr_t)_dram_wpss / KiB, + reserved_ram_resource(dev, 3, (uintptr_t)_dram_wpss / KiB, REGION_SIZE(dram_wpss) / KiB); } -- To view, visit https://review.coreboot.org/c/coreboot/+/55102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8501e9ce52bb296bb42797d8b43fd38174b80550 Gerrit-Change-Number: 55102 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7280: aop loading changes
by Ravi kumar (Code Review) 31 May '21

31 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49767 to look at the new patch set (#42). Change subject: sc7280: aop loading changes ...................................................................... sc7280: aop loading changes Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/aop_load_reset.c A src/soc/qualcomm/sc7280/include/soc/aop.h M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/mmu.c M src/soc/qualcomm/sc7280/soc.c 6 files changed, 57 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/49767/42 -- To view, visit https://review.coreboot.org/c/coreboot/+/49767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90b0f48e15df390970e027bff2065b7a89b14cec Gerrit-Change-Number: 49767 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: cpucp loading changes
by Ravi kumar (Code Review) 31 May '21

31 May '21

Attention is currently required from: Ravi kumar, Shelley Chen, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Patrick Georgi, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49768 to look at the new patch set (#42). Change subject: sc7280: cpucp loading changes ...................................................................... sc7280: cpucp loading changes Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/cpucp_load_reset.c A src/soc/qualcomm/sc7280/include/soc/cpucp.h M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/soc.c 6 files changed, 76 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49768/42 -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7280: add support for clock driver
by Ravi kumar (Code Review) 31 May '21

31 May '21

Attention is currently required from: Shelley Chen, Ravi kumar, Taniya Das, Paul Menzel, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Taniya Das, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50580 to look at the new patch set (#40). Change subject: sc7280: add support for clock driver ...................................................................... sc7280: add support for clock driver The clock driver supports configuring the general purpose PLLs, configuring the root clock generator(RCG), enable clock branch and also the block resets. It supports the clock consumers for QUP, SDCC, PCIE, Display to be able to configure & enable the desired clocks. The clock driver also supports reset of subsystems like AOP and SHRM. BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Signed-off-by: Taniya Das <tdas(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h A src/soc/qualcomm/sc7280/include/soc/clock.h 4 files changed, 1,198 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/50580/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/50580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590a93cda0d6eccb51b54692b620d43ccacede77 Gerrit-Change-Number: 50580 Gerrit-PatchSet: 40 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <tdas(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <tdas(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: payloads/Linuxboot/u-root: Explicitly set GO111MODULE=off
by Arthur Heymans (Code Review) 31 May '21

31 May '21

Attention is currently required from: Martin Roth, Paul Menzel, Stefan Reinauer, Christian Walter, Arthur Heymans, Ron Minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55095 ) Change subject: payloads/Linuxboot/u-root: Explicitly set GO111MODULE=off ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/55095/comment/78f261b6_3d4f4670 PS1, Line 9: GO111MODULe > capital E Done -- To view, visit https://review.coreboot.org/c/coreboot/+/55095 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie90b400418ccd06426a0e00ec7f7932066f57d7e Gerrit-Change-Number: 55095 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 31 May 2021 15:34:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd/cezanne: remove warm reset flag code
by Felix Held (Code Review) 31 May '21

31 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55101 ) Change subject: [WIP] soc/amd/cezanne: remove warm reset flag code ...................................................................... [WIP] soc/amd/cezanne: remove warm reset flag code The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register, the NCP_WARM_BOOT bit never got set. [1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev 3.01 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b --- M src/soc/amd/cezanne/cpu.c M src/soc/amd/cezanne/include/soc/iomap.h M src/soc/amd/cezanne/include/soc/southbridge.h M src/soc/amd/cezanne/reset.c 4 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/55101/1 diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index f002665..ddc49a9 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -55,8 +55,6 @@ /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - set_warm_reset_flag(); } static void zen_2_3_init(struct device *dev) diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h index 4c4252a..4f01c64 100644 --- a/src/soc/amd/cezanne/include/soc/iomap.h +++ b/src/soc/amd/cezanne/include/soc/iomap.h @@ -44,7 +44,6 @@ #endif /* ENV_X86 */ /* I/O Ranges */ -#define NCP_ERR 0x00f0 #define ACPI_IO_BASE 0x0400 #define ACPI_PM_EVT_BLK (ACPI_IO_BASE + 0x00) #define ACPI_PM1_STS (ACPI_PM_EVT_BLK + 0x00) diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index e58a8cd..e82f33f 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -118,9 +118,6 @@ #define FCH_AOAC_DEV_AMBA 17 #define FCH_AOAC_DEV_ESPI 27 -/* IO 0xf0 NCP Error */ -#define NCP_WARM_BOOT (1 << 7) /* Write-once */ - void fch_pre_init(void); void fch_early_init(void); void fch_init(void *chip_info); diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c index b05c0b6..1360bd5 100644 --- a/src/soc/amd/cezanne/reset.c +++ b/src/soc/amd/cezanne/reset.c @@ -7,19 +7,6 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> -/* TODO: is NCP_ERR still valid? It appears reserved and always 0xff. b/184281092 */ -void set_warm_reset_flag(void) -{ - uint8_t ncp = inb(NCP_ERR); - - outb(NCP_ERR, ncp | NCP_WARM_BOOT); -} - -int is_warm_reset(void) -{ - return !!(inb(NCP_ERR) & NCP_WARM_BOOT); -} - void do_cold_reset(void) { /* De-assert and then assert all PwrGood signals on CF9 reset. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/55101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b Gerrit-Change-Number: 55101 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2021