coreboot-gerrit May 2021

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Change in coreboot[master]: drivers/i2c/designware: Report I2C timings for additional bus speeds
by Furquan Shaikh (Code Review) 31 May '21

31 May '21

Attention is currently required from: Tim Wawrzynczak, Werner Zeh, Kyösti Mälkki. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55088 ) Change subject: drivers/i2c/designware: Report I2C timings for additional bus speeds ...................................................................... Patch Set 2: (1 comment) File src/drivers/i2c/designware/dw_i2c.c: https://review.coreboot.org/c/coreboot/+/55088/comment/e8d3b796_a9dfb7f0 PS2, Line 834: Now check if there are more speed settings available and report them as well. Would it be bad to expose information about all different I2C speeds to the OS? We can skip the ones where it is not possible to calculate sane values i.e. revert CB:34385. The problem that CB:34385 was trying to address is "dw_i2c: bad counts" message. We can either lower the severity of the print or drop it completely: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… -- To view, visit https://review.coreboot.org/c/coreboot/+/55088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If921e0613864660dc1bb8d7c1b30fb9db8ac655d Gerrit-Change-Number: 55088 Gerrit-PatchSet: 2 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 31 May 2021 23:57:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add helpers for cbi fw_config settings.
by Furquan Shaikh (Code Review) 31 May '21

31 May '21

Attention is currently required from: Raul Rangel, Martin Roth, Paul Menzel, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54639 ) Change subject: mb/google/guybrush: Add helpers for cbi fw_config settings. ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/guybrush/variants/guybrush/helpers.c: https://review.coreboot.org/c/coreboot/+/54639/comment/be814d1d_a94302e2 PS4, Line 32: if (config == UNDEFINED_FW_CONFIG || ! fw_config_probe(FW_CONFIG(FP, FP_PRESENT))) > For now I'm going to keep just doing the manual probe. […] We don't really need the manual probing using fw_config at variant level. See my comment here: https://review.coreboot.org/c/coreboot/+/54639/comment/3edfe9fa_89d983e1/. With that, we can achieve reuse of helpers at baseboard level without having to define a global fw_config space. https://review.coreboot.org/c/coreboot/+/54639/comment/67cbfeaf_47d399a3 PS4, Line 44: get_variant_wwan_type > You mention having this live in guybrush baseboard, but I don't see how that works if not every plat […] The helper functions at the baseboard level don't need to use fw_config at all. fw_config can be used at the override tree level to enable/disable appropriate devices. That allows use of common helper functions without having to define a global fw_config space. For both FPMCU and WWAN there are already devices present in the device tree. `variant_has_fpmcu()` was already written with that in mind. For WWAN, similar support is required. Guybrush uses WWAN on gpp_bridge_2. Thus, gpp_bridge_2 is the device that needs to be enabled/disabled using appropriate fw_config (which in this case is WWAN_FM350GL). And the baseboard function only needs to check the state of that device. In fact, it needs exactly the same code that `variant_has_fpmcu()` has implemented, but with a different device_path. This can be achieved with a helper function as follows: ``` bool variant_has_device_enabled(const struct *device_path, size_t path_length) { » const struct device *dev = find_dev_nested_path(all_devices->link_list, device_path, path_length); » return is_dev_enabled(dev); } bool variant_has_fpmcu(void) { » static const struct device_path fpmcu_path[] = { » » { » » » .type = DEVICE_PATH_MMIO, » » » .mmio.addr = APU_UART1_BASE » » }, » » { » » » .type = DEVICE_PATH_GENERIC, » » » .generic.id = 0, » » » .generic.subid = 0 » » }, » }; » return variant_has_device_enabled(fpmcu_path, ARRAY_SIZE(fpmcu_path)); } bool variant_has_pcie_wwan(void) { » static const struct device_path pcie_wwan_path[] = { » » { » » » .type = DEVICE_PATH_PCI, » » » .pci.devfn = PCIE_GPP_2_2_DEVFN, » » }, » }; » return variant_has_device_enabled(pcie_wwan_path, ARRAY_SIZE(pcie_wwan_path)); } ``` At the override tree level you only need this in guybrush/overridetree.cb: ``` device ref gpp_bridge_2 on » probe WWAN WWAN_FM350GL end # WWAN ``` In the future if there are any variants that use a mix of PCIe and non-PCIe WWAN cards, they would need a similar probe statement for gpp_bridge_2. If there are variants that use only PCIe WWAN cards, they don't need to define fw_config for it and the override tree would look like this: ``` device ref gpp_bridge_2 on end # WWAN ``` With the support in baseboard implemented using device state rather than fw_config, there will not be any changes required to helpers.c for any variants and the fw_config defined at variant level also works fine. It allows for reuse as well as limited work at variant level for partners to support this. -- To view, visit https://review.coreboot.org/c/coreboot/+/54639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6 Gerrit-Change-Number: 54639 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 31 May 2021 20:00:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: introduce and use chipset device tree
by Felix Held (Code Review) 31 May '21

31 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50626 ) Change subject: soc/amd/picasso: introduce and use chipset device tree ...................................................................... Patch Set 6: (2 comments) Patchset: PS4: > for now I just put devices in there that always need to be on. […] Done File src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb: https://review.coreboot.org/c/coreboot/+/50626/comment/f13e86ba_82a475b8 PS4, Line 386: device pci 14.0 on end # SM > the patch is probably not ready yet, but wanted to push the changes i did in the meantime to have a […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Gerrit-Change-Number: 50626 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Mon, 31 May 2021 18:51:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboards using soc/amd/picasso: use aliases for remaining PCIe devices
by Felix Held (Code Review) 31 May '21

31 May '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55104 ) Change subject: mainboards using soc/amd/picasso: use aliases for remaining PCIe devices ...................................................................... mainboards using soc/amd/picasso: use aliases for remaining PCIe devices Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566 --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/vilboz/overridetree.cb 6 files changed, 49 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/55104/1 diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 10a5d2e..932d280 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -145,19 +145,19 @@ device ref gpp_bridge_1 on end device ref gpp_bridge_4 on end # NVMe device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on end # USB 3.1 - device pci 0.4 off end # USB 3.1 - device pci 0.5 on end # Audio - device pci 0.6 on end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on end # USB 3.1 + device ref xhci_1 off end # USB 3.1 + device ref acp on end # Audio + device ref hda on end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref internal_bridge_b on - device pci 0.0 off end # AHCI - device pci 0.1 off end # integrated Ethernet MAC - device pci 0.2 off end # integrated Ethernet MAC + device ref sata off end # AHCI + device ref xgbe_0 off end # integrated Ethernet MAC + device ref xgbe_1 off end # integrated Ethernet MAC end device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index 9b21895..6a1a3bc 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -143,19 +143,19 @@ device ref iommu on end device ref gpp_bridge_0 on end # Bridge to PCIe Ethernet chip device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on end # USB 3.1 - device pci 0.4 off end # USB 3.1 - device pci 0.5 on end # Audio - device pci 0.6 on end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on end # USB 3.1 + device ref xhci_1 off end # USB 3.1 + device ref acp on end # Audio + device ref hda on end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref internal_bridge_b on - device pci 0.0 off end # AHCI - device pci 0.1 off end # integrated Ethernet MAC - device pci 0.2 off end # integrated Ethernet MAC + device ref sata off end # AHCI + device ref xgbe_0 off end # integrated Ethernet MAC + device ref xgbe_1 off end # integrated Ethernet MAC end device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index fef625f..a12d318 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -143,19 +143,19 @@ device ref iommu on end device ref gpp_bridge_2 on end # Bridge to PCIe Ethernet chip device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on end # USB 3.1 - device pci 0.4 on end # USB 3.1 - device pci 0.5 on end # Audio - device pci 0.6 on end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on end # USB 3.1 + device ref xhci_1 on end # USB 3.1 + device ref acp on end # Audio + device ref hda on end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref internal_bridge_b on - device pci 0.0 on end # AHCI - device pci 0.1 off end # integrated Ethernet MAC - device pci 0.2 off end # integrated Ethernet MAC + device ref sata on end # AHCI + device ref xgbe_0 off end # integrated Ethernet MAC + device ref xgbe_1 off end # integrated Ethernet MAC end device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 57710c2..f3ad329 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -264,10 +264,10 @@ end device ref gpp_bridge_2 on end # SD device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on # USB 3.1 + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -334,7 +334,7 @@ end end end - device pci 0.5 on + device ref acp on chip drivers/amd/i2s_machine_dev register "hid" = ""AMDI5682"" # DMIC select GPIO for ACP machine device @@ -350,8 +350,8 @@ device generic 0.0 on end end end # Audio - device pci 0.6 off end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref hda off end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref lpc_bridge on chip ec/google/chromeec diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 1ddc763..364458b2 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -258,10 +258,10 @@ device ref gpp_bridge_2 on end # SD device ref gpp_bridge_6 on end # NVME device ref internal_bridge_a on - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocessor - device pci 0.3 on # USB 3.1 + device ref gfx on end # Internal GPU + device ref gfx_hda on end # Display HDA + device ref crypto on end # Crypto Coprocessor + device ref xhci_0 on # USB 3.1 chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -330,7 +330,7 @@ end end end - device pci 0.4 on # USB 3.1 + device ref xhci_1 on # USB 3.1 chip drivers/usb/acpi # The following devices are only enabled on Picasso SKUs register "desc" = ""Root Hub"" @@ -355,7 +355,7 @@ end end end - device pci 0.5 on + device ref acp on chip drivers/amd/i2s_machine_dev register "hid" = ""AMDI5682"" # DMIC select GPIO for ACP machine device @@ -371,8 +371,8 @@ device generic 0.0 on end end end # Audio - device pci 0.6 off end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device + device ref hda off end # HDA + device ref mp2 on end # non-Sensor Fusion Hub device end device ref lpc_bridge on chip ec/google/chromeec diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 7cadaf8..5469b32 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -159,7 +159,7 @@ end end # SD device ref internal_bridge_a on - device pci 0.5 on + device ref acp on chip drivers/amd/i2s_machine_dev register "hid" = ""AMDI1015"" # DMIC select GPIO for ACP machine device -- To view, visit https://review.coreboot.org/c/coreboot/+/55104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566 Gerrit-Change-Number: 55104 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Enable TCSS
by Deepti Deshatty (Code Review) 31 May '21

31 May '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54090 to look at the new patch set (#9). Change subject: mb/google/brya: Enable TCSS ...................................................................... mb/google/brya: Enable TCSS Select SOC_INTEL_COMMON_BLOCK_TCSS to enable Type C Subsystem. TEST=Verified build for brya Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Change-Id: Ie3cb8b8836b17fa00ab0089d03fca9f22c4d702e --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/54090/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/54090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3cb8b8836b17fa00ab0089d03fca9f22c4d702e Gerrit-Change-Number: 54090 Gerrit-PatchSet: 9 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer:intel/common/block: Move mainboard api to tcss comm...
by Deepti Deshatty (Code Review) 31 May '21

31 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Sridhar Siricilla, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Sridhar Siricilla, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/54733 to look at the new patch set (#4). Change subject: mb/google/volteer:intel/common/block: Move mainboard api to tcss common block ...................................................................... mb/google/volteer:intel/common/block: Move mainboard api to tcss common block As per the comments in CB:54090 mainboard api mainboard_tcss_get_port_info() is simplified and moved to tcss common block code. Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.com> Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 --- M src/drivers/intel/pmc_mux/conn/chip.h M src/drivers/intel/pmc_mux/conn/conn.c M src/mainboard/google/volteer/mainboard.c M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/tcss.c 5 files changed, 85 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/54733/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/54733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 Gerrit-Change-Number: 54733 Gerrit-PatchSet: 4 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0
by Felix Held (Code Review) 31 May '21

31 May '21

Attention is currently required from: Jason Glenesk, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55103 ) Change subject: mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0 ...................................................................... mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/vilboz/overridetree.cb M util/mainboard/google/trembyle/template/overridetree.cb 7 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/55103/1 diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 7015185..10a5d2e 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -140,11 +140,11 @@ device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.1 on end # GPP Bridge 0 - device pci 1.2 on end # GPP Bridge 1 - device pci 1.5 on end # NVMe - device pci 8.1 on # Bridge to Bus A + device ref iommu on end + device ref gpp_bridge_0 on end + device ref gpp_bridge_1 on end + device ref gpp_bridge_4 on end # NVMe + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -154,12 +154,12 @@ device pci 0.6 on end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Bridge to Bus B + device ref internal_bridge_b on device pci 0.0 off end # AHCI device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.3 on # D14F3 bridge + device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card end end diff --git a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb index d1e0241..9b21895 100644 --- a/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/cereme/devicetree.cb @@ -140,9 +140,9 @@ device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.1 on end # Bridge to PCIe Ethernet chip - device pci 8.1 on # Bridge to Bus A + device ref iommu on end + device ref gpp_bridge_0 on end # Bridge to PCIe Ethernet chip + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -152,12 +152,12 @@ device pci 0.6 on end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Bridge to Bus B + device ref internal_bridge_b on device pci 0.0 off end # AHCI device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.3 on # D14F3 bridge + device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card end end diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index 1c20095..fef625f 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -140,9 +140,9 @@ device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.3 on end # Bridge to PCIe Ethernet chip - device pci 8.1 on # Bridge to Bus A + device ref iommu on end + device ref gpp_bridge_2 on end # Bridge to PCIe Ethernet chip + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -152,12 +152,12 @@ device pci 0.6 on end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 8.2 on # Bridge to Bus B + device ref internal_bridge_b on device pci 0.0 on end # AHCI device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.3 on # D14F3 bridge + device ref lpc_bridge on chip superio/smsc/sio1036 # optional debug card end end diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 0d0e829..57710c2 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -255,15 +255,15 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.2 on # GPP Bridge 1 - Wifi + device ref iommu on end + device ref gpp_bridge_1 on # Wifi chip drivers/wifi/generic register "wake" = "GEVENT_8" device pci 00.0 on end end end - device pci 1.3 on end # GPP Bridge 2 - SD - device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device ref gpp_bridge_2 on end # SD + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -353,7 +353,7 @@ device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 14.3 on # - D14F3 bridge + device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 on chip ec/google/chromeec/i2c_tunnel diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 8d0abad..1ddc763 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -248,16 +248,16 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.2 on end # IOMMU - device pci 1.2 on # GPP Bridge 1 - Wifi + device ref iommu on end + device ref gpp_bridge_1 on # Wifi chip drivers/wifi/generic register "wake" = "GEVENT_8" device pci 00.0 on end end end - device pci 1.3 on end # GPP Bridge 2 - SD - device pci 1.7 on end # GPP Bridge 6 - NVME - device pci 8.1 on # Internal GPP Bridge 0 to Bus A + device ref gpp_bridge_2 on end # SD + device ref gpp_bridge_6 on end # NVME + device ref internal_bridge_a on device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA device pci 0.2 on end # Crypto Coprocessor @@ -374,7 +374,7 @@ device pci 0.6 off end # HDA device pci 0.7 on end # non-Sensor Fusion Hub device end - device pci 14.3 on # - D14F3 bridge + device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 on chip ec/google/chromeec/i2c_tunnel diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 43a64b0d..7cadaf8 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -152,13 +152,13 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 1.3 on + device ref gpp_bridge_2 on chip drivers/generic/bayhub_lv2 register "enable_power_saving" = "1" device pci 00.0 on end end - end # GPP Bridge 2 - SD - device pci 8.1 on + end # SD + device ref internal_bridge_a on device pci 0.5 on chip drivers/amd/i2s_machine_dev register "hid" = ""AMDI1015"" @@ -200,7 +200,7 @@ end end # Audio end - device pci 14.3 on # - D14F3 bridge + device ref lpc_bridge on chip ec/google/chromeec device pnp 0c09.0 on chip ec/google/chromeec/i2c_tunnel diff --git a/util/mainboard/google/trembyle/template/overridetree.cb b/util/mainboard/google/trembyle/template/overridetree.cb index d09c942..52607d1 100644 --- a/util/mainboard/google/trembyle/template/overridetree.cb +++ b/util/mainboard/google/trembyle/template/overridetree.cb @@ -37,7 +37,7 @@ # See AMD 55570-B1 Table 13: PCI Device ID Assignments. device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 1.7 on end # GPP Bridge 6 - NVME + device ref gpp_bridge_6 on end # NVME end # domain device mmio 0xfedc4000 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/55103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f Gerrit-Change-Number: 55103 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: introduce and use chipset device tree
by Felix Held (Code Review) 31 May '21

31 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50626 to look at the new patch set (#6). Change subject: soc/amd/picasso: introduce and use chipset device tree ...................................................................... soc/amd/picasso: introduce and use chipset device tree The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/mandolin/variants/cereme/devicetree.cb M src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/soc/amd/picasso/Kconfig A src/soc/amd/picasso/chipset.cb M util/mainboard/google/trembyle/template/overridetree.cb 8 files changed, 50 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/50626/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/50626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Gerrit-Change-Number: 50626 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer:intel/common/block: Move mainboard api to tcss comm...
by Deepti Deshatty (Code Review) 31 May '21

31 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Paul Menzel, Sridhar Siricilla, Patrick Rudolph. Deepti Deshatty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54733 ) Change subject: mb/google/volteer:intel/common/block: Move mainboard api to tcss common block ...................................................................... Patch Set 3: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/54733/comment/9a06cf30_84cf81f1 PS2, Line 7: mb/google/volteer:intel/common/block: move api to tcss common block. > Please remove the dot/period at the end of the commit message summary. Ack https://review.coreboot.org/c/coreboot/+/54733/comment/16e741f3_7e27ca77 PS2, Line 9: change id 54090 > Please use the real change-id. Yes the change id is correct. File src/soc/intel/common/block/tcss/tcss.c: https://review.coreboot.org/c/coreboot/+/54733/comment/0b7151b1_9aa78b5e PS2, Line 17: extern struct chip_operations drivers_intel_pmc_mux_conn_ops; > In coreboot, we're trying to avoid having to add these `extern struct chip_operations .... […] Ack https://review.coreboot.org/c/coreboot/+/54733/comment/ac430c48_b3e30eb1 PS2, Line 344: const struct drivers_intel_pmc_mux_conn_config *get_mux_connector_config( : const struct device *mux, size_t port) : { : const struct drivers_intel_pmc_mux_conn_config *mux_config = NULL; : const struct device *connector; : const struct device_path conn_path[] = { : { .type = DEVICE_PATH_GENERIC, .generic.id = port, .generic.subid = 0}, : }; : : connector = find_dev_nested_path(mux->link_list, conn_path, : ARRAY_SIZE(conn_path)); : : if (connector && connector->chip_ops == &drivers_intel_pmc_mux_conn_ops) : mux_config = connector->chip_info; : : return mux_config; : } > Since we want to move the chip driver-specific code to `pmc_mux/conn/conn. […] Ack https://review.coreboot.org/c/coreboot/+/54733/comment/8e6a87eb_4ce4a747 PS2, Line 362: const struct device *get_pmc_mux(void) : { : const struct device *pmc; : const struct device *mux; : : pmc = pcidev_path_on_root(PCH_DEVFN_PMC); : if (!pmc || !pmc->link_list) { : printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__); : return NULL; : } : : mux = pmc->link_list->children; : return mux; : } > this function isn't needed, see following comment Ack https://review.coreboot.org/c/coreboot/+/54733/comment/bad9bb59_395b429a PS2, Line 377: { : static struct tcss_port_map port_map[MAX_TYPE_C_PORTS]; : const struct drivers_intel_pmc_mux_conn_config *mux_config; : const struct device *mux; : size_t active_ports = 0; : size_t port; : : mux = get_pmc_mux(); : : if (!mux || !mux->link_list) { : printk(BIOS_ERR, "%s: unable to find PMC mux device or its connector\n", : __func__); : return NULL; : } : : for (port = 0; port < MAX_TYPE_C_PORTS; port++) { : mux_config = get_mux_connector_config(mux, port); : : if (!mux_config) : continue; : : port_map[active_ports].usb2_port = mux_config->usb2_port_number; : port_map[active_ports].usb3_port = mux_config->usb3_port_number; : active_ports++; : } : : *num_ports = active_ports; : return port_map; : } > I am thinking this function now can look something more like: […] yes this looks simple, after verification, the 'conn_path' looks like below, need to add mux device to this. const struct device_path conn_path[] = { { .type = DEVICE_PATH_PCI, .pci.devfn = PCH_DEVFN_PMC }, {.type = DEVICE_PATH_GENERIC, .generic.id=0, .generic.subid=0 }, { .type = DEVICE_PATH_GENERIC, .generic.id = i }, }; Instead of above, i thought to make the 'conn_path' simple, by including the sub function get_pmc_mux(). Please comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/54733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7894363df4862f7cfe733d93e6160677fb8a9e31 Gerrit-Change-Number: 54733 Gerrit-PatchSet: 3 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 May 2021 17:36:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/mipi_camera: Add macros to increase code readability
by Paul Menzel (Code Review) 31 May '21

31 May '21

Attention is currently required from: Varshit B Pandya, Maulik V Vaghela, Sugnan Prabhu S, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55097 ) Change subject: drivers/intel/mipi_camera: Add macros to increase code readability ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/55097/comment/91e78d75_2fb0494a PS4, Line 10: Example CL:52013 I am not allowed to access this URL (404). https://review.coreboot.org/c/coreboot/+/55097/comment/07672670_0ffb8d0f PS4, Line 15: TEST=Build and check static.c for consistency You did this with the next commit, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/55097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4137e09c934bf06857ceedb933e616bed5070dd Gerrit-Change-Number: 55097 Gerrit-PatchSet: 4 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 31 May 2021 17:36:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021