coreboot-gerrit May 2021

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Change in coreboot[master]: util/kconfig: Uprev to Linux 5.3's kconfig
by Patrick Georgi (Code Review) 13 Jul '21

13 Jul '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37152 ) Change subject: util/kconfig: Uprev to Linux 5.3's kconfig ...................................................................... util/kconfig: Uprev to Linux 5.3's kconfig This was originally several commits that had to be squashed into one because the intermediate states weren't able to build coreboot: - one to remove everything that wasn't our own code, leaving only regex.[ch], toada.c, description.md and Makefile.inc - one to copy in Linux 5.3's scripts/kconfig and adapt Makefile.inc to make the original Makefile work again. TODO: - more commits that bring back our modifications, both directly in the code and as a diff in a patches/ subdirectory. Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/kconfig/Makefile M util/kconfig/Makefile.inc D util/kconfig/POTFILES.in D util/kconfig/check.sh M util/kconfig/conf.c M util/kconfig/confdata.c M util/kconfig/expr.c M util/kconfig/expr.h A util/kconfig/gconf-cfg.sh M util/kconfig/gconf.c M util/kconfig/images.c A util/kconfig/images.h D util/kconfig/kxgettext.c A util/kconfig/lexer.l M util/kconfig/list.h M util/kconfig/lkc.h M util/kconfig/lkc_proto.h D util/kconfig/lxdialog/.gitignore M util/kconfig/lxdialog/BIG.FAT.WARNING D util/kconfig/lxdialog/check-lxdialog.sh M util/kconfig/lxdialog/checklist.c M util/kconfig/lxdialog/dialog.h M util/kconfig/lxdialog/inputbox.c M util/kconfig/lxdialog/menubox.c M util/kconfig/lxdialog/textbox.c M util/kconfig/lxdialog/util.c M util/kconfig/lxdialog/yesno.c A util/kconfig/mconf-cfg.sh M util/kconfig/mconf.c M util/kconfig/menu.c A util/kconfig/merge_config.sh A util/kconfig/nconf-cfg.sh M util/kconfig/nconf.c M util/kconfig/nconf.gui.c M util/kconfig/nconf.h R util/kconfig/parser.y A util/kconfig/preprocess.c A util/kconfig/qconf-cfg.sh M util/kconfig/qconf.cc M util/kconfig/qconf.h A util/kconfig/streamline_config.pl M util/kconfig/symbol.c M util/kconfig/util.c D util/kconfig/zconf.gperf D util/kconfig/zconf.hash.c_shipped D util/kconfig/zconf.l D util/kconfig/zconf.lex.c_shipped D util/kconfig/zconf.tab.c_shipped 48 files changed, 4,250 insertions(+), 8,203 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/37152/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0e8fe4e9022b278f34ab113a433ef4d45e5c355 Gerrit-Change-Number: 37152 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 46

Change in coreboot[master]: cpu/intel/car/core2/cache_as_ram: Add x86_64 support
by Patrick Rudolph (Code Review) 07 Jul '21

07 Jul '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45823 ) Change subject: cpu/intel/car/core2/cache_as_ram: Add x86_64 support ...................................................................... cpu/intel/car/core2/cache_as_ram: Add x86_64 support Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/car/cache_as_ram_symbols.inc M src/cpu/intel/car/core2/cache_as_ram.S 2 files changed, 26 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/45823/1 diff --git a/src/cpu/intel/car/cache_as_ram_symbols.inc b/src/cpu/intel/car/cache_as_ram_symbols.inc index 857e039..c75b1e44 100644 --- a/src/cpu/intel/car/cache_as_ram_symbols.inc +++ b/src/cpu/intel/car/cache_as_ram_symbols.inc @@ -16,5 +16,13 @@ car_mtrr_mask: .uintptr_t _car_mtrr_mask +car_mtrr_size: +.uintptr_t _car_mtrr_size + car_mtrr_start: .uintptr_t _car_mtrr_start + +#if !CONFIG(NO_XIP_EARLY_STAGES) +xip_mtrr_mask: +.uintptr_t _xip_mtrr_mask +#endif diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 837394c..5d6994f 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -6,6 +6,8 @@ .global bootblock_pre_c_entry +#include <cpu/intel/car/cache_as_ram_symbols.inc> + .code32 _cache_as_ram_setup: @@ -91,7 +93,7 @@ /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr - movl $_car_mtrr_mask, %eax + movl car_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -118,8 +120,8 @@ /* Clear the cache memory region. This will also fill up the cache. */ cld xorl %eax, %eax - movl $_car_mtrr_start, %edi - movl $_car_mtrr_size, %ecx + movl car_mtrr_start, %edi + movl car_mtrr_size, %ecx shr $2, %ecx rep stosl @@ -133,12 +135,12 @@ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx movl $_program, %eax - andl $_xip_mtrr_mask, %eax + andl xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx rdmsr - movl $_xip_mtrr_mask, %eax + movl xip_mtrr_mask, %eax orl $MTRR_PHYS_MASK_VALID, %eax wrmsr @@ -156,6 +158,16 @@ andl $0xfffffff0, %esp subl $4, %esp +#if ENV_X86_64 + + #include <cpu/x86/64bit/entry64.inc> + + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else /* push TSC and BIST to stack */ movd %mm0, %eax pushl %eax /* BIST */ @@ -163,6 +175,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif before_c_entry: post_code(0x29) -- To view, visit https://review.coreboot.org/c/coreboot/+/45823 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27cdec5f112588b219f51112279b2dfbb05b6c97 Gerrit-Change-Number: 45823 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: ironlake: Add support for x86_64
by Patrick Rudolph (Code Review) 07 Jul '21

07 Jul '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45699 ) Change subject: ironlake: Add support for x86_64 ...................................................................... ironlake: Add support for x86_64 Allow to compile the experimental x86_64 code. Tested on Lenovo Thinkpad T410. Works without issues. Change-Id: I60f2fccba357cb5fb5d85feb4ee8d02abfe6bc7e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/microcode/microcode_asm.S M src/cpu/intel/model_2065x/Kconfig M src/cpu/x86/early_reset.S 3 files changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/45699/1 diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index f02351a..5a8b907 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -45,6 +45,7 @@ .section .text .global update_bsp_microcode +.code32 update_bsp_microcode: /* Keep return address */ diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 78cac30..19eeab0 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -3,12 +3,20 @@ if CPU_INTEL_MODEL_2065X +config ARCH_EXP_X86_64 + bool "Experimental 64bit support" + default n + config CPU_SPECIFIC_OPTIONS def_bool y - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_32 if !ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_32 if !ARCH_EXP_X86_64 + select ARCH_BOOTBLOCK_X86_64 if ARCH_EXP_X86_64 + select ARCH_VERSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_ROMSTAGE_X86_64 if ARCH_EXP_X86_64 + select ARCH_RAMSTAGE_X86_64 if ARCH_EXP_X86_64 select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S index 6ce9d52..c6d0703 100644 --- a/src/cpu/x86/early_reset.S +++ b/src/cpu/x86/early_reset.S @@ -9,6 +9,7 @@ .section .text .global check_mtrr +.code32 check_mtrr: /* Use the MTRR default type MSR as a proxy for detecting INIT#. -- To view, visit https://review.coreboot.org/c/coreboot/+/45699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60f2fccba357cb5fb5d85feb4ee8d02abfe6bc7e Gerrit-Change-Number: 45699 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: arch/x86: Use ENV_X86_64 instead of _x86_64_
by Patrick Rudolph (Code Review) 06 Jul '21

06 Jul '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44867 ) Change subject: arch/x86: Use ENV_X86_64 instead of _x86_64_ ...................................................................... arch/x86: Use ENV_X86_64 instead of _x86_64_ Untested. Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/assembly_entry.S M src/arch/x86/boot.c M src/arch/x86/c_exit.S M src/arch/x86/c_start.S M src/arch/x86/cpu.c M src/arch/x86/cpu_common.c M src/arch/x86/exception.c M src/arch/x86/exit_car.S M src/arch/x86/gdt_init.S M src/arch/x86/idt.S M src/arch/x86/include/arch/cpu.h M src/arch/x86/include/arch/registers.h M src/arch/x86/memcpy.c M src/arch/x86/wakeup.S M src/cpu/qemu-x86/cache_as_ram_bootblock.S M src/cpu/x86/64bit/entry64.inc M src/cpu/x86/lapic/lapic_cpu_init.c M src/cpu/x86/smm/smm_stub.S M src/cpu/x86/smm/smmhandler.S M src/include/assert.h M src/include/cpu/x86/cr.h M src/soc/intel/denverton_ns/soc_util.c 22 files changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/44867/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 31670c2..6e73027 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -15,7 +15,7 @@ #define _STACK_TOP _ecar_stack #endif -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -26,7 +26,7 @@ _start: /* Migrate GDT to this text segment */ -#ifdef __x86_64__ +#if ENV_X86_64 call gdt_init64 #else call gdt_init diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index 777a0b7..31e7cee 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -21,14 +21,14 @@ void arch_prog_run(struct prog *prog) { -#if ENV_RAMSTAGE && defined(__x86_64__) +#if ENV_RAMSTAGE && ENV_X86_64 const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog)); const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog)); /* On x86 coreboot payloads expect to be called in protected mode */ protected_mode_jump(entry, arg); #else -#ifdef __x86_64__ +#if ENV_X86_64 void (*doit)(void *arg); #else /* Ensure the argument is pushed on the stack. */ diff --git a/src/arch/x86/c_exit.S b/src/arch/x86/c_exit.S index e5b9bf8..bb1df28 100644 --- a/src/arch/x86/c_exit.S +++ b/src/arch/x86/c_exit.S @@ -5,7 +5,7 @@ #include <cpu/x86/cr.h> -#ifdef __x86_64__ +#if ENV_X86_64 /* * Functions to handle mode switches from long mode to protected diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index c46a45c..47d6597 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -22,7 +22,7 @@ #endif .section ".text._start", "ax", @progbits -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -31,7 +31,7 @@ _start: cli lgdt %cs:gdtaddr -#ifndef __x86_64__ +#if ENV_X86_32 ljmp $RAM_CODE_SEG, $1f #endif 1: movl $RAM_DATA_SEG, %eax @@ -40,7 +40,7 @@ movl %eax, %ss movl %eax, %fs movl %eax, %gs -#ifdef __x86_64__ +#if ENV_X86_64 mov $RAM_CODE_SEG64, %ecx call SetCodeSelector #endif @@ -49,7 +49,7 @@ cld -#ifdef __x86_64__ +#if ENV_X86_64 mov %rdi, _cbmem_top_ptr #else /* The return argument is at 0(%esp), the calling argument at 4(%esp) */ @@ -110,7 +110,7 @@ .globl gdb_stub_breakpoint gdb_stub_breakpoint: -#ifdef __x86_64__ +#if ENV_X86_64 pop %rax /* Return address */ pushfl push %cs @@ -132,7 +132,7 @@ gdtaddr: .word gdt_end - gdt - 1 -#ifdef __x86_64__ +#if ENV_X86_64 .quad gdt #else .long gdt /* we know the offset */ @@ -169,7 +169,7 @@ /* selgdt 0x18, flat data segment */ .word 0xffff, 0x0000 -#ifdef __x86_64__ +#if ENV_X86_64 .byte 0x00, 0x92, 0xcf, 0x00 #else .byte 0x00, 0x93, 0xcf, 0x00 @@ -203,7 +203,7 @@ * limit */ -#ifdef __x86_64__ +#if ENV_X86_64 /* selgdt 0x48, flat x64 code segment */ .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0xaf, 0x00 @@ -211,7 +211,7 @@ gdt_end: .section ".text._start", "ax", @progbits -#ifdef __x86_64__ +#if ENV_X86_64 SetCodeSelector: # save rsp because iret will align it to a 16 byte boundary mov %rsp, %rdx diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index d054cfe..d44bd2f 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -14,7 +14,7 @@ #include <device/device.h> #include <smp/spinlock.h> -#ifndef __x86_64__ +#if ENV_X86_32 /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -137,7 +137,7 @@ vendor_name[0] = '\0'; /* Unset */ -#ifndef __x86_64__ +#if ENV_X86_32 /* Find the id and vendor_name */ if (!cpu_have_cpuid()) { /* Its a 486 if we can modify the AC flag */ diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 07de155..77d08c41 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -2,7 +2,7 @@ #include <cpu/cpu.h> -#ifndef __x86_64__ +#if ENV_X86_32 /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index f10c7bf..6c519c3 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -491,7 +491,7 @@ logical_processor = cpu_index(); #endif u8 *code; -#ifdef __x86_64__ +#if ENV_X86_64 #define MDUMP_SIZE 0x100 printk(BIOS_EMERG, "CPU Index %d - APIC %d Unexpected Exception:\n" diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S index dc356b2..db36821 100644 --- a/src/arch/x86/exit_car.S +++ b/src/arch/x86/exit_car.S @@ -11,7 +11,7 @@ .long 0 .long 0 -#if defined(__x86_64__) +#if ENV_X86_64 .code64 .macro pop_eax_edx pop %rax @@ -42,13 +42,13 @@ is expected to be implemented in assembly. */ /* Migrate GDT to this text segment */ -#if defined(__x86_64__) +#if ENV_X86_64 call gdt_init64 #else call gdt_init #endif -#ifdef __x86_64__ +#if ENV_X86_64 mov %rdi, _cbmem_top_ptr #else /* The return argument is at 0(%esp), the calling argument at 4(%esp) */ @@ -67,7 +67,7 @@ call chipset_teardown_car /* Enable caching if not already enabled. */ -#ifdef __x86_64__ +#if ENV_X86_64 mov %cr0, %rax and $(~(CR0_CD | CR0_NW)), %eax mov %rax, %cr0 @@ -102,7 +102,7 @@ /* Need to align stack to 16 bytes at the call instruction. Therefore account for the 1 push. */ andl $0xfffffff0, %esp -#if defined(__x86_64__) +#if ENV_X86_64 mov %rbp, %rdi #else sub $12, %esp diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S index 1558ac6..287f17b 100644 --- a/src/arch/x86/gdt_init.S +++ b/src/arch/x86/gdt_init.S @@ -15,7 +15,7 @@ .word gdt_end - gdt -1 /* compute the table limit */ .long gdt /* we know the offset */ -#ifdef __x86_64__ +#if ENV_X86_64 .code64 .section ".text._gdt64_", "ax", @progbits .globl gdt_init64 diff --git a/src/arch/x86/idt.S b/src/arch/x86/idt.S index 6807056..d763b9e 100644 --- a/src/arch/x86/idt.S +++ b/src/arch/x86/idt.S @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ .section ".text._idt", "ax", @progbits -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -109,7 +109,7 @@ .global int_hand int_hand: -#ifdef __x86_64__ +#if ENV_X86_64 /* At this point, on x86-64, on the stack there is: * 0(%rsp) vector * 8(%rsp) error code diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index b622465..e523fc0 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -236,7 +236,7 @@ { struct cpu_info *ci; __asm__( -#ifdef __x86_64__ +#if ENV_X86_64 "and %%rsp,%0; " "or %2, %0 " #else diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 5f8f9be..7043cd1 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -42,7 +42,7 @@ uint64_t r##A; \ } __packed -#ifdef __ARCH_x86_64__ +#if ENV_X86_64 struct eregs { QUAD_DOWNTO8(a); QUAD_DOWNTO8(c); diff --git a/src/arch/x86/memcpy.c b/src/arch/x86/memcpy.c index 1cfdf89..93002cd 100644 --- a/src/arch/x86/memcpy.c +++ b/src/arch/x86/memcpy.c @@ -15,7 +15,7 @@ #endif asm volatile( -#ifdef __x86_64__ +#if ENV_X86_64 "rep ; movsd\n\t" "mov %4,%%rcx\n\t" #else diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index ae2efe0..dc9510b 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -6,7 +6,7 @@ /* CR0 bits */ #define PE (1 << 0) -#ifdef __x86_64__ +#if ENV_X86_64 .code64 #else .code32 @@ -14,7 +14,7 @@ .globl __wakeup __wakeup: -#ifdef __x86_64__ +#if ENV_X86_64 xor %rax,%rax mov %ss, %ax push %rax diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 415ed24..4489d2c 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -28,7 +28,7 @@ and $0xfffffff0, %esp /* Restore the BIST result and timestamps. */ -#if defined(__x86_64__) +#if ENV_X86_64 movd %mm2, %rdi shld %rdi, 32 movd %mm1, %rsi diff --git a/src/cpu/x86/64bit/entry64.inc b/src/cpu/x86/64bit/entry64.inc index 65c0fdc..5049169 100644 --- a/src/cpu/x86/64bit/entry64.inc +++ b/src/cpu/x86/64bit/entry64.inc @@ -9,7 +9,7 @@ * Clobbers: eax, ecx, edx */ -#if defined(__x86_64__) +#if ENV_X86_64 .code32 #if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0 #error pagetables must be 4KiB aligned! diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index f89d9e3..342c86d 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -39,7 +39,7 @@ static inline void setup_secondary_gdt(void) { u16 *gdt_limit; -#ifdef __x86_64__ +#if ENV_X86_64 u64 *gdt_base; #else u32 *gdt_base; diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 11ea9a7..dd902d7 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -178,7 +178,7 @@ /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp -#ifdef __x86_64__ +#if ENV_X86_64 mov %ecx, %edi /* Backup IA32_EFER. Preserves ebx. */ movl $(IA32_EFER), %ecx @@ -197,7 +197,7 @@ * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; * c_handler(&arg) */ -#ifdef __x86_64__ +#if ENV_X86_64 push %rbx /* uintptr_t *canary */ push $(smm_runtime) push %rcx /* size_t cpu */ diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 340840f..bb91cb1 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -43,7 +43,7 @@ #define SMM_HANDLER_OFFSET 0x0000 -#if defined(__x86_64__) +#if ENV_X86_64 .bss ia32efer_backup_eax: .long @@ -169,7 +169,7 @@ movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ subl %ebp, %ebx /* subtract core X offset */ -#if defined(__x86_64__) +#if ENV_X86_64 /* Backup IA32_EFER. Preserves ebx. */ movl $(IA32_EFER), %ecx rdmsr @@ -189,7 +189,7 @@ /* Call C handler */ call smi_handler -#if defined(__x86_64__) +#if ENV_X86_64 /* * The only reason to go back to protected mode is that RSM doesn't restore * MSR registers and MSR IA32_EFER was modified by entering long mode. diff --git a/src/include/assert.h b/src/include/assert.h index 944c677..27d7309 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -80,7 +80,7 @@ *(type *)(uintptr_t)0; \ }) -#ifdef __x86_64__ +#if ENV_X86_64 #define pointer_to_uint32_safe(x) ({ \ if ((uintptr_t)(x) > 0xffffffffUL) \ die("Cast from pointer to uint32_t overflows"); \ diff --git a/src/include/cpu/x86/cr.h b/src/include/cpu/x86/cr.h index 3508505a..c70f35c 100644 --- a/src/include/cpu/x86/cr.h +++ b/src/include/cpu/x86/cr.h @@ -9,7 +9,7 @@ #define COMPILER_BARRIER "memory" -#ifdef __x86_64__ +#if ENV_X86_64 #define CRx_TYPE uint64_t #define CRx_IN "q" #define CRx_RET "=q" diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index d5b9b34..b4c707d 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -274,7 +274,7 @@ unsigned long d0, d1, d2; asm volatile( -#ifdef __x86_64__ +#if ENV_X86_64 "rep ; movsd\n\t" "mov %4,%%rcx\n\t" #else -- To view, visit https://review.coreboot.org/c/coreboot/+/44867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I152483d24af0512c0ee4fbbe8931b7312e487ac6 Gerrit-Change-Number: 44867 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 7

Change in coreboot[master]: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Inte...
by Lean Sheng Tan (Code Review) 25 Jun '21

25 Jun '21

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34159 ) Change subject: mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP ...................................................................... mb/intel/coffeelake_rvp: Fix display issues on CFL-H, CFL-S, WHL Intel RVP This patch fixes display issues on both CFL-H & S, and WHL Intel RVP platform where display are not showing up in UEFI shell, by configuring DDi ports in device tree. This patches also fixes no eDP display observed in UEFI shell on UEFI Payload. Root cause is eDP requires minimum delay between GPIO programming and eDP initialisation, which was not sufficient during FSP initialisation which causes VBT to return error during eDP init. This issue is fixed by programming eDP GPIO's in bootblock stage and skipping FSP GPIO programming by setting 'DdiPortEdp=0' in devicetree. TEST= verified eDP display, HDMI and DP functionalities on CFL-H, CFL-S & WHL Intel RVP platforms. Signed-off-by: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c --- M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb 4 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34159/1 diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index ec8f58b..aa009bb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -593,6 +593,19 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + /* I4 : EDP_HPD */ + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + + /* F19 : EDP_VDDEN */ + PAD_CFG_NF(GPP_F19, NONE, PLTRST, NF1), + + /* F20 : EDP_BKLTEN */ + PAD_CFG_NF(GPP_F20, NONE, PLTRST, NF1), + + /* F21 : EDP_BKLTCTL */ + PAD_CFG_NF(GPP_F21, NONE, PLTRST, NF1), + #endif }; diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb index 9648ac3..40da8eb 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_h/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC5)" register "usb2_ports[1]" = "USB2_PORT_MID(OC6)" register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb index 126cab0..6ee52a4 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cfl_s/devicetree.cb @@ -9,6 +9,19 @@ register "RMT" = "1" register "ScsEmmcHs400Enabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "0" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "0" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC4)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb index 429d5da..e824ac9 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_u/devicetree.cb @@ -9,6 +9,19 @@ register "ScsEmmcHs400Enabled" = "1" register "HeciEnabled" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "0" + register "DdiPortFHpd" = "0" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "0" + # Enable eDP device register "DdiPortEdp" = "1" # Enable HPD for DDI ports B/C/D/F -- To view, visit https://review.coreboot.org/c/coreboot/+/34159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee87649492f7803210f9a35cd46b4f9826cbc93c Gerrit-Change-Number: 34159 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: [WIP]soc/intel/car: Add support for bootguard CAR
by Arthur Heymans (Code Review) 23 Jun '21

23 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36682 ) Change subject: [WIP]soc/intel/car: Add support for bootguard CAR ...................................................................... [WIP]soc/intel/car: Add support for bootguard CAR Bootguard sets up CAR on its own so the only thing needed is to find a free MTRR for our own CAR region. Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/36682/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d5f5081..3ae4829 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -23,11 +23,20 @@ #include <rules.h> #include <intelblocks/msr.h> +#define BOOTGUARD_MSR 0x13a + .global bootblock_pre_c_entry bootblock_pre_c_entry: post_code(0x20) +/* Bootguard setups up it's own CAR and needs separate handling */ +check_boot_guard: + movl $BOOTGUARD_MSR, %ecx + rdmsr + andl $1, %eax + jnz bootguard_car_setup + movl $no_reset, %esp /* return address */ jmp check_mtrr /* Check if CPU properly reset */ @@ -456,3 +465,60 @@ jmp car_init_done #endif + +bootguard_car_setup: + /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + */ + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + /* Figure put how many MTRRs we have */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + + /* Find a free variable MTRR */ + movl $MTRR_PHYS_MASK(0), %ecx +test_is_free_mtrr: + rdmsr + test $MTRR_PHYS_MASK_VALID, %eax + jz found_free_mtrr + addl $2, %ecx + dec %ebx + jnz test_is_free_mtrr + + jmp .halt_forever + +found_free_mtrr: + /* Assume one MTRR is enough for now */ + decl %ecx /* MTRR_PHYS_BASE */ + movl $CONFIG_DCACHE_RAM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax + xorl %edx, %edx + wrmsr + + /* Configure the MTRR mask for the size region */ + incl %ecx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ + decl %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + +clear_cache_region: + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + jmp car_init_done -- To view, visit https://review.coreboot.org/c/coreboot/+/36682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifac5267f8f4b820a61519fb4a497e2ce7075cc40 Gerrit-Change-Number: 36682 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

12 62

Change in coreboot[master]: soc/intel/common/cache_as_ram.S: Add macro to clear CAR
by Arthur Heymans (Code Review) 22 Jun '21

22 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37191 ) Change subject: soc/intel/common/cache_as_ram.S: Add macro to clear CAR ...................................................................... soc/intel/common/cache_as_ram.S: Add macro to clear CAR Add a macro to clear CAR which is replicated 3 times in this code. Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 15 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37191/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d1ae6ca..6a0728d 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -48,6 +48,17 @@ 3: .endm + .macro clear_car + /* Clear the cache memory region. This will also fill up the cache */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + .endm + + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -256,13 +267,7 @@ post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -353,13 +358,7 @@ post_code(0x26) - /* Clear the cache memory region. This will also fill up the cache */ - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car post_code(0x27) @@ -462,12 +461,8 @@ xorl %edx, %edx wrmsr - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - xor %eax, %eax - cld - rep stosl + clear_car + /* * Set IA32_PQR_ASSOC = 0x01 * At this stage we apply LLC_WAY_MASK_1 to the cache. -- To view, visit https://review.coreboot.org/c/coreboot/+/37191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec28e3f393c4fe222bfb0d5358f815691ec199ae Gerrit-Change-Number: 37191 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR
by Arthur Heymans (Code Review) 22 Jun '21

22 Jun '21

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37190 ) Change subject: soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR ...................................................................... soc/intel/common/cache_as_ram.S: Add macro to find a free MTRR This adds a macro to find an available MTRR(s) to set up CAR. This added complexity is not required on bootpaths without bootguard but with bootguard MTRR's have already been set up by the ACM so we need to figure out at runtime which ones are available. Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 43 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/37190/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 0992d85..d1ae6ca 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -23,6 +23,31 @@ #include <rules.h> #include <intelblocks/msr.h> + /* puts 1 to eax if not found, 0 if found */ + .macro find_free_mtrr + /* Figure put how many MTRRs we have */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + + /* Find a free variable MTRR */ + movl $MTRR_PHYS_MASK(0), %ecx +1: + rdmsr + test $MTRR_PHYS_MASK_VALID, %eax + jz 2f + addl $2, %ecx + dec %ebx + jnz 1b + + movl $1, %eax + jmp 3f +2: + movl $0, %eax + decl %ecx +3: + .endm + .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -93,15 +118,19 @@ post_code(0x24) #if ((CONFIG_DCACHE_RAM_SIZE & (CONFIG_DCACHE_RAM_SIZE - 1)) == 0) + find_free_mtrr + cmp $1, %eax + jne 1f + jmp .halt_forever +1: /* Configure CAR region as write-back (WB) */ - mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr /* Configure the MTRR mask for the size region */ - mov $MTRR_PHYS_MASK(0), %ecx + inc %ecx mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ dec %eax not %eax @@ -109,14 +138,18 @@ movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ wrmsr #elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */ + find_free_mtrr + cmp $1, %eax + jne 1f + jmp .halt_forever +1: /* Configure CAR region as write-back (WB) */ - mov $MTRR_PHYS_BASE(0), %ecx mov $CONFIG_DCACHE_RAM_BASE, %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr - mov $MTRR_PHYS_MASK(0), %ecx + incl %ecx mov $(512 * KiB), %eax /* size mask */ dec %eax not %eax @@ -124,13 +157,17 @@ movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ wrmsr - mov $MTRR_PHYS_BASE(1), %ecx + find_free_mtrr + cmp $1, %eax + jne 1f + jmp .halt_forever +1: mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax or $MTRR_TYPE_WRBACK, %eax xor %edx,%edx wrmsr - mov $MTRR_PHYS_MASK(1), %ecx + incl %ecx mov $(256 * KiB), %eax /* size mask */ dec %eax not %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/37190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5442c75464cfb2b3611c63a472c8ee521c014d Gerrit-Change-Number: 37190 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/google/wilco: Fix comment about enclosure type
by Kyösti Mälkki (Code Review) 21 Jun '21

21 Jun '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42141 ) Change subject: ec/google/wilco: Fix comment about enclosure type ...................................................................... ec/google/wilco: Fix comment about enclosure type SYSTEM_TYPE_CONVERTIBLE is not valid SMBIOS enclosure type, but selecting it implies SMBIOS_ENCLOSURE_CONVERTIBLE. Change-Id: Ib658af7b80586428b22f08a738964637e1fbd17a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/ec/google/wilco/acpi/vbtn.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42141/1 diff --git a/src/ec/google/wilco/acpi/vbtn.asl b/src/ec/google/wilco/acpi/vbtn.asl index 6227367..bc9dd34 100644 --- a/src/ec/google/wilco/acpi/vbtn.asl +++ b/src/ec/google/wilco/acpi/vbtn.asl @@ -5,7 +5,7 @@ * the Linux kernel at drivers/platform/x86/intel-vbtn.c * * For tablet/laptop and dock/undock events to work the board must - * select SYSTEM_TYPE_CONVERTIBLE for the SMBIOS enclosure type to + * have SMBIOS_ENCLOSURE_CONVERTIBLE for the SMBIOS enclosure type to * indicate the device is a convertible. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib658af7b80586428b22f08a738964637e1fbd17a Gerrit-Change-Number: 42141 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] nb/intel/haswell/pcie.c: Add some ASPM steps
by Angel Pons (Code Review) 20 Jun '21

20 Jun '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47223 ) Change subject: [WIP] nb/intel/haswell/pcie.c: Add some ASPM steps ...................................................................... [WIP] nb/intel/haswell/pcie.c: Add some ASPM steps Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/pcie.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/47223/1 diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c index d9e77a7..6eba75e 100644 --- a/src/northbridge/intel/haswell/pcie.c +++ b/src/northbridge/intel/haswell/pcie.c @@ -5,6 +5,7 @@ #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <assert.h> static void pcie_disable(struct device *dev) @@ -13,6 +14,17 @@ dev->enabled = 0; } +static void pcie_init(struct device *dev) +{ + /* Enable support for L0s and L1 */ + pci_or_config32(dev, 0xac, 3 << 10); + + pci_and_config32(dev, 0x200, ~(3 << 26)); + + /* Other fields in the register must not be changed while writing this */ + pci_or_config16(dev, 0x258, 1 << 2); +} + #if CONFIG(HAVE_ACPI_TABLES) static const char *pcie_acpi_name(const struct device *dev) { @@ -54,7 +66,7 @@ .scan_bus = pciexp_scan_bridge, .reset_bus = pci_bus_reset, .disable = pcie_disable, - .init = pci_dev_init, + .init = pcie_init, .ops_pci = &pci_dev_ops_pci, #if CONFIG(HAVE_ACPI_TABLES) .acpi_name = pcie_acpi_name, -- To view, visit https://review.coreboot.org/c/coreboot/+/47223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dcdd4ca431c2ae1e62f2719c376d8bdef3054bd Gerrit-Change-Number: 47223 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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