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Change subject: console: CONSOLE_SPI_FLASH depends on BOOT_DEVICE_SPI_FLASH
......................................................................
Patch Set 2: Code-Review+2
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52792 )
Change subject: sb/intel/{i82371eb/i82801dx}: select BOOT_DEVICE_NOT_SPI_FLASH
......................................................................
Patch Set 2: Code-Review+2
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52748 )
Change subject: soc/amd/picasso/dmi.c: Fix builds for boards without Google EC
......................................................................
soc/amd/picasso/dmi.c: Fix builds for boards without Google EC
For CRBs without Google EC with CONFIG_CHROMEOS=y we will get a build
error as google_chromeec_cbi_get_dram_part_num() is not defined. Use
EC_GOOGLE_CHROMEEC instead of CHROMEOS to gate the call.
BUG=b:184124605
Change-Id: I2b200f4fb11513c6fc17a2f0af3e12e5a3e3e5a1
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52748
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Rob Barnes <robbarnes(a)google.com>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/picasso/dmi.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
Raul Rangel: Looks good to me, approved
Rob Barnes: Looks good to me, but someone else must approve
diff --git a/src/soc/amd/picasso/dmi.c b/src/soc/amd/picasso/dmi.c
index 1133670..69928ad 100644
--- a/src/soc/amd/picasso/dmi.c
+++ b/src/soc/amd/picasso/dmi.c
@@ -158,7 +158,7 @@
}
printk(BIOS_DEBUG, "AMD_FSP_DMI_HOB found\n");
- if (CONFIG(CHROMEOS)) {
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
/* Prefer DRAM part number from CBI. */
if (google_chromeec_cbi_get_dram_part_num(
cbi_part_number, sizeof(cbi_part_number)) == 0) {
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51795 )
Change subject: soc/intel/alderlake: Enable HWP CPPC support in CB
......................................................................
soc/intel/alderlake: Enable HWP CPPC support in CB
Kconfig change which enables the hwp cppc acpi support is to get the
maximum performance of each CPU to check and enable Intel Turbo Boost
Max Technology.
BUG=none
BRANCH=none
TEST=check GCPC and CPC generated in acpi tables for each CPU
Change-Id: I5d93774e8025466f1911cf77459910fe872bfcc8
Signed-off-by: ravindr1 <ravindra(a)intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51795
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
Ravindra: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 2efe760..7480a41 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -47,6 +47,7 @@
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
+ select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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