coreboot-gerrit May 2021

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Change in coreboot[master]: DO-NOT-SUBMIT: MT8195 Cherry review ToT
by Rex-BC Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Rex-BC Chen, Yidi Lin. Rex-BC Chen has uploaded a new patch set (#37) to the change originally created by Yidi Lin. ( https://review.coreboot.org/c/coreboot/+/52260 ) Change subject: DO-NOT-SUBMIT: MT8195 Cherry review ToT ...................................................................... DO-NOT-SUBMIT: MT8195 Cherry review ToT Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs M README.md 5 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/52260/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/52260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ed96b245bbb52501e9b7d6b89ed42468f505ab0 Gerrit-Change-Number: 52260 Gerrit-PatchSet: 37 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Joel Kitching <kitching(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/puff/var/dooly: enable touchscreen wakeup
by Tony Huang (Code Review) 03 May '21

03 May '21

Attention is currently required from: Sam McNally, Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Keith Tzeng, Wisley Chen. Hello Sam McNally, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Edward O'Callaghan, Keith Tzeng, Wisley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52725 to look at the new patch set (#8). Change subject: mb/google/puff/var/dooly: enable touchscreen wakeup ...................................................................... mb/google/puff/var/dooly: enable touchscreen wakeup Follow touchpad to set interrupt gpio to PAD_CFG_GPI_IRQ_WAKE. Add fake touchscreen enable_pin GPP_D9 to ensure meet power sequence T11 in spec v0.8. BUG=b:186070097 BRANCH=puff TEST=Build and make sure TS works to wakeup suspend/resume. Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/gpio.c M src/mainboard/google/hatch/variants/dooly/overridetree.cb 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/52725/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/52725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd Gerrit-Change-Number: 52725 Gerrit-PatchSet: 8 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: add pmif/spmi/pmic init in romstage
by Hung-Te Lin (Code Review) 03 May '21

03 May '21

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu, Yidi Lin. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52849 ) Change subject: mb/google/cherry: add pmif/spmi/pmic init in romstage ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: src/mainboard/google/cherry/romstage.c:6:10: fatal error: soc/pmif.h: No such file or directory #include <soc/pmif.h> ^~~~~~~~~~~~ compilation terminated. -- To view, visit https://review.coreboot.org/c/coreboot/+/52849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eeddb44b5495d05602c995a6103a56b09cf126a Gerrit-Change-Number: 52849 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Comment-Date: Mon, 03 May 2021 08:50:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: add pmif/spmi/pmic driver
by Rex-BC Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52668 ) Change subject: soc/mediatek/mt8195: add pmif/spmi/pmic driver ...................................................................... Patch Set 4: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52668/comment/a839acb5_392460d1 PS3, Line 2: henryc.chen > If you used *Henry Chen*, that’d be great: […] Done https://review.coreboot.org/c/coreboot/+/52668/comment/d978e96c_642edfa3 PS3, Line 10: and spi, so we add pmif driver to control pmics. > This change seems to include firmware (encoded in header files). […] Ack https://review.coreboot.org/c/coreboot/+/52668/comment/89049ba2_7bca2834 PS3, Line 11: > 1. Please document the datasheet name and revision. […] Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. https://review.coreboot.org/c/coreboot/+/52668/comment/93f9f545_52ccaaa5 PS3, Line 12: henryc.chen > Dito. Done Patchset: PS3: > We generally prefer to have mainboard and SoC level code in separate commits. […] mb patch: https://review.coreboot.org/c/coreboot/+/52849/1 File src/soc/mediatek/mt8195/pmif_clk.c: https://review.coreboot.org/c/coreboot/+/52668/comment/bedc335b_b8e26491 PS3, Line 108: if (diff_by_min < diff_by_max) { : cal_result = min; : current_val = pmif_get_ulposc_freq_mhz(min); : } else { : cal_result = max; : current_val = pmif_get_ulposc_freq_mhz(max); : } > Maybe: […] Done https://review.coreboot.org/c/coreboot/+/52668/comment/17db89d9_35dce1a2 PS3, Line 119: printk(BIOS_ERR, "[%s] calibration fail: %dM\n", __func__, current_val); > Please also print out `CAL_TOL_RATE` and `target_val`. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Gerrit-Change-Number: 52668 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 03 May 2021 08:41:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: add pmif/spmi/pmic init in romstage
by Rex-BC Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Yidi Lin. Hello Yidi Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52849 to review the following change. Change subject: mb/google/cherry: add pmif/spmi/pmic init in romstage ...................................................................... mb/google/cherry: add pmif/spmi/pmic init in romstage Signed-off-by: Henry Chen <henryc.chen(a)mediatek.com> Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I2eeddb44b5495d05602c995a6103a56b09cf126a --- M src/mainboard/google/cherry/Makefile.inc A src/mainboard/google/cherry/romstage.c 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/52849/1 diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc index ada29aa..4831a39 100644 --- a/src/mainboard/google/cherry/Makefile.inc +++ b/src/mainboard/google/cherry/Makefile.inc @@ -7,6 +7,7 @@ romstage-y += memlayout.ld romstage-y += chromeos.c +romstage-y += romstage.c ramstage-y += memlayout.ld ramstage-y += chromeos.c diff --git a/src/mainboard/google/cherry/romstage.c b/src/mainboard/google/cherry/romstage.c new file mode 100644 index 0000000..cba5995 --- /dev/null +++ b/src/mainboard/google/cherry/romstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/stages.h> +#include <soc/mt6315.h> +#include <soc/mt6359p.h> +#include <soc/pmif.h> + +void platform_romstage_main(void) +{ + mtk_pmif_init(); + mt6359p_init(); + mt6315_init(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eeddb44b5495d05602c995a6103a56b09cf126a Gerrit-Change-Number: 52849 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: add pmif/spmi/pmic driver
by Rex-BC Chen (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52668 to look at the new patch set (#4). Change subject: soc/mediatek/mt8195: add pmif/spmi/pmic driver ...................................................................... soc/mediatek/mt8195: add pmif/spmi/pmic driver MT8195 also uses mt6359p so we can reuse most drivers. The only differences are IO configuaration, clock setting, and PMIC internal setting related to soc. Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Signed-off-by: Henry Chen <henryc.chen(a)mediatek.com> Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/pmif_spmi.h M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/include/soc/addressmap.h A src/soc/mediatek/mt8195/include/soc/iocfg.h A src/soc/mediatek/mt8195/include/soc/pmif.h A src/soc/mediatek/mt8195/mt6315.c A src/soc/mediatek/mt8195/mt6359p.c A src/soc/mediatek/mt8195/pmif_clk.c A src/soc/mediatek/mt8195/pmif_spi.c A src/soc/mediatek/mt8195/pmif_spmi.c 10 files changed, 927 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/52668/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Gerrit-Change-Number: 52668 Gerrit-PatchSet: 4 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/i2c/generic: Set S0W to D3hot for wake device
by Edward O'Callaghan (Code Review) 03 May '21

03 May '21

Attention is currently required from: Furquan Shaikh, Tony Huang, Keith Tzeng, Wisley Chen. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52847 ) Change subject: drivers/i2c/generic: Set S0W to D3hot for wake device ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Gerrit-Change-Number: 52847 Gerrit-PatchSet: 4 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 May 2021 08:14:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO
by Maulik V Vaghela (Code Review) 03 May '21

03 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52783 ) Change subject: soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/52783/comment/2ac48aac_33c3b435 PS4, Line 383: #define GPP_E9 309 : #define GPP_E10 309 > duplicate Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d Gerrit-Change-Number: 52783 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 03 May 2021 07:58:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO
by Maulik V Vaghela (Code Review) 03 May '21

03 May '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela. Hello Bora Guvendik, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Bernardo Perez Priego, Ronak Kanabar, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52783 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO ...................................................................... soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO Adding GPIO definition for community 3 which is CPU reserved GPIO used by CPU side PCIe root ports. We did not have this definition since FSP used to program this GPIOs. Now, instead of FSP,coreboot programs CPU PCIe GPIOs for CLKSRC and lanes to put GPIOs in native mode. Thus adding definition of this virtual GPIOs in this CL. BUG=None BRANCH=None TEST=Check if correct registers are being programmed Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/include/soc/gpio_defs.h M src/soc/intel/alderlake/include/soc/gpio_soc_defs.h 3 files changed, 237 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/52783/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d Gerrit-Change-Number: 52783 Gerrit-PatchSet: 5 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 reg
by Maulik V Vaghela (Code Review) 03 May '21

03 May '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52782 ) Change subject: soc/intel/common/block: Add definition for NAF_VWE bit for PAD_CFG0 reg ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/common/block/include/intelblocks/gpio_defs.h: https://review.coreboot.org/c/coreboot/+/52782/comment/aa29133b_74334ef4 PS3, Line 38: PAD_CFG0_NAFVWE_ENABLE > Is this applicable to more than just ADL? Yes Tim...It's common definition between multiple platforms...Like it's applicable for TGL also. https://review.coreboot.org/c/coreboot/+/52782/comment/de3c5c41_5087ea3d PS3, Line 224: PAD_IOSSTATE(TxLASTRxE) > Is this always required when selecting […] I have tried to maintain same definition as PAD_CFG_NF for this. We need to set IOSTATE as 0x00 for NF and since we want to set NAF_VWE bit with Native function only, I have maintain same definition as PAD_CFG_NF and added this BIT for DW0 -- To view, visit https://review.coreboot.org/c/coreboot/+/52782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I732e68b413eb01b8ae1a4927836762c8875b73d2 Gerrit-Change-Number: 52782 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 03 May 2021 07:52:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit May 2021