coreboot-gerrit May 2021

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Change in coreboot[master]: HACK: soc/mediatek: Add function to raise the big CPU frequency
by Yidi Lin (Code Review) 03 May '21

03 May '21

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46410 to review the following change. Change subject: HACK: soc/mediatek: Add function to raise the big CPU frequency ...................................................................... HACK: soc/mediatek: Add function to raise the big CPU frequency Implement mt_pll_raise_ca76_freq() in MT8192 to raise the frequency. usage: mt_pll_raise_ca76_freq(2200UL * MHz); Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I2ebc4c0230e7c42c887bdac227eb366deb743986 --- M src/soc/mediatek/common/include/soc/pll_common.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/46410/1 diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index d9ba230..54b12e8 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -59,6 +59,7 @@ int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); void mt_pll_raise_little_cpu_freq(u32 freq); +void mt_pll_raise_ca76_freq(u32 freq); enum fmeter_type { FMETER_ABIST = 0, diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 0366cd6..cd65d25 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -546,3 +546,30 @@ return 0; } + +void mt_pll_raise_ca76_freq(u32 freq) +{ + /* enable [4] intermediate clock armpll_divider_pll1_ck */ + setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); + + /* switch ca76 clock source to intermediate clock */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, + MCU_MUX_SRC_DIV_PLL1); + + /* disable armpll_bl frequency output */ + clrbits32(plls[APMIXED_ARMPLL_BL].reg, PLL_EN); + + /* raise armpll_bl frequency */ + pll_set_rate(&plls[APMIXED_ARMPLL_BL], freq); + + /* enable armpll_bl frequency output */ + setbits32(plls[APMIXED_ARMPLL_BL].reg, PLL_EN); + udelay(PLL_EN_DELAY); + + /* switch ca76 clock source back to armpll_bl */ + clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, + MCU_MUX_SRC_PLL); + + /* disable [4] intermediate clock armpll_divider_pll1_ck */ + clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ebc4c0230e7c42c887bdac227eb366deb743986 Gerrit-Change-Number: 46410 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/generic: Set SW0 to 3 for wake device
by Edward O'Callaghan (Code Review) 03 May '21

03 May '21

Attention is currently required from: Furquan Shaikh, Tony Huang, Keith Tzeng, Wisley Chen. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52847 ) Change subject: drivers/i2c/generic: Set SW0 to 3 for wake device ...................................................................... Patch Set 1: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52847/comment/15a1de0c_8103a4f6 PS1, Line 9: 3 Only because this commit impacts many boards can you elaborate a little more why `3` and not `4` to help if someone does need to bisect back to this for their board. File src/drivers/i2c/generic/generic.c: https://review.coreboot.org/c/coreboot/+/52847/comment/9fc7b4b0_7d07adcd PS1, Line 101: 3); please update `Documentation/acpi/devicetree.md` as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/52847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a Gerrit-Change-Number: 52847 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Keith Tzeng <keith.tzeng(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 May 2021 05:44:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Use set_dev_state_by_devicetree()
by build bot (Jenkins) (Code Review) 03 May '21

03 May '21

Attention is currently required from: Michael Niewöhner, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52810 ) Change subject: soc/intel/skylake: Use set_dev_state_by_devicetree() ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/skylake/chip.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-118206): https://review.coreboot.org/c/coreboot/+/52810/comment/b8699626_3d34a651 PS6, Line 461: if (!xdci_can_enable()) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/52810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75088098a4cceea2e860ca97c4853d2e5279c2f2 Gerrit-Change-Number: 52810 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 03 May 2021 05:24:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Use set_dev_state_by_devicetree()
by Felix Singer (Code Review) 03 May '21

03 May '21

Attention is currently required from: Michael Niewöhner, Patrick Rudolph. Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52810 to look at the new patch set (#6). Change subject: soc/intel/skylake: Use set_dev_state_by_devicetree() ...................................................................... soc/intel/skylake: Use set_dev_state_by_devicetree() Change-Id: I75088098a4cceea2e860ca97c4853d2e5279c2f2 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/romstage/fsp_params.c 2 files changed, 35 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/52810/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/52810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75088098a4cceea2e860ca97c4853d2e5279c2f2 Gerrit-Change-Number: 52810 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: add pmif/spmi/pmic driver
by Yidi Lin (Code Review) 03 May '21

03 May '21

Attention is currently required from: Hung-Te Lin, Paul Menzel, Rex-BC Chen. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52668 ) Change subject: soc/mediatek/mt8195: add pmif/spmi/pmic driver ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52668/comment/d2d651c9_15f64db5 PS3, Line 9: MT8195 > What is the difference to `mediatek/mt8192`? The code looks similar. The IO pins, clock setting and PMIC setting related to SoC are difference from MT8192. The common parts are moved to common/ folder. File src/soc/mediatek/mt8195/mt6315.c: https://review.coreboot.org/c/coreboot/+/52668/comment/8e7a5f45_ab8a954d PS3, Line 6: /* disable magic key protection */ > What does that mean? Please reference the datasheet name and section. The setting is the PMIC internal setting. The values are simulation results provided by IC designer. The setting is unique to different MediaTek SoC and can't be customized. We have datasheets for MT6315 and MT6359p. But those settings won't be disclosed. File src/soc/mediatek/mt8195/pmif_clk.c: PS3: > This looks very similar to `src/soc/mediatek/mt8192/pmif_clk.c`. Please do not duplicate code. The clock register and bit definition are different to mt8192 even though it looks very similar to `mt8192/pmif_clk.c`. We prefer keeping a complete pmif_clk.c in mt8195/ folder for maintenance. -- To view, visit https://review.coreboot.org/c/coreboot/+/52668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Gerrit-Change-Number: 52668 Gerrit-PatchSet: 3 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 May 2021 04:35:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]: soc/amd/cezanne: Generate PCI routing table
by Yu-hsuan Hsu (Code Review) 03 May '21

03 May '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Eric Peers, Karthik Ramasubramanian, Felix Held. Yu-hsuan Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51556 ) Change subject: [WIP]: soc/amd/cezanne: Generate PCI routing table ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hi Raul, when do you plan to merge this patch? We need this patch to enable audio function on Guybrush. See https://b.corp.google.com/issues/184617007#comment33 for more information. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/51556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Gerrit-Change-Number: 51556 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Yu-hsuan Hsu <yuhsuan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 03 May 2021 04:10:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: devapc: update domain remap setting
by Nina-CM Wu (Code Review) 03 May '21

03 May '21

Attention is currently required from: Xi Chen, Yu-Ping Wu. Nina-CM Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52705 ) Change subject: soc/mediatek/mt8192: devapc: update domain remap setting ...................................................................... Patch Set 4: (1 comment) File src/soc/mediatek/mt8192/devapc.c: https://review.coreboot.org/c/coreboot/+/52705/comment/0360f398_ef54fb07 PS2, Line 86: /* > Sorry, no, what I meant is the first line of the comment. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa9e75db85482a6c016b8b423c0b05f97e585b1 Gerrit-Change-Number: 52705 Gerrit-PatchSet: 4 Gerrit-Owner: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 03 May 2021 03:20:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: devapc: update domain remap setting
by Nina-CM Wu (Code Review) 03 May '21

03 May '21

Attention is currently required from: Nina-CM Wu, Xi Chen. Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52705 to look at the new patch set (#4). Change subject: soc/mediatek/mt8192: devapc: update domain remap setting ...................................................................... soc/mediatek/mt8192: devapc: update domain remap setting Update domain remap setting to prevent DSP (domain 4) from accessing registers. Change-Id: Iefa9e75db85482a6c016b8b423c0b05f97e585b1 Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> --- M src/soc/mediatek/mt8192/devapc.c M src/soc/mediatek/mt8192/include/soc/devapc.h 2 files changed, 54 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/52705/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa9e75db85482a6c016b8b423c0b05f97e585b1 Gerrit-Change-Number: 52705 Gerrit-PatchSet: 4 Gerrit-Owner: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8192: devapc: update domain remap setting
by Yu-Ping Wu (Code Review) 03 May '21

03 May '21

Attention is currently required from: Nina-CM Wu, Xi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52705 ) Change subject: soc/mediatek/mt8192: devapc: update domain remap setting ...................................................................... Patch Set 3: (1 comment) File src/soc/mediatek/mt8192/devapc.c: https://review.coreboot.org/c/coreboot/+/52705/comment/c15609e2_6cda0027 PS2, Line 86: /* > Done Sorry, no, what I meant is the first line of the comment. The first sentence should be moved to the second line. -- To view, visit https://review.coreboot.org/c/coreboot/+/52705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefa9e75db85482a6c016b8b423c0b05f97e585b1 Gerrit-Change-Number: 52705 Gerrit-PatchSet: 3 Gerrit-Owner: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Comment-Date: Mon, 03 May 2021 03:15:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nina-CM Wu <nina-cm.wu(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/vilboz: Disable HDMI 2.0 for Vilboz
by Kangheui Won (Code Review) 03 May '21

03 May '21

Attention is currently required from: Frank Wu, Martin Roth, Chris Wang, EricR Lai. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52724 ) Change subject: mb/google/zork/vilboz: Disable HDMI 2.0 for Vilboz ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0dc0d584f0e87bc9c3da85a583cb8c8bed76440 Gerrit-Change-Number: 52724 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Huang <patrick.huang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 May 2021 02:04:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2021